void
main(void)
{
memset(edata, 0, (ulong)end-(ulong)edata);
conf.nmach = 1;
machinit();
confinit();
xinit();
trapinit();
mmuinit();
plan9iniinit();
hwintrinit();
clockinit();
timerinit();
console();
quotefmtinstall();
printinit();
cpuidprint();
print("\nPlan 9 from Bell Labs\n");
procinit0();
initseg();
timersinit();
links();
chandevreset();
pageinit();
swapinit();
sharedseginit();
fpsave(&initfp);
initfp.fpscr = 0;
userinit();
schedinit();
}
/**
* Intializes all XINU data structures and devices.
* @return OK if everything is initialized successfully
*/
local sysinit(void)
{
int i = 0;
pcb *ppcb = NULL; /* process control block pointer */
semblk *psem = NULL; /* semaphore block pointer */
memblk *pmem = NULL; /* memory block pointer */
/* Initialize system variables */
/* Count this NULLPROC as the first process in the system. */
numproc = 1;
/* Initialize free memory list */
freelist.next = pmem = (memblk *) roundmb(minheap);
freelist.length = (ulong)truncew((ulong)platform.maxaddr - (ulong)minheap);
pmem->next = NULL;
pmem->length = freelist.length;
/* Initialize process table */
for (i = 0; i < NPROC; i++)
{ proctab[i].state = PRFREE; }
/* initialize null process entry */
ppcb = &proctab[NULLPROC];
ppcb->state = PRCURR;
strncpy(ppcb->name, "prnull", 7);
ppcb->stkbase = (void *)&end;
ppcb->stkptr = NULL;
ppcb->stklen = (ulong)minheap - (ulong)&end;
ppcb->priority = 0;
currpid = NULLPROC;
/* Initialize semaphores */
for (i = 0; i < NSEM; i++)
{
psem = &semtab[i];
psem->state = SFREE;
psem->count = 0;
psem->queue = newqueue();
}
/* initialize bounded-waiting mutex subsystems */
mutexInit();
/* initialize process ready list */
readylist = newqueue();
#if RTCLOCK
/* initialize real time clock */
clockinit();
#endif
return OK;
}
void
main(void)
{
extern char edata[], end[];
uint rev;
okay(1);
m = (Mach*)MACHADDR;
memset(edata, 0, end - edata); /* clear bss */
machinit();
mmuinit1();
optionsinit("/boot/boot boot");
quotefmtinstall();
ataginit((Atag*)BOOTARGS);
confinit(); /* figures out amount of memory */
xinit();
uartconsinit();
screeninit();
print("\nPlan 9 from Bell Labs\n");
rev = getfirmware();
print("firmware: rev %d\n", rev);
if(rev < Minfirmrev){
print("Sorry, firmware (start.elf) must be at least rev %d (%s)\n",
Minfirmrev, Minfirmdate);
for(;;)
;
}
trapinit();
clockinit();
printinit();
timersinit();
cpuidprint();
archreset();
procinit0();
initseg();
links();
chandevreset(); /* most devices are discovered here */
pageinit();
swapinit();
userinit();
gpiomeminit();
schedinit();
assert(0); /* shouldn't have returned */
}
void
main(void)
{
hwrpb = (Hwrpb*)0x10000000;
hwrpb = (Hwrpb*)(KZERO|hwrpb->phys);
arginit();
machinit();
options();
ioinit();
clockinit();
confinit();
archinit();
xinit();
memholes();
if(i8237alloc != nil)
i8237alloc();
mmuinit();
if(arch->coreinit)
arch->coreinit();
trapinit();
screeninit();
printinit();
/* it's now safe to print */
/* dumpopts(); /* DEBUG */
i8250console();
quotefmtinstall();
print("\nPlan 9\n");
cpuidprint();
if(arch->corehello)
arch->corehello();
procinit0();
initseg();
timersinit();
links();
chandevreset();
pageinit();
swapinit();
savefpregs(&initfp);
initfp.fpstatus = 0x68028000;
userinit();
schedinit();
}
void
main(void)
{
machinit();
trapinit();
quotefmtinstall();
confinit();
xinit();
mmuinit();
intrinit();
clockinit();
printinit();
screeninit();
ioinit();
doc("ioinit...");
ns16552install();
poolsizeinit();
doc("ns16552install...");
kbdinit();
doc("kbdinit...");
cacheinit();
doc("cacheinit...");
procinit();
doc("procinit...");
putphys(MID, 0x1F<<16); /* enable arbitration */
links();
doc("links");
chandevreset();
doc("chandevreset...");
print("\nInferno Operating System\n");
print("%s-%s \n\n",VERSION, conffile);
print("JIT Compilation Mode = %d\n",cflag);
userinit();
doc("userinit...");
/* clear pending processor interrupts */
putphys(PROCINTCLR, (~0<<17)|(1<<15));
print("berore schedinit\n");
schedinit();
}
void
main(void)
{
machinit();
options();
archinit();
quotefmtinstall();
confinit();
cpminit();
xinit();
poolsizeinit();
trapinit();
mmuinit();
printinit();
uartinstall();
serialconsole();
doc("screeninit");
screeninit();
doc("kbdinit");
kbdinit();
doc("clockinit");
clockinit();
doc("procinit");
procinit();
cpuidprint();
doc("links");
links();
doc("chandevreset");
chandevreset();
eve = strdup("inferno");
print("\nInferno %s\n", VERSION);
print("Vita Nuova\n");
print("conf %s (%lud) jit %d\n\n",conffile, kerndate, cflag);
doc("userinit");
userinit();
doc("schedinit");
schedinit();
}
void
main(void)
{
mmuinvalidate();
/* zero out bss */
memset(edata, 0, end-edata);
/* point to Mach structure */
m = (Mach*)MACHADDR;
memset(m, 0, sizeof(Mach));
m->ticks = 1;
active.machs = 1;
rs232power(1);
quotefmtinstall();
iprint("\nPlan 9 bitsy kernel\n");
confinit();
xinit();
mmuinit();
machinit();
trapinit();
sa1110_uartsetup(1);
dmainit();
screeninit();
printinit(); /* from here on, print works, before this we need iprint */
clockinit();
procinit0();
initseg();
links();
chandevreset();
pageinit();
swapinit();
userinit();
powerinit();
schedinit();
}
/**
* Intializes all XINU data structures and devices.
* @return OK if everything is initialized successfully
*/
local sysinit(void)
{
int i = 0;
pcb *ppcb = NULL; /* process control block pointer */
/* Initialize system variables */
/* Count this NULLPROC as the first process in the system. */
numproc = 1;
/* Initialize process table */
for (i = 0; i < NPROC; i++)
{ proctab[i].state = PRFREE; }
/* initialize null process entry */
ppcb = &proctab[NULLPROC];
ppcb->state = PRCURR;
strncpy(ppcb->name, "prnull", 7);
ppcb->stkbase = (void *)&end;
ppcb->stkptr = NULL;
ppcb->stklen = (ulong)minheap - (ulong)&end;
/* TODO: This line won't compile properly until you have added
* a priority field to the process control block.
*/
ppcb->priority = 0;
currpid = NULLPROC;
/* initialize process ready list */
readylist = newqueue();
#if RTCLOCK
/* initialize real time clock */
clockinit();
#endif
return OK;
}
/*
* called on a cpu other than 0 from cpureset in l.s,
* from _vrst in lexception.s.
* mmu and l1 (and system-wide l2) caches and coherency (smpon) are on,
* but interrupts are disabled.
* our mmu is using an exact copy of cpu0's l1 page table
* as it was after userinit ran.
*/
void
cpustart(void)
{
int ms;
ulong *evp;
Power *pwr;
up = nil;
if (active.machs & (1<<m->machno)) {
serialputc('?');
serialputc('r');
panic("cpu%d: resetting after start", m->machno);
}
assert(m->machno != 0);
errata();
cortexa9cachecfg();
memdiag(&testmem);
machinit(); /* bumps nmach, adds bit to machs */
machoff(m->machno); /* not ready to go yet */
/* clock signals and scu are system-wide and already on */
clockshutdown(); /* kill any watch-dog timer */
trapinit();
clockinit(); /* sets loop delay */
timersinit();
cpuidprint();
/*
* notify cpu0 that we're up so it can proceed to l1diag.
*/
evp = (ulong *)soc.exceptvec; /* magic */
*evp = m->machno;
coherence();
l1diag(); /* contend with other cpus to verify sanity */
/*
* pwr->noiopwr == 0
* pwr->detect == 0x1ff (default, all disabled)
*/
pwr = (Power *)soc.power;
assert(pwr->gatests == MASK(7)); /* everything has power */
/*
* 8169 has to initialise before we get past this, thus cpu0
* has to schedule processes first.
*/
if (Debug)
iprint("cpu%d: waiting for 8169\n", m->machno);
for (ms = 0; !l1ptstable.word && ms < 5000; ms += 10) {
delay(10);
cachedinvse(&l1ptstable.word, sizeof l1ptstable.word);
}
if (!l1ptstable.word)
iprint("cpu%d: 8169 unreasonably slow; proceeding\n", m->machno);
/* now safe to copy cpu0's l1 pt in mmuinit */
mmuinit(); /* update our l1 pt from cpu0's */
fpon();
machon(m->machno); /* now ready to go and be scheduled */
if (Debug)
iprint("cpu%d: scheding\n", m->machno);
schedinit();
panic("cpu%d: schedinit returned", m->machno);
}
/*
* entered from l.s with mmu enabled.
*
* we may have to realign the data segment; apparently 5l -H0 -R4096
* does not pad the text segment. on the other hand, we may have been
* loaded by another kernel.
*
* be careful not to touch the data segment until we know it's aligned.
*/
void
main(Mach* mach)
{
extern char bdata[], edata[], end[], etext[];
static ulong vfy = 0xcafebabe;
m = mach;
if (vfy != 0xcafebabe)
memmove(bdata, etext, edata - bdata);
if (vfy != 0xcafebabe) {
wave('?');
panic("misaligned data segment");
}
memset(edata, 0, end - edata); /* zero bss */
vfy = 0;
wave('9');
machinit();
archreset();
mmuinit();
optionsinit("/boot/boot boot");
quotefmtinstall();
archconsole();
wave(' ');
/* want plan9.ini to be able to affect memory sizing in confinit */
plan9iniinit(); /* before we step on plan9.ini in low memory */
/* set memsize before xinit */
confinit();
/* xinit would print if it could */
xinit();
/*
* Printinit will cause the first malloc call.
* (printinit->qopen->malloc) unless any of the
* above (like clockintr) do an irqenable, which
* will call malloc.
* If the system dies here it's probably due
* to malloc(->xalloc) not being initialised
* correctly, or the data segment is misaligned
* (it's amazing how far you can get with
* things like that completely broken).
*
* (Should be) boilerplate from here on.
*/
trapinit();
clockinit();
printinit();
uartkirkwoodconsole();
/* only now can we print */
print("from Bell Labs\n\n");
#ifdef CRYPTOSANDBOX
print("sandbox: 64K at physical %#lux, mapped to 0xf10b0000\n",
PADDR((uintptr)sandbox & ~(BY2PG-1)));
#endif
archconfinit();
cpuidprint();
timersinit();
procinit0();
initseg();
links();
chandevreset(); /* most devices are discovered here */
spiprobe();
pageinit();
swapinit();
userinit();
schedinit();
panic("schedinit returned");
}
/*
* at entry, l.s has set m for cpu0 and printed "Plan 9 from Be"
* but has not zeroed bss.
*/
void
main(void)
{
int cpu;
static ulong vfy = 0xcafebabe;
up = nil;
if (vfy != 0xcafebabe) {
serialputc('?');
serialputc('d');
panic("data segment misaligned");
}
memset(edata, 0, end - edata);
/*
* we can't lock until smpon has run, but we're supposed to wait
* until l1 & l2 are on. too bad. l1 is on, l2 will soon be.
*/
smpon();
iprint("ll Labs ");
cacheinit();
/*
* data segment is aligned, bss is zeroed, caches' characteristics
* are known. begin initialisation.
*/
mach0init();
l2pageinit();
mmuinit();
optionsinit("/boot/boot boot");
quotefmtinstall();
/* want plan9.ini to be able to affect memory sizing in confinit */
plan9iniinit(); /* before we step on plan9.ini in low memory */
/* l2 looks for *l2off= in plan9.ini */
l2cache->on(); /* l2->on requires locks to work, thus smpon */
l2cache->info(&cachel[2]);
allcache->on();
cortexa9cachecfg();
trapinit(); /* so confinit can probe memory to size it */
confinit(); /* figures out amount of memory */
/* xinit prints (if it can), so finish up the banner here. */
delay(100);
navailcpus = getncpus();
iprint("(mp arm; %d cpus)\n\n", navailcpus);
delay(100);
for (cpu = 1; cpu < navailcpus; cpu++)
stopcpu(cpu);
xinit();
irqtooearly = 0; /* now that xinit and trapinit have run */
mainmem->flags |= POOL_ANTAGONISM /* | POOL_PARANOIA */ ;
/*
* Printinit will cause the first malloc call.
* (printinit->qopen->malloc) unless any of the
* above (like clockinit) do an irqenable, which
* will call malloc.
* If the system dies here it's probably due
* to malloc(->xalloc) not being initialised
* correctly, or the data segment is misaligned
* (it's amazing how far you can get with
* things like that completely broken).
*
* (Should be) boilerplate from here on.
*/
archreset(); /* cfg clock signals, print cache cfg */
clockinit(); /* start clocks */
timersinit();
delay(50); /* let uart catch up */
printinit();
kbdenable();
cpuidprint();
chkmissing();
procinit0();
initseg();
// dmainit();
links();
conf.monitor = 1;
// screeninit();
iprint("pcireset...");
pcireset(); /* this tends to hang after a reboot */
iprint("ok\n");
chandevreset(); /* most devices are discovered here */
// i8250console(); /* too early; see init0 */
pageinit(); /* prints "1020M memory: ⋯ */
swapinit();
userinit();
/*
* starting a cpu will eventually result in it calling schedinit,
* so everything necessary to run user processes should be set up
* before starting secondary cpus.
*/
launchinit();
/* SMP & FW are already on when we get here; u-boot set them? */
for (cpu = 1; cpu < navailcpus; cpu++)
if (startcpu(cpu) < 0)
panic("cpu%d didn't start", cpu);
l1diag();
schedinit();
panic("cpu%d: schedinit returned", m->machno);
}
void
main() {
uint j=0,i=0,k=0;
uint rev;
ulong pc;
pc = getpc();
pl011_addr((void *)pc, 1);
pl011_puts("Entered main() at ");
pl011_addr(&main, 0);
pl011_puts(" with SP=");
pl011_addr((void *)getsp(), 0);
pl011_puts(" with SC=");
pl011_addr((void *)getsc(), 0);
pl011_puts(" with CPSR=");
pl011_addr((void *)getcpsr(), 0);
pl011_puts(" with SPSR=");
pl011_addr((void *)getspsr(), 1);
pl011_puts("Clearing Mach: ");
memset(m, 0, sizeof(Mach));
pl011_addr((char *)m, 0); pl011_puts("-");
pl011_addr((char *)(m+1), 1);
pl011_puts("Clearing edata: ");
memset(edata, 0, end-edata);
pl011_addr((char *)&edata, 0); pl011_puts("-");
pl011_addr((char *)&end, 1);
conf.nmach = 1;
quotefmtinstall();
confinit();
mmuinit1();
xinit();
poolinit();
poolsizeinit();
//uartconsinit();
screeninit();
trapinit();
timersinit();
clockinit();
printinit();
swcursorinit();
rev = getfirmware();
print("\nARM %ld MHz id %8.8lux firmware: rev %d, mem: %ld\n"
,(m->cpuhz+500000)/1000000, getcpuid(), rev, conf.topofmem/MB);
print("Inferno OS %s Vita Nuova\n", VERSION);
print("Ported to Raspberry Pi (BCM2835) by LynxLine\n\n");
procinit();
links();
chandevreset();
eve = strdup("inferno");
userinit();
schedinit();
pl011_puts("to inifinite loop\n\n");
for (;;);
}
void
main(void)
{
int machno;
/* entry to main pushed stuff onto the stack. */
// memset(edata, 0, (ulong)end-(ulong)edata);
machno = getpir();
if (machno > 0)
startcpu(machno);
// dcrcompile();
if (dverify != 0x01020304) {
uartlputs("data segment not initialised\n");
panic("data segment not initialised");
}
if (bverify != 0) {
uartlputs("bss segment not zeroed\n");
panic("bss segment not zeroed");
}
mach0init();
archreset();
quotefmtinstall();
optionsinit("/boot/boot boot");
// archconsole();
meminit();
confinit();
mmuinit();
xinit(); /* xinit would print if it could */
trapinit();
qtminit();
ioinit();
uncinit();
printinit();
uartliteconsole();
mainmem->flags |= POOL_ANTAGONISM;
mainmem->panic = mypanic;
ethermedium.maxtu = 1512; /* must be multiple of 4 for temac's dma */
// print("\n\nPlan 9k H\n"); /* already printed by l.s */
plan9iniinit();
timersinit();
clockinit();
dma0init(); /* does not start kprocs; see init0 */
fpuinit();
procinit0();
initseg();
links();
chandevreset();
okprint = 1; /* only now can we print */
barriers();
dcflush((uintptr)&okprint, sizeof okprint);
cpuidprint();
print("%d Hz clock", HZ);
print("; memory size %,ud (%#ux)\n", (uint)memsz, (uint)memsz);
pageinit();
swapinit();
userinit();
active.thunderbirdsarego = 1;
dcflush((uintptr)&active.thunderbirdsarego,
sizeof active.thunderbirdsarego);
schedinit();
/* no return */
panic("schedinit returned");
}
void
main(void)
{
// int i;
extern char bdata[], edata[], end[], etext[];
static ulong vfy = 0xcafebabe;
/* l.s has already printed "Plan 9 from Be" */
// m = mach; /* now done in l.s */
/* realign data seg; apparently -H0 -R4096 does not pad the text seg */
if (vfy != 0xcafebabe) {
// wave('<'); wave('-');
memmove(bdata, etext, edata - bdata);
}
/*
* once data segment is in place, always zero bss since we may
* have been loaded by another Plan 9 kernel.
*/
memset(edata, 0, end - edata); /* zero BSS */
cacheuwbinv();
l2cacheuwbinv();
if (vfy != 0xcafebabe)
panic("data segment misaligned");
vfy = 0;
wave('l');
machinit();
mmuinit();
optionsinit("/boot/boot boot");
quotefmtinstall();
/* want plan9.ini to be able to affect memory sizing in confinit */
plan9iniinit(); /* before we step on plan9.ini in low memory */
trapinit(); /* so confinit can probe memory to size it */
confinit(); /* figures out amount of memory */
/* xinit prints (if it can), so finish up the banner here. */
delay(500);
iprint("l Labs\n\n");
delay(500);
xinit();
mainmem->flags |= POOL_ANTAGONISM /* | POOL_PARANOIA */ ;
/*
* Printinit will cause the first malloc call.
* (printinit->qopen->malloc) unless any of the
* above (like clockinit) do an irqenable, which
* will call malloc.
* If the system dies here it's probably due
* to malloc(->xalloc) not being initialised
* correctly, or the data segment is misaligned
* (it's amazing how far you can get with
* things like that completely broken).
*
* (Should be) boilerplate from here on.
*/
archreset(); /* configure clock signals */
clockinit(); /* start clocks */
timersinit();
watchdoginit();
delay(250); /* let uart catch up */
printinit();
// kbdenable();
cpuidprint();
// chkmissing();
procinit0();
initseg();
dmainit();
links();
conf.monitor = 1;
screeninit();
chandevreset(); /* most devices are discovered here */
// i8250console(); /* too early; see init0 */
pageinit();
swapinit();
userinit();
schedinit();
}
