static void __init cns3420_init(void)
{
cns3xxx_l2x0_init();
platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs));
cns3xxx_ahci_init();
cns3xxx_sdhci_init();
pm_power_off = cns3xxx_power_off;
}
static void __init cns3xxx_init(void)
{
struct device_node *dn;
cns3xxx_l2x0_init();
dn = of_find_compatible_node(NULL, NULL, "cavium,cns3420-ahci");
if (of_device_is_available(dn)) {
u32 tmp;
tmp = __raw_readl(MISC_SATA_POWER_MODE);
tmp |= 0x1 << 16; /* Disable SATA PHY 0 from SLUMBER Mode */
tmp |= 0x1 << 17; /* Disable SATA PHY 1 from SLUMBER Mode */
__raw_writel(tmp, MISC_SATA_POWER_MODE);
/* Enable SATA PHY */
cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0);
cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1);
/* Enable SATA Clock */
cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_SATA);
/* De-Asscer SATA Reset */
cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SATA));
}
dn = of_find_compatible_node(NULL, NULL, "cavium,cns3420-sdhci");
if (of_device_is_available(dn)) {
u32 __iomem *gpioa = IOMEM(CNS3XXX_MISC_BASE_VIRT + 0x0014);
u32 gpioa_pins = __raw_readl(gpioa);
/* MMC/SD pins share with GPIOA */
gpioa_pins |= 0x1fff0004;
__raw_writel(gpioa_pins, gpioa);
cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO));
cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SDIO));
}
pm_power_off = cns3xxx_power_off;
of_platform_populate(NULL, of_default_bus_match_table,
cns3xxx_auxdata, NULL);
}
static void __init cns3xxx_init(void)
{
int i;
#ifdef CONFIG_CACHE_L2X0
/* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled
* Bits: .... ...0 0111 1001 0000 .... .... .... */
cns3xxx_l2x0_init();
#endif
#ifdef CONFIG_CACHE_L2CC
l2cc_init((void __iomem *) CNS3XXX_L2C_BASE_VIRT);
#endif
#ifdef CONFIG_CNS3XXX_DMAC
dmac_init();
#endif
#ifdef CONFIG_CNS3XXX_RAID
cns_rdma_init();
#endif
show_board_version();
{
volatile unsigned long *pciecfg0;
pciecfg0 = (volatile unsigned long *)CNS3XXX_PCIE0_CFG0_BASE_VIRT;
pciecfg0[1] |= 7;
printk("usec at kernel start: 0x%08lX\n", *(volatile unsigned long *)(CNS3XXX_PCIE0_MEM_BASE_VIRT+0x14));
}
ts43xx_ahci_init();
for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
struct amba_device *d = amba_devs[i];
int ret;
cns3xxx_pwr_power_up(CNS3XXX_PWR_PLL(PLL_LCD));
cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(LCDC));
cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(LCDC));
ret = amba_device_register(d, &iomem_resource);
if(ret)
printk("%s=>%d: %d\n", __FUNCTION__, __LINE__, ret);
}
platform_add_devices(cns3xxx_devs, ARRAY_SIZE(cns3xxx_devs));
lm_device_register(&cns3xxx_usb_otg_device);
i2c_register_board_info(0, cns3xxx_i2c_devices, ARRAY_SIZE(cns3xxx_i2c_devices));
i2c_register_board_info(1, cns3xxx_i2c_gpio_devices, ARRAY_SIZE(cns3xxx_i2c_gpio_devices));
spi_register_board_info(cns3xxx_spi_devices, ARRAY_SIZE(cns3xxx_spi_devices));
cns3xxx_proc_dir = proc_mkdir("cns3xxx", NULL);
#ifdef CONFIG_DEBUG_FS
cns3xxx_debugfs_dir = debugfs_create_dir("cns3xxx", NULL);
#endif
#ifdef CONFIG_CACHE_L2CC
l2cc_proc_init();
#endif
pm_power_off = cns3xxx_power_off;
}
