void
ingenic_putchar_init(void)
{
/*
* XXX don't screw with the UART's speed until we know what clock
* we're on
*/
#if 0
int rate;
#endif
extern int comspeed(long, long, int);
com0addr = (uint32_t *)MIPS_PHYS_TO_KSEG1(JZ_UART0);
#if 0
if (comcnfreq != -1) {
rate = comspeed(comcnspeed, comcnfreq, COM_TYPE_INGENIC);
if (rate < 0)
return; /* XXX */
#endif
com0addr[com_ier] = 0;
com0addr[com_lctl] = htole32(LCR_DLAB);
#if 0
com0addr[com_dlbl] = htole32(rate & 0xff);
com0addr[com_dlbh] = htole32(rate >> 8);
#endif
com0addr[com_lctl] = htole32(LCR_8BITS); /* XXX */
com0addr[com_mcr] = htole32(MCR_DTR|MCR_RTS);
com0addr[com_fifo] = htole32(
FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST |
FIFO_TRIGGER_1 | FIFO_UART_ON);
#if 0
}
int
cnspeed(dev_t dev, int sp)
{
if (major(dev) == 8) /* comN */
return comspeed(dev, sp);
/* pc0 and anything else */
return 9600;
}
int
cnspeed(dev_t dev, int sp)
{
if (major(dev) == 12) /* comN */
return (comspeed(dev, sp));
/* cn0 or anything else */
return (9600);
}
void
com_init(struct consdev *cn)
{
int rate;
OUTB(com_cfcr, LCR_DLAB);
rate = comspeed(CONSPEED);
OUTB(com_dlbl, rate);
OUTB(com_dlbh, rate >> 8);
OUTB(com_cfcr, LCR_8BITS);
OUTB(com_mcr, MCR_DTR | MCR_RTS);
OUTB(com_fifo,
FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1);
OUTB(com_ier, 0);
}
void
com_resume(struct com_softc *sc)
{
struct tty *tp = sc->sc_tty;
bus_space_tag_t iot = sc->sc_iot;
bus_space_handle_t ioh = sc->sc_ioh;
int ospeed;
if (!tp || !ISSET(tp->t_state, TS_ISOPEN)) {
#ifdef COM_CONSOLE
if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE))
cominit(iot, ioh, comconsrate, comconsfreq);
#endif
return;
}
/*
* Wake up the sleepy heads.
*/
if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) {
switch (sc->sc_uarttype) {
case COM_UART_ST16650:
case COM_UART_ST16650V2:
bus_space_write_1(iot, ioh, com_lcr, LCR_EFR);
bus_space_write_1(iot, ioh, com_efr, EFR_ECB);
bus_space_write_1(iot, ioh, com_ier, 0);
bus_space_write_1(iot, ioh, com_efr, 0);
bus_space_write_1(iot, ioh, com_lcr, 0);
break;
case COM_UART_TI16750:
bus_space_write_1(iot, ioh, com_ier, 0);
break;
case COM_UART_PXA2X0:
bus_space_write_1(iot, ioh, com_ier, IER_EUART);
break;
}
}
ospeed = comspeed(sc->sc_frequency, tp->t_ospeed);
if (ospeed != 0) {
bus_space_write_1(iot, ioh, com_lcr, sc->sc_lcr | LCR_DLAB);
bus_space_write_1(iot, ioh, com_dlbl, ospeed);
bus_space_write_1(iot, ioh, com_dlbh, ospeed >> 8);
bus_space_write_1(iot, ioh, com_lcr, sc->sc_lcr);
} else {
volatile struct NS16550 *
NS16550_init(int addr, int speed)
{
struct NS16550 *com_port;
com_port = (struct NS16550 *)(COMBASE + addr);
com_port->lcr = 0x80; /* Access baud rate */
speed = comspeed(speed);
com_port->dll = speed;
com_port->dlm = speed >> 8;
com_port->lcr = 0x03; /* 8 data, 1 stop, no parity */
com_port->mcr = 0x03; /* Set DTR and RTS */
com_port->fcr = 0x07; /* Clear & enable FIFOs */
com_port->ier = 0x00;
return (com_port);
}
static int
comparam(struct tty *tp, struct termios *t)
{
struct com_softc *sc = device_lookup_private(&xcom_cd, COMUNIT(tp->t_dev));
int iobase = sc->sc_iobase;
int ospeed = comspeed(t->c_ospeed);
u_char lcr;
tcflag_t oldcflag;
int s;
/* check requested parameters */
if (ospeed < 0 || (t->c_ispeed && t->c_ispeed != t->c_ospeed))
return EINVAL;
lcr = ISSET(sc->sc_lcr, LCR_SBREAK);
switch (ISSET(t->c_cflag, CSIZE)) {
case CS5:
SET(lcr, LCR_5BITS);
break;
case CS6:
SET(lcr, LCR_6BITS);
break;
case CS7:
SET(lcr, LCR_7BITS);
break;
case CS8:
SET(lcr, LCR_8BITS);
break;
}
if (ISSET(t->c_cflag, PARENB)) {
SET(lcr, LCR_PENAB);
if (!ISSET(t->c_cflag, PARODD))
SET(lcr, LCR_PEVEN);
}
if (ISSET(t->c_cflag, CSTOPB))
SET(lcr, LCR_STOPB);
sc->sc_lcr = lcr;
s = spltty();
if (ospeed == 0) {
CLR(sc->sc_mcr, MCR_DTR);
outb(pio(iobase , com_mcr), sc->sc_mcr);
}
/*
* Set the FIFO threshold based on the receive speed, if we are
* changing it.
*/
if (tp->t_ispeed != t->c_ispeed) {
if (ISSET(sc->sc_hwflags, COM_HW_FIFO))
outb(pio(iobase , com_fifo),
FIFO_ENABLE |
(t->c_ispeed <= 1200 ? FIFO_TRIGGER_1 : FIFO_TRIGGER_8));
}
if (ospeed != 0) {
outb(pio(iobase , com_lcr), lcr | LCR_DLAB);
outb(pio(iobase , com_dlbl), ospeed);
outb(pio(iobase , com_dlbh), ospeed >> 8);
outb(pio(iobase , com_lcr), lcr);
SET(sc->sc_mcr, MCR_DTR);
outb(pio(iobase , com_mcr), sc->sc_mcr);
} else
