/* Om DM365, Imager and TVP5146 I2C address collide. So we need to
* keep imager on reset when working with tvp5146 and vice-versa
* This function use GIO40 to act as reset to imager
*/
void image_sensor_hw_reset(int state)
{
u32 val1;
if (cpu_is_davinci_dm365()) {
val1 = cpld_read(DM365_CPLD_REGISTER3);
val1 |= DM365_IMAGER_RST_MASK;
cpld_write(val1, DM365_CPLD_REGISTER3);
/* CPLD to Route GPIO to Imager Reset line */
val1 = cpld_read(DM365_CPLD_REGISTER16);
val1 &= ~0x40404040;
cpld_write(val1, DM365_CPLD_REGISTER16);
val1 = cpld_read(DM365_CPLD_REGISTER18);
val1 |= 0x20202020;
cpld_write(val1, DM365_CPLD_REGISTER18);
val1 = cpld_read(DM365_CPLD_REGISTER18);
val1 &= ~0x01010101;
cpld_write(val1, DM365_CPLD_REGISTER18);
#ifndef CONFIG_MTD_CFI /* When NOR flash is use and at 16-bit access mode. GPIO 40 is used as address bus */
/* Pin mux to use GPIO40 */
davinci_cfg_reg(DM365_GPIO40, PINMUX_RESV);
/* Configure GPIO40 to be output and hight */
if (state)
gpio_direction_output(40, 1);
else
gpio_direction_output(40, 0);
#endif
}
}
void cpld_init(struct channel *sc)
{
u32 val;
/* PCRA */
val = SBE_2T3E3_CPLD_VAL_CRC32 |
cpld_val_map[SBE_2T3E3_CPLD_VAL_LOOP_TIMING_SOURCE][sc->h.slot];
cpld_write(sc, SBE_2T3E3_CPLD_REG_PCRA, val);
/* PCRB */
val = 0;
cpld_write(sc, SBE_2T3E3_CPLD_REG_PCRB, val);
/* PCRC */
val = 0;
cpld_write(sc, SBE_2T3E3_CPLD_REG_PCRC, val);
/* PBWF */
val = 0;
cpld_write(sc, SBE_2T3E3_CPLD_REG_PBWF, val);
/* PBWL */
val = 0;
cpld_write(sc, SBE_2T3E3_CPLD_REG_PBWL, val);
/* PLTR */
val = SBE_2T3E3_CPLD_VAL_LCV_COUNTER;
cpld_write(sc, SBE_2T3E3_CPLD_REG_PLTR, val);
udelay(1000);
/* PLCR */
val = 0;
cpld_write(sc, SBE_2T3E3_CPLD_REG_PLCR, val);
udelay(1000);
/* PPFR */
val = 0x55;
cpld_write(sc, SBE_2T3E3_CPLD_REG_PPFR, val);
/* TODO: this doesn't work!!! */
/* SERIAL_CHIP_SELECT */
val = 0;
cpld_write(sc, SBE_2T3E3_CPLD_REG_SERIAL_CHIP_SELECT, val);
/* PICSR */
val = SBE_2T3E3_CPLD_VAL_DMO_SIGNAL_DETECTED |
SBE_2T3E3_CPLD_VAL_RECEIVE_LOSS_OF_LOCK_DETECTED |
SBE_2T3E3_CPLD_VAL_RECEIVE_LOSS_OF_SIGNAL_DETECTED;
cpld_write(sc, SBE_2T3E3_CPLD_REG_PICSR, val);
cpld_start_intr(sc);
udelay(1000);
}
int mt9xxx_set_input_mux(unsigned char channel)
{
int err = 0;
u8 val[2];
u32 val1;
val[0] = 8;
if (cpu_is_davinci_dm644x())
return err;
val[1] = 0x80;
if (cpu_is_davinci_dm355()) {
//Logi err = davinci_i2c_write(2, val, MSP430_I2C_ADDR);
if (err)
return err;
} else if (cpu_is_davinci_dm365()) {
/* Drive TVP5146 Reset to low */
tvp514x_hw_reset(0);
/* drive the sensor reset line high */
image_sensor_hw_reset(1);
/* Set Mux for image sensor */
val1 = cpld_read(DM365_CPLD_REGISTER3);
val1 &= ~DM365_VIDEO_MUX_MASK;
val1 |= DM365_SENSOR_SEL;
cpld_write(val1, DM365_CPLD_REGISTER3);
}
/* For image sensor we need to program I2C switch
* PCA9543A
*/
//Logi val[0] = 0x01;
//Logi davinci_i2c_write(1, val, PCA9543A_I2C_ADDR);
return 0;
}
/* type = 0 for TVP5146 and 1 for Image sensor */
int tvp514x_set_input_mux(unsigned char channel)
{
int err = 0;
u8 val[2];
u32 val1;
val[0] = 8;
val[1] = 0x0;
if (cpu_is_davinci_dm644x())
return err;
/* Logi if (cpu_is_davinci_dm355())
err = davinci_i2c_write(2, val, MSP430_I2C_ADDR);
else */if (cpu_is_davinci_dm365()) {
/* drive the sensor reset line low */
image_sensor_hw_reset(0);
/* set tvp5146 reset line high */
tvp514x_hw_reset(1);
/* Set Mux for TVP5146 */
val1 = cpld_read(DM365_CPLD_REGISTER3);
val1 &= ~DM365_VIDEO_MUX_MASK;
val1 |= DM365_TVP5146_SEL;
cpld_write(val1, DM365_CPLD_REGISTER3);
}
return err;
}
static
int cpld_accesible(void)
{
cpld_init();
cpld_write(AVR_ADDR, 0x02);
return cpld_read(AVR_ADDR) == 0x02;
}
static int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
u32 addr, val;
if (argc < 3)
return CMD_RET_USAGE;
addr = simple_strtoul(argv[2], NULL, 16);
if (!(addr == CPLD_ADDR_VERSION || addr == CPLD_ADDR_MODE ||
addr == CPLD_ADDR_MUX || addr == CPLD_ADDR_HDMI ||
addr == CPLD_ADDR_DIPSW || addr == CPLD_ADDR_RESET)) {
printf("cpld invalid addr\n");
return CMD_RET_USAGE;
}
if (argc == 3 && strcmp(argv[1], "read") == 0) {
printf("0x%x\n", cpld_read(addr));
} else if (argc == 4 && strcmp(argv[1], "write") == 0) {
val = simple_strtoul(argv[3], NULL, 16);
if (addr == CPLD_ADDR_MUX) {
/* never mask SCIFA0 console */
val &= ~MUX_MSK_SCIFA0_USB;
val |= MUX_VAL_SCIFA0_USB;
}
cpld_write(addr, val);
}
return 0;
}
void t3e3_reg_write(struct channel *sc, u32 *reg)
{
u32 i;
switch (reg[0]) {
case SBE_2T3E3_CHIP_21143:
dc_write(sc->addr, reg[1], reg[2]);
break;
case SBE_2T3E3_CHIP_CPLD:
for (i = 0; i < SBE_2T3E3_CPLD_REG_MAX; i++)
if (cpld_reg_map[i][sc->h.slot] == reg[1]) {
cpld_write(sc, i, reg[2]);
break;
}
break;
case SBE_2T3E3_CHIP_FRAMER:
for (i = 0; i < SBE_2T3E3_FRAMER_REG_MAX; i++)
if (t3e3_framer_reg_map[i] == reg[1]) {
exar7250_write(sc, i, reg[2]);
break;
}
break;
case SBE_2T3E3_CHIP_LIU:
for (i = 0; i < SBE_2T3E3_LIU_REG_MAX; i++)
if (t3e3_liu_reg_map[i] == reg[1]) {
exar7300_write(sc, i, reg[2]);
break;
}
break;
}
}
void cpld_stop_intr(struct channel *sc)
{
u32 val;
/* PIER */
val = 0;
cpld_write(sc, SBE_2T3E3_CPLD_REG_PIER, val);
}
void cpld_start_intr(struct channel *sc)
{
u32 val;
/* PIER */
val = SBE_2T3E3_CPLD_VAL_INTERRUPT_FROM_ETHERNET_ENABLE |
SBE_2T3E3_CPLD_VAL_INTERRUPT_FROM_FRAMER_ENABLE;
cpld_write(sc, SBE_2T3E3_CPLD_REG_PIER, val);
}
int tvp7002_set_input_mux(unsigned char channel)
{
u32 val;
val = cpld_read(DM365_CPLD_REGISTER3);
val &= ~DM365_VIDEO_MUX_MASK;
val |= DM365_TVP7002_SEL;
cpld_write(val, DM365_CPLD_REGISTER3);
return 0;
}
/* For DM365, we need set tvp5146 reset line low for
* working with sensor. This API is used for this
* purpose state is 0 for reset low and 1 for high
*/
void tvp514x_hw_reset(int state)
{
u32 val1;
if (cpu_is_davinci_dm365()) {
val1 = cpld_read(DM365_CPLD_REGISTER19);
if (state)
val1 &= ~DM365_TVP5146_RST_MASK;
else
val1 |= 0x01010101;
cpld_write(val1, DM365_CPLD_REGISTER19);
}
}
void update_led(struct channel *sc, int blinker)
{
int leds;
if (sc->s.LOS)
leds = 0; /* led1 = off */
else if (sc->s.OOF)
leds = 2; /* led1 = yellow */
else if ((blinker & 1) && sc->rcv_count) {
leds = 0; /* led1 = off */
sc->rcv_count = 0;
} else
leds = 1; /* led1 = green */
cpld_write(sc, SBE_2T3E3_CPLD_REG_LEDR, leds);
sc->leds = leds;
}
void cpld_LOS_update(struct channel *sc)
{
u_int8_t los;
cpld_write(sc, SBE_2T3E3_CPLD_REG_PICSR,
SBE_2T3E3_CPLD_VAL_DMO_SIGNAL_DETECTED |
SBE_2T3E3_CPLD_VAL_RECEIVE_LOSS_OF_LOCK_DETECTED |
SBE_2T3E3_CPLD_VAL_RECEIVE_LOSS_OF_SIGNAL_DETECTED);
los = cpld_read(sc, SBE_2T3E3_CPLD_REG_PICSR) &
SBE_2T3E3_CPLD_VAL_RECEIVE_LOSS_OF_SIGNAL_DETECTED;
if (los != sc->s.LOS)
dev_info(&sc->pdev->dev, "SBE 2T3E3: LOS status: %s\n",
los ? "Loss of signal" : "Signal OK");
sc->s.LOS = los;
}
static int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
struct udevice *dev;
u32 addr, val;
int ret;
ret = uclass_get_device_by_driver(UCLASS_SYSRESET,
DM_GET_DRIVER(sysreset_renesas_ulcb),
&dev);
if (ret)
return ret;
if (argc == 2 && strcmp(argv[1], "info") == 0) {
printf("CPLD version:\t\t\t0x%08x\n",
cpld_read(dev, CPLD_ADDR_VERSION));
printf("H3 Mode setting (MD0..28):\t0x%08x\n",
cpld_read(dev, CPLD_ADDR_MODE));
printf("Multiplexer settings:\t\t0x%08x\n",
cpld_read(dev, CPLD_ADDR_MUX));
printf("DIPSW (SW6):\t\t\t0x%08x\n",
cpld_read(dev, CPLD_ADDR_DIPSW6));
return 0;
}
if (argc < 3)
return CMD_RET_USAGE;
addr = simple_strtoul(argv[2], NULL, 16);
if (!(addr == CPLD_ADDR_VERSION || addr == CPLD_ADDR_MODE ||
addr == CPLD_ADDR_MUX || addr == CPLD_ADDR_DIPSW6 ||
addr == CPLD_ADDR_RESET)) {
printf("Invalid CPLD register address\n");
return CMD_RET_USAGE;
}
if (argc == 3 && strcmp(argv[1], "read") == 0) {
printf("0x%x\n", cpld_read(dev, addr));
} else if (argc == 4 && strcmp(argv[1], "write") == 0) {
val = simple_strtoul(argv[3], NULL, 16);
cpld_write(dev, addr, val);
}
return 0;
}
void cpld_init(void)
{
u32 val;
/* PULL-UP on MISO line */
val = readl(PUPR3);
val |= PUPR3_SD3_DAT1;
writel(val, PUPR3);
gpio_request(SCLK, "SCLK");
gpio_request(SSTBZ, "SSTBZ");
gpio_request(MOSI, "MOSI");
gpio_request(MISO, "MISO");
gpio_direction_output(SCLK, 0);
gpio_direction_output(SSTBZ, 1);
gpio_direction_output(MOSI, 0);
gpio_direction_input(MISO);
/* dummy read */
cpld_read(CPLD_ADDR_VERSION);
printf("CPLD version: 0x%08x\n",
cpld_read(CPLD_ADDR_VERSION));
printf("H2 Mode setting (MD0..28): 0x%08x\n",
cpld_read(CPLD_ADDR_MODE));
printf("Multiplexer settings: 0x%08x\n",
cpld_read(CPLD_ADDR_MUX));
printf("HDMI setting: 0x%08x\n",
cpld_read(CPLD_ADDR_HDMI));
printf("DIPSW (SW3): 0x%08x\n",
cpld_read(CPLD_ADDR_DIPSW));
#ifdef CONFIG_SH_SDHI
/* switch MUX to SD0 */
val = cpld_read(CPLD_ADDR_MUX);
val &= ~MUX_MSK_SD0;
val |= MUX_VAL_SD0;
cpld_write(CPLD_ADDR_MUX, val);
#endif
}
void cpld_set_fractional_mode(struct channel *sc, u32 mode,
u32 start, u32 stop)
{
if (mode == SBE_2T3E3_FRACTIONAL_MODE_NONE) {
start = 0;
stop = 0;
}
if (sc->p.fractional_mode == mode && sc->p.bandwidth_start == start &&
sc->p.bandwidth_stop == stop)
return;
switch (mode) {
case SBE_2T3E3_FRACTIONAL_MODE_NONE:
cpld_write(sc, SBE_2T3E3_CPLD_REG_PCRC,
SBE_2T3E3_CPLD_VAL_FRACTIONAL_MODE_NONE);
break;
case SBE_2T3E3_FRACTIONAL_MODE_0:
cpld_write(sc, SBE_2T3E3_CPLD_REG_PCRC,
SBE_2T3E3_CPLD_VAL_FRACTIONAL_MODE_0);
break;
case SBE_2T3E3_FRACTIONAL_MODE_1:
cpld_write(sc, SBE_2T3E3_CPLD_REG_PCRC,
SBE_2T3E3_CPLD_VAL_FRACTIONAL_MODE_1);
break;
case SBE_2T3E3_FRACTIONAL_MODE_2:
cpld_write(sc, SBE_2T3E3_CPLD_REG_PCRC,
SBE_2T3E3_CPLD_VAL_FRACTIONAL_MODE_2);
break;
default:
netdev_err(sc->dev, "wrong mode in set_fractional_mode\n");
return;
}
cpld_write(sc, SBE_2T3E3_CPLD_REG_PBWF, start);
cpld_write(sc, SBE_2T3E3_CPLD_REG_PBWL, stop);
sc->p.fractional_mode = mode;
sc->p.bandwidth_start = start;
sc->p.bandwidth_stop = stop;
}
void rcar_cpld_reset_cpu(void)
{
cpld_init();
cpld_write(CPLD_ADDR_RESET, 1);
}
static int renesas_ulcb_sysreset_request(struct udevice *dev, enum sysreset_t type)
{
cpld_write(dev, CPLD_ADDR_RESET, 1);
return -EINPROGRESS;
}
void reset_cpu(ulong addr)
{
cpld_write(CPLD_ADDR_RESET, 1);
}
