static irqreturn_t davinci_interrupt(int irq, void *__hci) { unsigned long flags; irqreturn_t retval = IRQ_NONE; struct musb *musb = __hci; void __iomem *tibase = musb->ctrl_base; u32 tmp; spin_lock_irqsave(&musb->lock, flags); /* NOTE: DaVinci shadows the Mentor IRQs. Don't manage them through * the Mentor registers (except for setup), use the TI ones and EOI. * * Docs describe irq "vector" registers asociated with the CPPI and * USB EOI registers. These hold a bitmask corresponding to the * current IRQ, not an irq handler address. Would using those bits * resolve some of the races observed in this dispatch code?? */ /* CPPI interrupts share the same IRQ line, but have their own * mask, state, "vector", and EOI registers. */ if (is_cppi_enabled()) { u32 cppi_tx = musb_readl(tibase, DAVINCI_TXCPPI_MASKED_REG); u32 cppi_rx = musb_readl(tibase, DAVINCI_RXCPPI_MASKED_REG); if (cppi_tx || cppi_rx) { DBG(4, "CPPI IRQ t%x r%x\n", cppi_tx, cppi_rx); cppi_completion(musb, cppi_rx, cppi_tx); retval = IRQ_HANDLED; } } /* ack and handle non-CPPI interrupts */ tmp = musb_readl(tibase, DAVINCI_USB_INT_SRC_MASKED_REG); musb_writel(tibase, DAVINCI_USB_INT_SRC_CLR_REG, tmp); DBG(4, "IRQ %08x\n", tmp); musb->int_rx = (tmp & DAVINCI_USB_RXINT_MASK) >> DAVINCI_USB_RXINT_SHIFT; musb->int_tx = (tmp & DAVINCI_USB_TXINT_MASK) >> DAVINCI_USB_TXINT_SHIFT; musb->int_usb = (tmp & DAVINCI_USB_USBINT_MASK) >> DAVINCI_USB_USBINT_SHIFT; /* DRVVBUS irqs are the only proxy we have (a very poor one!) for * DaVinci's missing ID change IRQ. We need an ID change IRQ to * switch appropriately between halves of the OTG state machine. * Managing DEVCTL.SESSION per Mentor docs requires we know its * value, but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set. * Also, DRVVBUS pulses for SRP (but not at 5V) ... */ if (tmp & (DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT)) { int drvvbus = musb_readl(tibase, DAVINCI_USB_STAT_REG); void __iomem *mregs = musb->mregs; u8 devctl = musb_readb(mregs, MUSB_DEVCTL); int err = musb->int_usb & MUSB_INTR_VBUSERROR; err = is_host_enabled(musb) && (musb->int_usb & MUSB_INTR_VBUSERROR); if (err) { /* The Mentor core doesn't debounce VBUS as needed * to cope with device connect current spikes. This * means it's not uncommon for bus-powered devices * to get VBUS errors during enumeration. * * This is a workaround, but newer RTL from Mentor * seems to allow a better one: "re"starting sessions * without waiting (on EVM, a **long** time) for VBUS * to stop registering in devctl. */ musb->int_usb &= ~MUSB_INTR_VBUSERROR; musb->xceiv.state = OTG_STATE_A_WAIT_VFALL; mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); WARN("VBUS error workaround (delay coming)\n"); } else if (is_host_enabled(musb) && drvvbus) { musb->is_active = 1; MUSB_HST_MODE(musb); musb->xceiv.default_a = 1; musb->xceiv.state = OTG_STATE_A_WAIT_VRISE; portstate(musb->port1_status |= USB_PORT_STAT_POWER); del_timer(&otg_workaround); } else { musb->is_active = 0; MUSB_DEV_MODE(musb); musb->xceiv.default_a = 0; musb->xceiv.state = OTG_STATE_B_IDLE; portstate(musb->port1_status &= ~USB_PORT_STAT_POWER); } /* NOTE: this must complete poweron within 100 msec */ davinci_source_power(musb, drvvbus, 0); DBG(2, "VBUS %s (%s)%s, devctl %02x\n", drvvbus ? "on" : "off", otg_state_string(musb), err ? " ERROR" : "", devctl); retval = IRQ_HANDLED; } if (musb->int_tx || musb->int_rx || musb->int_usb) retval |= musb_interrupt(musb); /* irq stays asserted until EOI is written */ musb_writel(tibase, DAVINCI_USB_EOI_REG, 0); /* poll for ID change */ if (is_otg_enabled(musb) && musb->xceiv.state == OTG_STATE_B_IDLE) mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); spin_unlock_irqrestore(&musb->lock, flags); /* REVISIT we sometimes get unhandled IRQs * (e.g. ep0). not clear why... */ if (retval != IRQ_HANDLED) DBG(5, "unhandled? %08x\n", tmp); return IRQ_HANDLED; }
static irqreturn_t davinci_interrupt(int irq, void *__hci, struct pt_regs *r) { unsigned long flags; irqreturn_t retval = IRQ_NONE; struct musb *musb = __hci; void *__iomem tibase = musb->ctrl_base; u32 tmp; spin_lock_irqsave(&musb->Lock, flags); #ifdef CONFIG_USB_TI_CPPI_DMA /* CPPI interrupts share the same IRQ line, but have their own * mask, state, and EIO registers. */ { u32 cppi_tx = musb_readl(tibase, DAVINCI_TXCPPI_MASKED_REG); u32 cppi_rx = musb_readl(tibase, DAVINCI_RXCPPI_MASKED_REG); if (cppi_tx || cppi_rx) { DBG(4, "<== CPPI IRQ t%x r%x\n", cppi_tx, cppi_rx); cppi_completion(musb, cppi_rx, cppi_tx); retval = IRQ_HANDLED; } } #endif /* NOTE: DaVinci shadows the Mentor IRQs; don't manage them through * the mentor registers (except for setup), use the TI ones and EOI. */ /* ack and handle non-CPPI interrupts */ tmp = musb_readl(tibase, DAVINCI_USB_INT_SRC_MASKED_REG); musb_writel(tibase, DAVINCI_USB_INT_SRC_CLR_REG, tmp); musb->int_rx = (tmp & DAVINCI_USB_RXINT_MASK) >> DAVINCI_USB_RXINT_SHIFT; musb->int_tx = (tmp & DAVINCI_USB_TXINT_MASK) >> DAVINCI_USB_TXINT_SHIFT; musb->int_usb = (tmp & DAVINCI_USB_USBINT_MASK) >> DAVINCI_USB_USBINT_SHIFT; musb->int_regs = r; if (tmp & (1 << (8 + DAVINCI_USB_USBINT_SHIFT))) { int drvvbus = musb_readl(tibase, DAVINCI_USB_STAT_REG); /* NOTE: this must complete poweron within 100 msec */ DBG(1, "drvvbus Interrupt\n"); #ifndef CONFIG_ARCH_DAVINCI_DM355 #ifdef CONFIG_USB_MUSB_OTG davinci_vbus_power(musb, drvvbus); #elif defined(CONFIG_USB_MUSB_HDRC_HCD) /* In host mode manipulate vbus based on core request * but keep the session on. */ davinci_vbus_power(musb, drvvbus); #endif #endif drvvbus = 0; retval = IRQ_HANDLED; } if (musb->int_tx || musb->int_rx || musb->int_usb) retval |= musb_interrupt(musb); /* irq stays asserted until EOI is written */ musb_writel(tibase, DAVINCI_USB_EOI_REG, 0); spin_unlock_irqrestore(&musb->Lock, flags); /* REVISIT we sometimes get unhandled IRQs with CPPI * (minimally, host TX). not clear why... */ if (retval != IRQ_HANDLED) DBG(5, "unhandled? %08x\n", tmp); return IRQ_HANDLED; }