void riscv_cpu_unassigned_access(CPUState *cs, hwaddr addr, bool is_write,
bool is_exec, int unused, unsigned size)
{
target_ulong pc;
target_ulong cs_base;
int flags;
cpu_get_tb_cpu_state(cs->env_ptr, &pc, &cs_base, &flags);
printf("unassigned address not implemented for riscv\n");
printf("Instruction Address: %016lX\n", pc);
printf("unassigned Address: %016lX\n", addr);
exit(1);
}
static inline TranslationBlock *tb_find_fast(CPUState *env)
{
TranslationBlock *tb;
target_ulong cs_base, pc;
int flags;
/* we record a subset of the CPU state. It will
always be the same before a given translated block
is executed. */
cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
if (unlikely(!tb || tb->pc != pc || tb->cs_base != cs_base ||
tb->flags != flags)) {
tb = tb_find_slow(env, pc, cs_base, flags);
}
return tb;
}
int after_block_exec(CPUState* cpu, TranslationBlock *tb) {
CPUArchState* env = (CPUArchState*)cpu->env_ptr;
instr_type tb_type = call_cache[tb->pc];
if (tb_type == INSTR_CALL) {
stack_entry se = {tb->pc+tb->size,tb_type};
callstacks[get_stackid(env)].push_back(se);
// Also track the function that gets called
target_ulong pc, cs_base;
uint32_t flags;
// This retrieves the pc in an architecture-neutral way
cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
function_stacks[get_stackid(env)].push_back(pc);
PPP_RUN_CB(on_call, cpu, pc);
}
else if (tb_type == INSTR_RET) {
//printf("Just executed a RET in TB " TARGET_FMT_lx "\n", tb->pc);
//if (next) printf("Next TB: " TARGET_FMT_lx "\n", next->pc);
}
return 1;
}
target_ulong panda_current_pc(CPUState *env) {
target_ulong pc, cs_base;
int flags;
cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
return pc;
}
