void m65ce02_set_irq_line(int irqline, int state)
{
if (irqline == INPUT_LINE_NMI)
{
if (m65ce02.nmi_state == state) return;
m65ce02.nmi_state = state;
if( state != CLEAR_LINE )
{
LOG(("M65ce02#%d set_nmi_line(ASSERT)\n", cpu_getactivecpu()));
EAD = M65CE02_NMI_VEC;
m65ce02_ICount -= 7;
PUSH(PCH);
PUSH(PCL);
PUSH(P & ~F_B);
P = (P & ~F_D) | F_I; /* knock out D and set I flag */
PCL = RDMEM(EAD);
PCH = RDMEM(EAD+1);
LOG(("M65ce02#%d takes NMI ($%04x)\n", cpu_getactivecpu(), PCD));
change_pc(PCD);
}
}
else
{
m65ce02.irq_state = state;
if( state != CLEAR_LINE )
{
LOG(("M65ce02#%d set_irq_line(ASSERT)\n", cpu_getactivecpu()));
m65ce02.pending_irq = 1;
}
}
}
UINT32 debug_comment_get_opcode_crc32(offs_t address)
{
int i;
UINT32 crc;
UINT8 opbuf[64], argbuf[64];
char buff[256];
offs_t numbytes;
int maxbytes = activecpu_max_instruction_bytes();
UINT32 addrmask = (debug_get_cpu_info(cpu_getactivecpu()))->space[ADDRESS_SPACE_PROGRAM].logaddrmask;
int use_new_dasm = (activecpu_get_info_fct(CPUINFO_PTR_DISASSEMBLE_NEW) != NULL);
memset(opbuf, 0x00, sizeof(opbuf));
memset(argbuf, 0x00, sizeof(argbuf));
// fetch the bytes up to the maximum
for (i = 0; i < maxbytes; i++)
{
opbuf[i] = debug_read_opcode(address + i, 1, FALSE);
argbuf[i] = debug_read_opcode(address + i, 1, TRUE);
}
if (use_new_dasm)
{
numbytes = cpunum_dasm_new(cpu_getactivecpu(), buff, address & addrmask, opbuf, argbuf, maxbytes) & DASMFLAG_LENGTHMASK;
}
else
{
numbytes = cpunum_dasm(cpu_getactivecpu(), buff, address & addrmask) & DASMFLAG_LENGTHMASK;
}
crc = crc32(0, argbuf, numbytes);
return crc;
}
SEIBU_SOUND_SYSTEM_YM2203_HARDWARE
SEIBU_SOUND_SYSTEM_ADPCM_HARDWARE
/* Interrupt Generators */
static INTERRUPT_GEN( deadang_interrupt )
{
if (cpu_getiloops())
cpunum_set_input_line_and_vector(cpu_getactivecpu(), 0, HOLD_LINE, 0xc8/4); /* VBL */
else
cpunum_set_input_line_and_vector(cpu_getactivecpu(), 0, HOLD_LINE, 0xc4/4); /* VBL */
}
/****************************************************************************
* Set IRQ line state
****************************************************************************/
static void set_irq_line(int irqline, int state)
{
if (irqline == INPUT_LINE_NMI)
{
if (hd6309.nmi_state == state) return;
hd6309.nmi_state = state;
LOG(("HD6309#%d set_irq_line (NMI) %d (PC=%4.4X)\n", cpu_getactivecpu(), state, pPC));
if( state == CLEAR_LINE ) return;
/* if the stack was not yet initialized */
if( !(hd6309.int_state & HD6309_LDS) ) return;
hd6309.int_state &= ~HD6309_SYNC;
/* HJB 990225: state already saved by CWAI? */
if( hd6309.int_state & HD6309_CWAI )
{
hd6309.int_state &= ~HD6309_CWAI;
hd6309.extra_cycles += 7; /* subtract +7 cycles next time */
}
else
{
CC |= CC_E; /* save entire state */
PUSHWORD(pPC);
PUSHWORD(pU);
PUSHWORD(pY);
PUSHWORD(pX);
PUSHBYTE(DP);
if ( MD & MD_EM )
{
PUSHBYTE(F);
PUSHBYTE(E);
hd6309.extra_cycles += 2; /* subtract +2 cycles */
}
PUSHBYTE(B);
PUSHBYTE(A);
PUSHBYTE(CC);
hd6309.extra_cycles += 19; /* subtract +19 cycles next time */
}
CC |= CC_IF | CC_II; /* inhibit FIRQ and IRQ */
PCD = RM16(0xfffc);
CHANGE_PC;
}
else if (irqline < 2)
{
LOG(("HD6309#%d set_irq_line %d, %d (PC=%4.4X)\n", cpu_getactivecpu(), irqline, state, pPC));
hd6309.irq_state[irqline] = state;
if (state == CLEAR_LINE) return;
CHECK_IRQ_LINES();
}
}
void saturn_set_nmi_line(int state)
{
if (saturn.nmi_state == state) return;
saturn.nmi_state = state;
if( state != CLEAR_LINE )
{
LOG(( "M6502#%d set_nmi_line(ASSERT)\n", cpu_getactivecpu()));
saturn_ICount -= 7;
saturn_push(saturn.pc);
saturn.pc=IRQ_ADDRESS;
LOG(("M6502#%d takes NMI ($%04x)\n", cpu_getactivecpu(), PC));
change_pc(saturn.pc);
}
}
void pic16C5x_init(void)
{
int cpu = cpu_getactivecpu();
state_save_register_INT8("pic16C5x", cpu, "Old_Data", &old_data, 1);
state_save_register_UINT8("pic16C5x", cpu, "W", &R.W, 1);
state_save_register_UINT8("pic16C5x", cpu, "ALU", &R.ALU, 1);
state_save_register_UINT8("pic16C5x", cpu, "Option", &R.OPTION, 1);
state_save_register_UINT8("pic16C5x", cpu, "TRISA", &R.TRISA, 1);
state_save_register_UINT8("pic16C5x", cpu, "TRISB", &R.TRISB, 1);
state_save_register_UINT8("pic16C5x", cpu, "TRISC", &R.TRISC, 1);
state_save_register_UINT8("pic16C5x", cpu, "PORTA", &R.PORTA, 1);
state_save_register_UINT8("pic16C5x", cpu, "PORTB", &R.PORTB, 1);
state_save_register_UINT8("pic16C5x", cpu, "PORTC", &R.PORTC, 1);
state_save_register_UINT8("pic16C5x", cpu, "Old_T0", &old_T0, 1);
state_save_register_UINT8("pic16C5x", cpu, "STR", &R.STATUS, 1);
state_save_register_UINT8("pic16C5x", cpu, "RAM_mask", &picRAMmask, 1);
state_save_register_UINT16("pic16C5x", cpu, "WDT", &R.WDT, 1);
state_save_register_UINT16("pic16C5x", cpu, "Prescaler", &R.prescaler, 1);
state_save_register_UINT16("pic16C5x", cpu, "Stack0", &R.STACK[0], 1);
state_save_register_UINT16("pic16C5x", cpu, "Stack1", &R.STACK[1], 1);
state_save_register_UINT16("pic16C5x", cpu, "PC", &R.PC, 1);
state_save_register_UINT16("pic16C5x", cpu, "PrevPC", &R.PREVPC, 1);
state_save_register_UINT16("pic16C5x", cpu, "Config", &R.CONFIG, 1);
state_save_register_UINT32("pic16C5x", cpu, "Opcode", &R.opcode.d, 1);
state_save_register_INT32("pic16C5x", cpu, "Delay_Timer", &delay_timer, 1);
state_save_register_INT32("pic16C5x", cpu, "PIC_model", &picmodel, 1);
state_save_register_INT32("pic16C5x", cpu, "Reset_Vector", &pic16C5x_reset_vector, 1);
}
static WRITE_HANDLER( ddragon_spriteram_w )
{
if ( cpu_getactivecpu() == 1 && offset == 0 )
dd_sub_cpu_busy = 0x10;
ddragon_spriteram[offset] = data;
}
static WRITE8_HANDLER(write_a00x)
{
switch(offset)
{
case 0x02: //A002 bit 7&6 = bank ????
{
int newbank;
reg_a002=data;
newbank=(data>>6)&3;
if(newbank!=bank)
{
UINT8 *ROM = memory_region(REGION_CPU1);
bank=newbank;
ROM = &ROM[0x10000+0x8000 * newbank + UNBANKED_SIZE];
memory_set_bankptr(1,ROM);
}
}
break;
case 0x06: // bit 1 = coin lockout/counter ?
break;
case 0x08: //A008
cpunum_set_input_line(cpu_getactivecpu(),0,CLEAR_LINE);
break;
}
}
static void tms7000_init(int index, int clock, const void *config, int (*irqcallback)(int))
{
int cpu = cpu_getactivecpu();
tms7000.irq_callback = irqcallback;
memset(tms7000.pf, 0, 0x100);
memset(tms7000.rf, 0, 0x80);
/* Save register state */
state_save_register_item("tms7000", cpu, pPC);
state_save_register_item("tms7000", cpu, pSP);
state_save_register_item("tms7000", cpu, pSR);
/* Save Interrupt state */
state_save_register_item_array("tms7000", cpu, tms7000.irq_state);
/* Save register and perpherial file state */
state_save_register_item_array("tms7000", cpu, tms7000.rf);
state_save_register_item_array("tms7000", cpu, tms7000.pf);
/* Save timer state */
state_save_register_item("tms7000", cpu, tms7000.t1_prescaler);
state_save_register_item("tms7000", cpu, tms7000.t1_capture_latch);
state_save_register_item("tms7000", cpu, tms7000.t1_decrementer);
state_save_register_item("tms7000", cpu, tms7000.idle_state);
tms7000.irq_callback = irqcallback;
}
static void c128_bankswitch (int reset)
{
if (mmu_cpu != MMU_CPU8502)
{
if (!MMU_CPU8502)
{
DBG_LOG (1, "switching to z80",
("active %d\n",cpu_getactivecpu()) );
memory_set_context(0);
c128_bankswitch_z80();
memory_set_context(1);
cpunum_set_input_line(0, INPUT_LINE_HALT, CLEAR_LINE);
cpunum_set_input_line(1, INPUT_LINE_HALT, ASSERT_LINE);
}
else
{
DBG_LOG (1, "switching to m6502",
("active %d\n",cpu_getactivecpu()) );
memory_set_context(1);
c128_bankswitch_128(reset);
memory_set_context(0);
cpunum_set_input_line(0, INPUT_LINE_HALT, ASSERT_LINE);
cpunum_set_input_line(1, INPUT_LINE_HALT, CLEAR_LINE);
/* NPW 19-Nov-2005 - In the C128, CPU #0 starts out and hands over
* control to CPU #1. CPU #1 seems to execute garbage from 0x0000
* up to 0x1100, at which point it finally hits some code
* (presumably set up by CPU #1.) This always worked, but when I
* changed the m8502 CPU core to use an internal memory map, it
* started BRK-ing forever when trying to execute 0x0000.
*
* I am not sure whether the C128 actually executes this invalid
* memory or if this is a bug in the C128 driver. In any case, the
* driver used to work with this behavior, so I am doing this hack
* where I set CPU #1's PC to 0x1100 on reset.
*/
if (cpunum_get_reg(1, REG_PC) == 0x0000)
cpunum_set_reg(1, REG_PC, 0x1100);
}
mmu_cpu = MMU_CPU8502;
return;
}
if (!MMU_CPU8502)
c128_bankswitch_z80();
else
c128_bankswitch_128(reset);
}
SEIBU_SOUND_SYSTEM_YM3812_HARDWARE
/* Interrupt Generator */
static INTERRUPT_GEN( dynduke_interrupt )
{
cpunum_set_input_line_and_vector(cpu_getactivecpu(), 0, HOLD_LINE, 0xc8/4); // VBL
}
void computer_writemem_byte(int cpu, int addr, int value)
{
int oldcpu = cpu_getactivecpu();
memory_set_context(cpu);
MEMORY_WRITE(cpu, addr, value);
if (oldcpu != cpu)
memory_set_context(oldcpu);
}
INLINE void irqn_line_assert(int irqline)
{
int cpunum = cpu_getactivecpu();
if (interrupt_enable[cpunum])
{
int vector = (irqline >= 0 && irqline < MAX_IRQ_LINES) ? interrupt_vector[cpunum][irqline] : 0xff;
cpu_set_irq_line_and_vector(cpunum, irqline, ASSERT_LINE, vector);
}
}
void saturn_set_irq_line(int irqline, int state)
{
saturn.irq_state = state;
if( state != CLEAR_LINE )
{
LOG(( "M6502#%d set_irq_line(ASSERT)\n", cpu_getactivecpu()));
saturn.pending_irq = 1;
}
}
int computer_readmem_byte(int cpu, int addr)
{
int oldcpu = cpu_getactivecpu(), result;
memory_set_context(cpu);
result = MEMORY_READ(cpu, addr);
if (oldcpu != cpu)
memory_set_context(oldcpu);
return result;
}
/****************************************************************************
* Set IRQ line state
****************************************************************************/
static void set_irq_line(int irqline, int state)
{
if (irqline == INPUT_LINE_NMI)
{
if (konami.nmi_state == state) return;
konami.nmi_state = state;
LOG(("KONAMI#%d set_nmi_line %d\n", cpu_getactivecpu(), state));
if( state == CLEAR_LINE ) return;
/* if the stack was not yet initialized */
if( !(konami.int_state & KONAMI_LDS) ) return;
konami.int_state &= ~KONAMI_SYNC;
/* state already saved by CWAI? */
if( konami.int_state & KONAMI_CWAI )
{
konami.int_state &= ~KONAMI_CWAI;
konami.extra_cycles += 7; /* subtract +7 cycles next time */
}
else
{
CC |= CC_E; /* save entire state */
PUSHWORD(pPC);
PUSHWORD(pU);
PUSHWORD(pY);
PUSHWORD(pX);
PUSHBYTE(DP);
PUSHBYTE(B);
PUSHBYTE(A);
PUSHBYTE(CC);
konami.extra_cycles += 19; /* subtract +19 cycles next time */
}
CC |= CC_IF | CC_II; /* inhibit FIRQ and IRQ */
PCD = RM16(0xfffc);
change_pc(PC); /* TS 971002 */
}
else if (irqline < 2)
{
LOG(("KONAMI#%d set_irq_line %d, %d\n", cpu_getactivecpu(), irqline, state));
konami.irq_state[irqline] = state;
if (state == CLEAR_LINE) return;
CHECK_IRQ_LINES;
}
}
static INTERRUPT_GEN( grchamp_interrupt )
{
int cpu = cpu_getactivecpu();
if ( grchamp_cpu_irq_enable[cpu] )
{
grchamp_cpu_irq_enable[cpu] = 0;
cpu_set_irq_line(cpu, 0, HOLD_LINE);
}
}
static int m6502_execute(int cycles)
{
m6502_ICount = cycles;
change_pc(PCD);
do
{
UINT8 op;
PPC = PCD;
CALL_MAME_DEBUG;
#if 1
/* if an irq is pending, take it now */
if( m6502.pending_irq )
m6502_take_irq();
op = RDOP();
(*m6502.insn[op])();
#else
/* thought as irq request while executing sei */
/* sei sets I flag on the stack*/
op = RDOP();
/* if an irq is pending, take it now */
if( m6502.pending_irq && (op == 0x78) )
m6502_take_irq();
(*m6502.insn[op])();
#endif
/* check if the I flag was just reset (interrupts enabled) */
if( m6502.after_cli )
{
LOG(("M6502#%d after_cli was >0", cpu_getactivecpu()));
m6502.after_cli = 0;
if (m6502.irq_state != CLEAR_LINE)
{
LOG((": irq line is asserted: set pending IRQ\n"));
m6502.pending_irq = 1;
}
else
{
LOG((": irq line is clear\n"));
}
}
else
if( m6502.pending_irq )
m6502_take_irq();
} while (m6502_ICount > 0);
return cycles - m6502_ICount;
}
static void m6509_set_irq_line(int irqline, int state)
{
if (irqline == INPUT_LINE_NMI)
{
if (m6509.nmi_state == state) return;
m6509.nmi_state = state;
if( state != CLEAR_LINE )
{
LOG(( "M6509#%d set_nmi_line(ASSERT)\n", cpu_getactivecpu()));
EAD = M6509_NMI_VEC;
EAWH = PBWH;
m6509_ICount -= 7;
PUSH(PCH);
PUSH(PCL);
PUSH(P & ~F_B);
P |= F_I; /* knock out D and set I flag */
PCL = RDMEM(EAD);
PCH = RDMEM(EAD+1);
LOG(("M6509#%d takes NMI ($%04x)\n", cpu_getactivecpu(), PCD));
change_pc(PCD);
}
}
else
{
if( irqline == M6509_SET_OVERFLOW )
{
if( m6509.so_state && !state )
{
LOG(( "M6509#%d set overflow\n", cpu_getactivecpu()));
P|=F_V;
}
m6509.so_state=state;
return;
}
m6509.irq_state = state;
if( state != CLEAR_LINE )
{
LOG(( "M6509#%d set_irq_line(ASSERT)\n", cpu_getactivecpu()));
m6509.pending_irq = 1;
}
}
}
void h8_itu_init(void)
{
h8.timer[0] = timer_alloc(h8itu_timer_0_cb);
h8.timer[1] = timer_alloc(h8itu_timer_1_cb);
h8.timer[2] = timer_alloc(h8itu_timer_2_cb);
h8.timer[3] = timer_alloc(h8itu_timer_3_cb);
h8.timer[4] = timer_alloc(h8itu_timer_4_cb);
h8_itu_reset();
h8.cpu_number = cpu_getactivecpu();
}
void s2650_state_load(void *file)
{
int cpu = cpu_getactivecpu();
state_load_UINT16(file,"s2650",cpu,"PAGE",&S.page,1);
state_load_UINT16(file,"s2650",cpu,"IAR",&S.iar,1);
state_load_UINT8(file,"s2650",cpu,"PSL",&S.psl,1);
state_load_UINT8(file,"s2650",cpu,"PSU",&S.psu,1);
state_load_UINT8(file,"s2650",cpu,"REG",S.reg,7);
state_load_UINT8(file,"s2650",cpu,"HALT",&S.halt,1);
state_load_UINT16(file,"s2650",cpu,"RAS",S.ras,8);
state_load_UINT8(file,"s2650",cpu,"IRQ_STATE",&S.irq_state,1);
}
void digdug_sharedram_w(int offset,int data)
{
/* a video ram write */
if (offset < 0x400)
dirtybuffer[offset] = 1;
/* location 9b3d is set to zero just before CPU 2 spins */
if (offset == 0x1b3d && data == 0 && cpu_get_pc () == 0x1df1 && cpu_getactivecpu () == 1)
cpu_spinuntil_int ();
digdug_sharedram[offset] = data;
}
void hd63705_init(void)
{
int cpu = cpu_getactivecpu();
state_register("hd63705");
state_save_register_INT32("hd63705",cpu,"IRQ1_STATE", &m6805.irq_state[0], 1);
state_save_register_INT32("hd63705",cpu,"IRQ2_STATE", &m6805.irq_state[1], 1);
state_save_register_INT32("hd63705",cpu,"TIMER1_STATE", &m6805.irq_state[2], 1);
state_save_register_INT32("hd63705",cpu,"TIMER2_STATE", &m6805.irq_state[3], 1);
state_save_register_INT32("hd63705",cpu,"TIMER3_STATE", &m6805.irq_state[4], 1);
state_save_register_INT32("hd63705",cpu,"PCI_STATE", &m6805.irq_state[5], 1);
state_save_register_INT32("hd63705",cpu,"SCI_STATE", &m6805.irq_state[6], 1);
state_save_register_INT32("hd63705",cpu,"ADCONV_STATE", &m6805.irq_state[7], 1);
}
void lh5801_state_load(void *file)
{
#if 0
int cpu = cpu_getactivecpu();
state_load_UINT16(file,"sc61860",cpu,"PC",&sc61860.pc,2);
state_load_UINT16(file,"sc61860",cpu,"DP",&sc61860.dp,2);
state_load_UINT8(file,"sc61860",cpu,"P",&sc61860.p,1);
state_load_UINT8(file,"sc61860",cpu,"Q",&sc61860.q,1);
state_load_UINT8(file,"sc61860",cpu,"R",&sc61860.r,1);
// state_load_UINT8(file,"sc61860",cpu,"C",&sc61860.carry,1);
// state_load_UINT8(file,"sc61860",cpu,"Z",&sc61860.zero,1);
#endif
}
Uint8 mcputest::cpu_mem_read(Uint16 addr)
{
// cpu #0
if (cpu_getactivecpu() == 0)
{
return m_cpumem[addr];
}
// cpu #1
else
{
return m_cpumem2[addr];
}
}
void mcputest::cpu_mem_write(Uint16 addr, Uint8 value)
{
// cpu #0
if (cpu_getactivecpu() == 0)
{
m_cpumem[addr] = value;
}
// cpu #1
else
{
m_cpumem2[addr] = value;
}
}
void arm_init(void)
{
int cpu = cpu_getactivecpu(),i;
char buf[8];
for (i=0; i<kNumRegisters; i++) {
sprintf(buf,"R%d",i);
state_save_register_UINT32("arm", cpu, buf, &arm.sArmRegister[i], 4);
}
state_save_register_UINT8("arm", cpu, "IRQ", &arm.pendingIrq, 1);
state_save_register_UINT8("arm", cpu, "FIQ", &arm.pendingFiq, 1);
return;
}
ADDRESS_MAP_END
/***************************************************************************/
static INTERRUPT_GEN( grchamp_interrupt )
{
int cpu = cpu_getactivecpu();
if ( grchamp_cpu_irq_enable[cpu] )
{
grchamp_cpu_irq_enable[cpu] = 0;
cpunum_set_input_line(cpu, 0, HOLD_LINE);
}
}
static void tms7000_service_timer1( void )
{
if( --tms7000.t1_prescaler < 0 ) /* Decrement prescaler and check for underflow */
{
tms7000.t1_prescaler = tms7000.pf[3] & 0x1f; /* Reload prescaler (5 bit) */
if( --tms7000.t1_decrementer < 0 ) /* Decrement timer1 register and check for underflow */
{
tms7000.t1_decrementer = tms7000.pf[2]; /* Reload decrementer (8 bit) */
cpunum_set_input_line( cpu_getactivecpu(), TMS7000_IRQ2_LINE, HOLD_LINE);
LOG( ("tms7000: trigger int2 (cycles: %d)\t%d\tdelta %d\n", activecpu_gettotalcycles(), activecpu_gettotalcycles() - tick, tms7000_cycles_per_INT2-(activecpu_gettotalcycles() - tick) );
tick = activecpu_gettotalcycles() );
/* Also, cascade out to timer 2 - timer 2 unimplemented */
}
/****************************************************************************
* Save CPU state
****************************************************************************/
static void state_save(void *file, const char *module)
{
int cpu = cpu_getactivecpu();
state_save_register_item(file, cpu, module, PC);
state_save_register_item(file, cpu, module, U);
state_save_register_item(file, cpu, module, S);
state_save_register_item(file, cpu, module, X);
state_save_register_item(file, cpu, module, Y);
state_save_register_item(file, cpu, module, DP);
state_save_register_item(file, cpu, module, CC);
state_save_register_item(file, cpu, module, konami.int_state);
state_save_register_item(file, cpu, module, konami.nmi_state);
state_save_register_item(file, cpu, module, konami.irq_state[0]);
state_save_register_item(file, cpu, module, konami.irq_state[1]);
}
