void __init mxc_timer_init(struct clk *timer_clk, void __iomem *base, int irq) { uint32_t tctl_val; clk_enable(timer_clk); timer_base = base; __raw_writel(0, timer_base + MXC_TCTL); __raw_writel(0, timer_base + MXC_TPRER); if (cpu_is_mx3() || cpu_is_mx25()) tctl_val = MX3_TCTL_CLK_IPG | MX3_TCTL_FRR | MX3_TCTL_WAITEN | MXC_TCTL_TEN; else tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; __raw_writel(tctl_val, timer_base + MXC_TCTL); mxc_clocksource_init(timer_clk); mxc_clockevent_init(timer_clk); setup_irq(irq, &mxc_timer_irq); }
static void mxc_set_mode(enum clock_event_mode mode, struct clock_event_device *evt) { unsigned long flags; /* * The timer interrupt generation is disabled at least * for enough time to call mxc_set_next_event() */ local_irq_save(flags); /* Disable interrupt in GPT module */ gpt_irq_disable(); if (mode != clockevent_mode) { /* Set event time into far-far future */ if (cpu_is_mx3()) __raw_writel(__raw_readl(timer_base + MX3_TCN) - 3, timer_base + MX3_TCMP); else __raw_writel(__raw_readl(timer_base + MX1_2_TCN) - 3, timer_base + MX1_2_TCMP); /* Clear pending interrupt */ gpt_irq_acknowledge(); } #ifdef DEBUG printk(KERN_INFO "mxc_set_mode: changing mode from %s to %s\n", clock_event_mode_label[clockevent_mode], clock_event_mode_label[mode]); #endif /* DEBUG */ /* Remember timer mode */ clockevent_mode = mode; local_irq_restore(flags); switch (mode) { case CLOCK_EVT_MODE_PERIODIC: printk(KERN_ERR"mxc_set_mode: Periodic mode is not " "supported for i.MX\n"); break; case CLOCK_EVT_MODE_ONESHOT: /* * Do not put overhead of interrupt enable/disable into * mxc_set_next_event(), the core has about 4 minutes * to call mxc_set_next_event() or shutdown clock after * mode switching */ local_irq_save(flags); gpt_irq_enable(); local_irq_restore(flags); break; case CLOCK_EVT_MODE_SHUTDOWN: case CLOCK_EVT_MODE_UNUSED: case CLOCK_EVT_MODE_RESUME: /* Left event sources disabled, no more interrupts appear */ break; } }
void __init mxc_timer_init(struct clk *timer_clk) { uint32_t tctl_val; int irq; clk_enable(timer_clk); if (cpu_is_mx1()) { #ifdef CONFIG_ARCH_MX1 timer_base = IO_ADDRESS(TIM1_BASE_ADDR); irq = TIM1_INT; #endif } else if (cpu_is_mx2()) { #ifdef CONFIG_ARCH_MX2 timer_base = IO_ADDRESS(GPT1_BASE_ADDR); irq = MXC_INT_GPT1; #endif } else if (cpu_is_mx3()) { #ifdef CONFIG_ARCH_MX3 timer_base = IO_ADDRESS(GPT1_BASE_ADDR); irq = MXC_INT_GPT; #endif } else BUG(); /* * Initialise to a known state (all timers off, and timing reset) */ __raw_writel(0, timer_base + MXC_TCTL); __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */ if (cpu_is_mx3()) tctl_val = MX3_TCTL_CLK_IPG | MX3_TCTL_FRR | MX3_TCTL_WAITEN | MXC_TCTL_TEN; else tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; __raw_writel(tctl_val, timer_base + MXC_TCTL); /* init and register the timer to the framework */ mxc_clocksource_init(timer_clk); mxc_clockevent_init(timer_clk); /* Make irqs happen */ setup_irq(irq, &mxc_timer_irq); }
static void gpt_irq_acknowledge(void) { if (cpu_is_mx1()) __raw_writel(0, timer_base + MX1_2_TSTAT); if (cpu_is_mx2()) __raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, timer_base + MX1_2_TSTAT); if (cpu_is_mx3() || cpu_is_mx25()) __raw_writel(MX3_TSTAT_OF1, timer_base + MX3_TSTAT); }
static inline void gpt_irq_enable(void) { if (cpu_is_mx3() || cpu_is_mx25()) __raw_writel(1<<0, timer_base + MX3_IR); else { __raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN, timer_base + MXC_TCTL); } }
static inline void gpt_irq_disable(void) { unsigned int tmp; if (cpu_is_mx3() || cpu_is_mx25()) __raw_writel(0, timer_base + MX3_IR); else { tmp = __raw_readl(timer_base + MXC_TCTL); __raw_writel(tmp & ~MX1_2_TCTL_IRQEN, timer_base + MXC_TCTL); } }
static void mxc_set_mode(enum clock_event_mode mode, struct clock_event_device *evt) { unsigned long flags; local_irq_save(flags); gpt_irq_disable(); if (mode != clockevent_mode) { if (cpu_is_mx3() || cpu_is_mx25()) __raw_writel(__raw_readl(timer_base + MX3_TCN) - 3, timer_base + MX3_TCMP); else __raw_writel(__raw_readl(timer_base + MX1_2_TCN) - 3, timer_base + MX1_2_TCMP); gpt_irq_acknowledge(); } #ifdef DEBUG printk(KERN_INFO "mxc_set_mode: changing mode from %s to %s\n", clock_event_mode_label[clockevent_mode], clock_event_mode_label[mode]); #endif clockevent_mode = mode; local_irq_restore(flags); switch (mode) { case CLOCK_EVT_MODE_PERIODIC: printk(KERN_ERR"mxc_set_mode: Periodic mode is not " "supported for i.MX\n"); break; case CLOCK_EVT_MODE_ONESHOT: local_irq_save(flags); gpt_irq_enable(); local_irq_restore(flags); break; case CLOCK_EVT_MODE_SHUTDOWN: case CLOCK_EVT_MODE_UNUSED: case CLOCK_EVT_MODE_RESUME: break; } }
static int __init mxc_clocksource_init(struct clk *timer_clk) { unsigned int c = clk_get_rate(timer_clk); if (cpu_is_mx3() || cpu_is_mx25()) clocksource_mxc.read = mx3_get_cycles; clocksource_mxc.mult = clocksource_hz2mult(c, clocksource_mxc.shift); clocksource_register(&clocksource_mxc); return 0; }
static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id) { struct clock_event_device *evt = &clockevent_mxc; uint32_t tstat; if (cpu_is_mx3() || cpu_is_mx25()) tstat = __raw_readl(timer_base + MX3_TSTAT); else tstat = __raw_readl(timer_base + MX1_2_TSTAT); gpt_irq_acknowledge(); evt->event_handler(evt); return IRQ_HANDLED; }
static int __init mxc_clockevent_init(struct clk *timer_clk) { unsigned int c = clk_get_rate(timer_clk); if (cpu_is_mx3() || cpu_is_mx25()) clockevent_mxc.set_next_event = mx3_set_next_event; clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC, clockevent_mxc.shift); clockevent_mxc.max_delta_ns = clockevent_delta2ns(0xfffffffe, &clockevent_mxc); clockevent_mxc.min_delta_ns = clockevent_delta2ns(0xff, &clockevent_mxc); clockevent_mxc.cpumask = cpumask_of(0); clockevents_register_device(&clockevent_mxc); return 0; }