/*
* This function is called only once by the gmond. Use to
* initialize data structures, etc or just return SYNAPSE_SUCCESS;
*/
g_val_t
metric_init(void)
{
g_val_t val;
/*
* Try to use the vm.swap_info sysctl to gather swap data. If it
* isn't implemented, fall back to trying to old kvm based interface.
*/
mibswap_size = MIB_SWAPINFO_SIZE;
if (sysctlnametomib("vm.swap_info", mibswap, &mibswap_size) == -1) {
kd = kvm_open(NULL, NULL, NULL, O_RDONLY, "metric_init()");
} else {
/*
* RELEASE versions of DragonFlyBSD with the swap mib have a version
* of libkvm that doesn't need root for simple proc access so we
* just open /dev/null to give us a working handle here.
*/
kd = kvm_open(_PATH_DEVNULL, NULL, NULL, O_RDONLY, "metric_init()");
use_vm_swap_info = 1;
}
pagesize = getpagesize();
/* Initalize some counters */
get_netbw(NULL, NULL, NULL, NULL);
cpu_state(-1);
val.int32 = SYNAPSE_SUCCESS;
return val;
}
g_val_t
cpu_intr_func ( void )
{
g_val_t val;
val.f = (float) cpu_state(3);
return val;
}
g_val_t
cpu_idle_func ( void )
{
g_val_t val;
val.f = (float) cpu_state(4);
return val;
}
g_val_t
cpu_system_func ( void )
{
g_val_t val;
val.f = (float) cpu_state(2);
return val;
}
g_val_t
cpu_nice_func ( void )
{
g_val_t val;
val.f = (float) cpu_state(1);
return val;
}
g_val_t
cpu_user_func ( void )
{
g_val_t val;
val.f = (float) cpu_state(0);
return val;
}
static struct dt_node *add_cpu_node(struct dt_node *cpus,
const struct HDIF_common_hdr *paca,
const struct sppaca_cpu_id *id,
bool okay)
{
const struct sppaca_cpu_timebase *timebase;
const struct sppaca_cpu_cache *cache;
const struct sppaca_cpu_attr *attr;
struct dt_node *cpu;
u32 no, size, ve_flags, l2_phandle, chip_id;
/* We use the process_interrupt_line as the res id */
no = be32_to_cpu(id->process_interrupt_line);
ve_flags = be32_to_cpu(id->verify_exists_flags);
prlog(PR_INFO, "CPU[%i]: PIR=%i RES=%i %s %s(%u threads)\n",
paca_index(paca), be32_to_cpu(id->pir), no,
ve_flags & CPU_ID_PACA_RESERVED
? "**RESERVED**" : cpu_state(ve_flags),
ve_flags & CPU_ID_SECONDARY_THREAD
? "[secondary] " :
(be32_to_cpu(id->pir) == boot_cpu->pir ? "[boot] " : ""),
((ve_flags & CPU_ID_NUM_SECONDARY_THREAD_MASK)
>> CPU_ID_NUM_SECONDARY_THREAD_SHIFT) + 1);
timebase = HDIF_get_idata(paca, SPPACA_IDATA_TIMEBASE, &size);
if (!timebase || size < sizeof(*timebase)) {
prerror("CPU[%i]: bad timebase size %u @ %p\n",
paca_index(paca), size, timebase);
return NULL;
}
cache = HDIF_get_idata(paca, SPPACA_IDATA_CACHE_SIZE, &size);
if (!cache || size < sizeof(*cache)) {
prerror("CPU[%i]: bad cache size %u @ %p\n",
paca_index(paca), size, cache);
return NULL;
}
cpu = add_core_common(cpus, cache, timebase, no, okay);
/* Core attributes */
attr = HDIF_get_idata(paca, SPPACA_IDATA_CPU_ATTR, &size);
if (attr)
add_core_attr(cpu, be32_to_cpu(attr->attr));
/* Add cache info */
l2_phandle = add_core_cache_info(cpus, cache, no, okay);
dt_add_property_cells(cpu, "l2-cache", l2_phandle);
/* We append the secondary cpus in __cpu_parse */
dt_add_property_cells(cpu, "ibm,ppc-interrupt-server#s", no);
dt_add_property_cells(cpu, DT_PRIVATE "hw_proc_id",
be32_to_cpu(id->hardware_proc_id));
dt_add_property_cells(cpu, "ibm,pir", be32_to_cpu(id->pir));
chip_id = pcid_to_chip_id(be32_to_cpu(id->processor_chip_id));
dt_add_property_cells(cpu, "ibm,chip-id", chip_id);
return cpu;
}