bool BufferManager::initialize()
{
    CTRACE();

    // create buffer pool
    mBufferPool = new BufferCache(DEFAULT_BUFFER_POOL_SIZE);
    if (!mBufferPool) {
        ELOGTRACE("failed to create gralloc buffer cache");
        return false;
    }

    // init gralloc module
    if (gralloc_open_img(&mGralloc)) {
        DEINIT_AND_RETURN_FALSE("failed to get gralloc module");
    }

    // create a dummy data buffer
    mDataBuffer = createDataBuffer(0);
    if (!mDataBuffer) {
        DEINIT_AND_RETURN_FALSE("failed to create data buffer");
    }

    mInitialized = true;
    return true;
}
DataBuffer* BufferManager::get(uint32_t handle)
{
    return createDataBuffer(handle);
}
Ejemplo n.º 3
0
    void PhyEngine::buildEngineGraph(RadioGraph& graph)
    {
        //Create the components
        VertexIterator i, iend;
        for(b::tie(i,iend) = vertices(graph); i != iend; ++i)
        {
            //Load the component and add to vector
            ComponentDescription current = graph[*i];
            b::shared_ptr<PhyComponent> comp = compManager_->loadComponent(current);
            comp->setEngine(this);    //Provide an interface to the component
            components_.push_back(comp);
        }

        //Do a topological sort of the graph
        deque<unsigned> topoOrder;
        topological_sort(graph, front_inserter(topoOrder), b::vertex_index_map(b::identity_property_map()));

        //Set up some containers
        vector< ReadBufferBase* > currentInBufs;
        vector< WriteBufferBase* > currentOutBufs;
        map<string, int> inputTypes, outputTypes;

        //The external input buffers feed the source component of the graph
        for( vector< b::shared_ptr< DataBufferBase > >::iterator i = engInputBuffers_.begin(); i != engInputBuffers_.end(); ++i)
        {
            DataBufferBase* buf = (*i).get();
            LinkDescription desc = buf->getLinkDescription();
            inputTypes[desc.sinkPort] = buf->getTypeIdentifier();
            currentInBufs.push_back(dynamic_cast<ReadBufferBase*>(buf));
        }

        //Set buffers on the components
        for(deque<unsigned>::iterator i = topoOrder.begin(); i != topoOrder.end(); ++i)
        {
            //Get the internal input buffer details
            InEdgeIterator edgeIt, edgeItEnd;
            for(b::tie(edgeIt, edgeItEnd) = in_edges(*i, graph); edgeIt != edgeItEnd; ++edgeIt)
            {
                inputTypes[graph[*edgeIt].sinkPort] =  graph[*edgeIt].theBuffer->getTypeIdentifier();
                currentInBufs.push_back(dynamic_cast<ReadBufferBase*>(graph[*edgeIt].theBuffer.get()));
            }

            //TODO: Check that the input port names from the xml match existing input ports
            //TODO: Check that inputs exist for each of the registered input port names

            //Get output buffer types from component
            components_[*i]->calculateOutputTypes(inputTypes, outputTypes);

            // temporary shell for testing template components
            std::vector<int> inTypes, outTypes;
            for (std::map<std::string, int>::iterator j = inputTypes.begin(); j != inputTypes.end(); ++j)
            {
                inTypes.push_back(j->second);
            }
            for (std::map<std::string, int>::iterator j = outputTypes.begin(); j != outputTypes.end(); ++j)
            {
                outTypes.push_back(j->second);
            }

            PhyComponent* x = components_[*i]->setupIO(inTypes, outTypes);
            if (x != components_[*i].get())
            {
                components_[*i].reset(x);
            }

            //Create internal output buffers and add to graph edges
            OutEdgeIterator outEdgeIt, outEdgeItEnd;
            for(b::tie(outEdgeIt, outEdgeItEnd) = out_edges(*i, graph); outEdgeIt != outEdgeItEnd; ++outEdgeIt)
            {
                //Check that the port name exists
                string srcPort = graph[*outEdgeIt].sourcePort;
                if(outputTypes.find(srcPort) == outputTypes.end())
                {
                    throw ResourceNotFoundException("Output port " + srcPort + \
                        " could not be found on PhyComponent " + components_[*i]->getName());
                }

                //Create a PhyDataBuffer of the correct type
                int currentType = outputTypes[srcPort];
                b::shared_ptr< DataBufferBase > buf = createPhyDataBuffer(currentType);
                graph[*outEdgeIt].theBuffer = buf;
                graph[*outEdgeIt].theBuffer->setLinkDescription(graph[*outEdgeIt]);
                internalBuffers_.push_back( buf );

                currentOutBufs.push_back( dynamic_cast<WriteBufferBase*>( buf.get() ) );

                //Remove from the outputTypes map
                outputTypes.erase( outputTypes.find( srcPort ) );
            }

            //Anything left in the outputTypes map must be an external output buffer
            for( map<string, int>::iterator j = outputTypes.begin(); j != outputTypes.end(); ++j)
            {
                //Create a DataBuffer and add to exOutputBuffers
                b::shared_ptr< DataBufferBase > buf = createDataBuffer( j->second );
                LinkDescription l;
                l.sourceEngine = engineName_;
                l.sourceComponent = components_[*i]->getName();
                l.sourcePort = j->first;
                buf->setLinkDescription(l);
                engOutputBuffers_.push_back(buf);
                currentOutBufs.push_back( dynamic_cast<WriteBufferBase*>( buf.get() ) );
            }

            //Set the buffers in the component
            components_[*i]->setBuffers(currentInBufs, currentOutBufs);

            //Initialize the component
            components_[*i]->initialize();

            currentInBufs.clear();
            currentOutBufs.clear();
        }

    }