static void check_bus_watcher(void) { uint32_t status, l2_err, memio_err; #ifdef DUMP_L2_ECC_TAG_ON_ERROR uint64_t l2_tag; #endif /* Destructive read, clears register and interrupt */ status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS)); /* Bit 31 is always on, but there's no #define for that */ if (status & ~(1UL << 31)) { l2_err = csr_in32(IOADDR(A_BUS_L2_ERRORS)); #ifdef DUMP_L2_ECC_TAG_ON_ERROR l2_tag = in64(IO_SPACE_BASE | A_L2_ECC_TAG); #endif memio_err = csr_in32(IOADDR(A_BUS_MEM_IO_ERRORS)); prom_printf("Bus watcher error counters: %08x %08x\n", l2_err, memio_err); prom_printf("\nLast recorded signature:\n"); prom_printf("Request %02x from %d, answered by %d with Dcode %d\n", (unsigned int)(G_SCD_BERR_TID(status) & 0x3f), (int)(G_SCD_BERR_TID(status) >> 6), (int)G_SCD_BERR_RID(status), (int)G_SCD_BERR_DCODE(status)); #ifdef DUMP_L2_ECC_TAG_ON_ERROR prom_printf("Last L2 tag w/ bad ECC: %016llx\n", l2_tag); #endif } else {
static inline u32 READ_SERCSR(u32 *addr, int line) { u32 val = csr_in32(addr); #if SIBYTE_1956_WAR csr_out32(last_mode1[line], uart_states[line].mode_1); #endif return val; }
static void check_bus_watcher(void) { uint32_t status, l2_err, memio_err; /* Destructive read, clears register and interrupt */ status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS)); /* Bit 31 is always on, but there's no #define for that */ if (status & ~(1UL << 31)) { l2_err = csr_in32(IOADDR(A_BUS_L2_ERRORS)); memio_err = csr_in32(IOADDR(A_BUS_MEM_IO_ERRORS)); prom_printf("Bus watcher error counters: %08x %08x\n", l2_err, memio_err); prom_printf("\nLast recorded signature:\n"); prom_printf("Request %02x from %d, answered by %d with Dcode %d\n", (unsigned int)(G_SCD_BERR_TID(status) & 0x3f), (int)(G_SCD_BERR_TID(status) >> 6), (int)G_SCD_BERR_RID(status), (int)G_SCD_BERR_DCODE(status)); } else {
static int smbus_xfer(struct i2c_adapter *i2c_adap, u16 addr, unsigned short flags, char read_write, u8 command, int size, union i2c_smbus_data * data) { struct i2c_algo_sibyte_data *adap = i2c_adap->algo_data; int data_bytes = 0; int error; while (csr_in32(SMB_CSR(adap, R_SMB_STATUS)) & M_SMB_BUSY) ; switch (size) { case I2C_SMBUS_QUICK: csr_out32((V_SMB_ADDR(addr) | (read_write == I2C_SMBUS_READ ? M_SMB_QDATA : 0) | V_SMB_TT_QUICKCMD), SMB_CSR(adap, R_SMB_START)); break; case I2C_SMBUS_BYTE: if (read_write == I2C_SMBUS_READ) { csr_out32((V_SMB_ADDR(addr) | V_SMB_TT_RD1BYTE), SMB_CSR(adap, R_SMB_START)); data_bytes = 1; } else { csr_out32(V_SMB_CMD(command), SMB_CSR(adap, R_SMB_CMD)); csr_out32((V_SMB_ADDR(addr) | V_SMB_TT_WR1BYTE), SMB_CSR(adap, R_SMB_START)); } break; case I2C_SMBUS_BYTE_DATA: csr_out32(V_SMB_CMD(command), SMB_CSR(adap, R_SMB_CMD)); if (read_write == I2C_SMBUS_READ) { csr_out32((V_SMB_ADDR(addr) | V_SMB_TT_CMD_RD1BYTE), SMB_CSR(adap, R_SMB_START)); data_bytes = 1; } else { csr_out32(V_SMB_LB(data->byte), SMB_CSR(adap, R_SMB_DATA)); csr_out32((V_SMB_ADDR(addr) | V_SMB_TT_WR2BYTE), SMB_CSR(adap, R_SMB_START)); } break; case I2C_SMBUS_WORD_DATA: csr_out32(V_SMB_CMD(command), SMB_CSR(adap, R_SMB_CMD)); if (read_write == I2C_SMBUS_READ) { csr_out32((V_SMB_ADDR(addr) | V_SMB_TT_CMD_RD2BYTE), SMB_CSR(adap, R_SMB_START)); data_bytes = 2; } else { csr_out32(V_SMB_LB(data->word & 0xff), SMB_CSR(adap, R_SMB_DATA)); csr_out32(V_SMB_MB(data->word >> 8), SMB_CSR(adap, R_SMB_DATA)); csr_out32((V_SMB_ADDR(addr) | V_SMB_TT_WR2BYTE), SMB_CSR(adap, R_SMB_START)); } break; default: return -1; /* XXXKW better error code? */ } while (csr_in32(SMB_CSR(adap, R_SMB_STATUS)) & M_SMB_BUSY) ; error = csr_in32(SMB_CSR(adap, R_SMB_STATUS)); if (error & M_SMB_ERROR) { /* Clear error bit by writing a 1 */ csr_out32(M_SMB_ERROR, SMB_CSR(adap, R_SMB_STATUS)); return -1; /* XXXKW better error code? */ } if (data_bytes == 1) data->byte = csr_in32(SMB_CSR(adap, R_SMB_DATA)) & 0xff; if (data_bytes == 2) data->word = csr_in32(SMB_CSR(adap, R_SMB_DATA)) & 0xffff; return 0; }