void scsi_curio_dbdma_init(int unit) { device_node_t *curio; scsi_curio_dbdma_commands = dbdma_alloc(2); curio = find_devices("53c94"); curio_chan = (dbdma_regmap_t *) POWERMAC_IO(curio->addrs[1].address); }
hide void mc_attach(device_t parent, device_t self, void *aux) { struct confargs *ca = aux; struct mc_softc *sc = device_private(self); u_int8_t myaddr[ETHER_ADDR_LEN]; u_int *reg; sc->sc_dev = self; sc->sc_node = ca->ca_node; sc->sc_regt = ca->ca_tag; reg = ca->ca_reg; reg[0] += ca->ca_baseaddr; reg[2] += ca->ca_baseaddr; reg[4] += ca->ca_baseaddr; sc->sc_txdma = mapiodev(reg[2], reg[3], false); sc->sc_rxdma = mapiodev(reg[4], reg[5], false); bus_space_map(sc->sc_regt, reg[0], reg[1], 0, &sc->sc_regh); sc->sc_tail = 0; sc->sc_txdmacmd = dbdma_alloc(sizeof(dbdma_command_t) * 2, NULL); sc->sc_rxdmacmd = (void *)dbdma_alloc(sizeof(dbdma_command_t) * 8, NULL); memset(sc->sc_txdmacmd, 0, sizeof(dbdma_command_t) * 2); memset(sc->sc_rxdmacmd, 0, sizeof(dbdma_command_t) * 8); printf(": irq %d,%d,%d", ca->ca_intr[0], ca->ca_intr[1], ca->ca_intr[2]); if (OF_getprop(sc->sc_node, "local-mac-address", myaddr, 6) != 6) { printf(": failed to get MAC address.\n"); return; } /* allocate memory for transmit buffer and mark it non-cacheable */ sc->sc_txbuf = malloc(PAGE_SIZE, M_DEVBUF, M_WAITOK); sc->sc_txbuf_phys = kvtop(sc->sc_txbuf); memset(sc->sc_txbuf, 0, PAGE_SIZE); /* * allocate memory for receive buffer and mark it non-cacheable * XXX This should use the bus_dma interface, since the buffer * needs to be physically contiguous. However, it seems that * at least on my system, malloc() does allocate contiguous * memory. If it's not, suggest reducing the number of buffers * to 2, which will fit in one 4K page. */ sc->sc_rxbuf = malloc(MC_NPAGES * PAGE_SIZE, M_DEVBUF, M_WAITOK); sc->sc_rxbuf_phys = kvtop(sc->sc_rxbuf); memset(sc->sc_rxbuf, 0, MC_NPAGES * PAGE_SIZE); if ((int)sc->sc_txbuf & PGOFSET) printf("txbuf is not page-aligned\n"); if ((int)sc->sc_rxbuf & PGOFSET) printf("rxbuf is not page-aligned\n"); sc->sc_bus_init = mc_init; sc->sc_putpacket = mc_putpacket; /* disable receive DMA */ dbdma_reset(sc->sc_rxdma); /* disable transmit DMA */ dbdma_reset(sc->sc_txdma); /* install interrupt handlers */ /*intr_establish(ca->ca_intr[1], IST_EDGE, IPL_NET, mc_dmaintr, sc);*/ intr_establish(ca->ca_intr[2], IST_EDGE, IPL_NET, mc_dmaintr, sc); intr_establish(ca->ca_intr[0], IST_EDGE, IPL_NET, mcintr, sc); sc->sc_biucc = XMTSP_64; sc->sc_fifocc = XMTFW_16 | RCVFW_64 | XMTFWU | RCVFWU | XMTBRST | RCVBRST; /*sc->sc_plscc = PORTSEL_10BT;*/ sc->sc_plscc = PORTSEL_GPSI | ENPLSIO; /* mcsetup returns 1 if something fails */ if (mcsetup(sc, myaddr)) { printf("mcsetup returns non zero\n"); return; } #ifdef NOTYET sc->sc_mediachange = mc_mediachange; sc->sc_mediastatus = mc_mediastatus; sc->sc_supmedia = mc_supmedia; sc->sc_nsupmedia = N_SUPMEDIA; sc->sc_defaultmedia = IFM_ETHER | IFM_10_T; #endif }
/* * Attach a found zs. * * Match slave number to zs unit number, so that misconfiguration will * not set up the keyboard as ttya, etc. */ void zsc_attach(struct device *parent, struct device *self, void *aux) { struct zsc_softc *zsc = (void *)self; struct confargs *ca = aux; struct zsc_attach_args zsc_args; volatile struct zschan *zc; struct xzs_chanstate *xcs; struct zs_chanstate *cs; struct zsdevice *zsd; int zsc_unit, channel; int s, theflags; int node, intr[3][3]; u_int regs[16]; zsc_unit = zsc->zsc_dev.dv_unit; zsd = mapiodev(ca->ca_baseaddr + ca->ca_reg[0], ca->ca_reg[1]); node = OF_child(ca->ca_node); /* ch-a */ for (channel = 0; channel < 2; channel++) { if (OF_getprop(node, "AAPL,interrupts", intr[channel], sizeof(intr[0])) == -1 && OF_getprop(node, "interrupts", intr[channel], sizeof(intr[0])) == -1) { printf(": cannot find interrupt property\n"); return; } if (OF_getprop(node, "reg", regs, sizeof(regs)) < 24) { printf(": cannot find reg property\n"); return; } regs[2] += ca->ca_baseaddr; regs[4] += ca->ca_baseaddr; #ifdef ZS_TXDMA zsc->zsc_txdmareg[channel] = mapiodev(regs[2], regs[3]); zsc->zsc_txdmacmd[channel] = dbdma_alloc(sizeof(dbdma_command_t) * 3); memset(zsc->zsc_txdmacmd[channel], 0, sizeof(dbdma_command_t) * 3); dbdma_reset(zsc->zsc_txdmareg[channel]); #endif node = OF_peer(node); /* ch-b */ } printf(": irq %d,%d\n", intr[0][0], intr[1][0]); /* * Initialize software state for each channel. */ for (channel = 0; channel < 2; channel++) { zsc_args.channel = channel; zsc_args.hwflags = zs_hwflags[zsc_unit][channel]; xcs = &zsc->xzsc_xcs_store[channel]; cs = &xcs->xzs_cs; zsc->zsc_cs[channel] = cs; cs->cs_channel = channel; cs->cs_private = NULL; cs->cs_ops = &zsops_null; zc = (channel == 0) ? &zsd->zs_chan_a : &zsd->zs_chan_b; cs->cs_reg_csr = &zc->zc_csr; cs->cs_reg_data = &zc->zc_data; memcpy(cs->cs_creg, zs_init_reg, 16); memcpy(cs->cs_preg, zs_init_reg, 16); /* Current BAUD rate generator clock. */ /* RTxC is 230400*16, so use 230400 */ cs->cs_brg_clk = PCLK / 16; if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) cs->cs_defspeed = zs_get_speed(cs); else cs->cs_defspeed = zs_defspeed[zsc_unit][channel]; cs->cs_defcflag = zs_def_cflag; /* Make these correspond to cs_defcflag (-crtscts) */ cs->cs_rr0_dcd = ZSRR0_DCD; cs->cs_rr0_cts = 0; cs->cs_wr5_dtr = ZSWR5_DTR; cs->cs_wr5_rts = 0; #ifdef __notyet__ cs->cs_slave_type = ZS_SLAVE_NONE; #endif /* Define BAUD rate stuff. */ xcs->cs_clocks[0].clk = PCLK; xcs->cs_clocks[0].flags = ZSC_RTXBRG | ZSC_RTXDIV; xcs->cs_clocks[1].flags = ZSC_RTXBRG | ZSC_RTXDIV | ZSC_VARIABLE | ZSC_EXTERN; xcs->cs_clocks[2].flags = ZSC_TRXDIV | ZSC_VARIABLE; xcs->cs_clock_count = 3; if (channel == 0) { theflags = 0; /*mac68k_machine.modem_flags;*/ /*xcs->cs_clocks[1].clk = mac68k_machine.modem_dcd_clk;*/ /*xcs->cs_clocks[2].clk = mac68k_machine.modem_cts_clk;*/ xcs->cs_clocks[1].clk = 0; xcs->cs_clocks[2].clk = 0; } else { theflags = 0; /*mac68k_machine.print_flags;*/ xcs->cs_clocks[1].flags = ZSC_VARIABLE; /* * Yes, we aren't defining ANY clock source enables for the * printer's DCD clock in. The hardware won't let us * use it. But a clock will freak out the chip, so we * let you set it, telling us to bar interrupts on the line. */ /*xcs->cs_clocks[1].clk = mac68k_machine.print_dcd_clk;*/ /*xcs->cs_clocks[2].clk = mac68k_machine.print_cts_clk;*/ xcs->cs_clocks[1].clk = 0; xcs->cs_clocks[2].clk = 0; } if (xcs->cs_clocks[1].clk) zsc_args.hwflags |= ZS_HWFLAG_NO_DCD; if (xcs->cs_clocks[2].clk) zsc_args.hwflags |= ZS_HWFLAG_NO_CTS; /* Set defaults in our "extended" chanstate. */ xcs->cs_csource = 0; xcs->cs_psource = 0; xcs->cs_cclk_flag = 0; /* Nothing fancy by default */ xcs->cs_pclk_flag = 0; if (theflags & ZSMAC_RAW) { zsc_args.hwflags |= ZS_HWFLAG_RAW; printf(" (raw defaults)"); } /* * XXX - This might be better done with a "stub" driver * (to replace zstty) that ignores LocalTalk for now. */ if (theflags & ZSMAC_LOCALTALK) { printf(" shielding from LocalTalk"); cs->cs_defspeed = 1; cs->cs_creg[ZSRR_BAUDLO] = cs->cs_preg[ZSRR_BAUDLO] = 0xff; cs->cs_creg[ZSRR_BAUDHI] = cs->cs_preg[ZSRR_BAUDHI] = 0xff; zs_write_reg(cs, ZSRR_BAUDLO, 0xff); zs_write_reg(cs, ZSRR_BAUDHI, 0xff); /* * If we might have LocalTalk, then make sure we have the * Baud rate low-enough to not do any damage. */ } /* * We used to disable chip interrupts here, but we now * do that in zscnprobe, just in case MacOS left the chip on. */ xcs->cs_chip = 0; /* Stash away a copy of the final H/W flags. */ xcs->cs_hwflags = zsc_args.hwflags; /* * Look for a child driver for this channel. * The child attach will setup the hardware. */ if (!config_found(self, (void *)&zsc_args, zsc_print)) { /* No sub-driver. Just reset it. */ u_char reset = (channel == 0) ? ZSWR9_A_RESET : ZSWR9_B_RESET; s = splzs(); zs_write_reg(cs, 9, reset); splx(s); } } /* XXX - Now safe to install interrupt handlers. */ mac_intr_establish(parent, intr[0][0], IST_LEVEL, IPL_TTY, zshard, NULL, "zs0"); mac_intr_establish(parent, intr[1][0], IST_LEVEL, IPL_TTY, zshard, NULL, "zs1"); #ifdef ZS_TXDMA mac_intr_establish(parent, intr[0][1], IST_LEVEL, IPL_TTY, zs_txdma_int, (void *)0, "zsdma0"); mac_intr_establish(parent, intr[1][1], IST_LEVEL, IPL_TTY, zs_txdma_int, (void *)1, "zsdma1"); #endif zsc->zsc_softintr = softintr_establish(IPL_SOFTTTY, zssoft, zsc); if (zsc->zsc_softintr == NULL) panic("zsattach: could not establish soft interrupt"); /* * Set the master interrupt enable and interrupt vector. * (common to both channels, do it on A) */ cs = zsc->zsc_cs[0]; s = splzs(); /* interrupt vector */ zs_write_reg(cs, 2, zs_init_reg[2]); /* master interrupt control (enable) */ zs_write_reg(cs, 9, zs_init_reg[9]); splx(s); /* connect power management for port 0 */ cs->enable = zs_enable; cs->disable = zs_disable; }
/* * Attach this instance, and then all the sub-devices */ void espattach(device_t parent, device_t self, void *aux) { struct esp_softc *esc = device_private(self); struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; struct confargs *ca = aux; u_int *reg; int sz; /* * Set up glue for MI code early; we use some of it here. */ sc->sc_dev = self; sc->sc_glue = &esp_glue; esc->sc_node = ca->ca_node; esc->sc_pri = ca->ca_intr[0]; aprint_normal(" irq %d", esc->sc_pri); /* * Map my registers in. */ reg = ca->ca_reg; esc->sc_reg = mapiodev(ca->ca_baseaddr + reg[0], reg[1]); esc->sc_dmareg = mapiodev(ca->ca_baseaddr + reg[2], reg[3]); /* Allocate 16-byte aligned DMA command space */ esc->sc_dmacmd = dbdma_alloc(sizeof(dbdma_command_t) * 20); /* Other settings */ sc->sc_id = 7; sz = OF_getprop(ca->ca_node, "clock-frequency", &sc->sc_freq, sizeof(int)); if (sz != sizeof(int)) sc->sc_freq = 25000000; /* gimme MHz */ sc->sc_freq /= 1000000; /* esc->sc_dma->sc_esp = esc;*/ /* * XXX More of this should be in ncr53c9x_attach(), but * XXX should we really poke around the chip that much in * XXX the MI code? Think about this more... */ /* * Set up static configuration info. */ sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; sc->sc_cfg2 = NCRCFG2_SCSI2; /* | NCRCFG2_FE */ sc->sc_cfg3 = NCRCFG3_CDB; sc->sc_rev = NCR_VARIANT_NCR53C94; /* * XXX minsync and maxxfer _should_ be set up in MI code, * XXX but it appears to have some dependency on what sort * XXX of DMA we're hooked up to, etc. */ /* * This is the value used to start sync negotiations * Note that the NCR register "SYNCTP" is programmed * in "clocks per byte", and has a minimum value of 4. * The SCSI period used in negotiation is one-fourth * of the time (in nanoseconds) needed to transfer one byte. * Since the chip's clock is given in MHz, we have the following * formula: 4 * period = (1000 / freq) * 4 */ sc->sc_minsync = 1000 / sc->sc_freq; sc->sc_maxxfer = 64 * 1024; /* and the interuppts */ intr_establish(esc->sc_pri, IST_EDGE, IPL_BIO, ncr53c9x_intr, sc); /* Reset SCSI bus when halt. */ shutdownhook_establish(esp_shutdownhook, sc); /* Do the common parts of attachment. */ sc->sc_adapter.adapt_minphys = minphys; sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; ncr53c9x_attach(sc); /* Turn on target selection using the `DMA' method */ sc->sc_features |= NCR_F_DMASELECT; }
/* * Attach this instance, and then all the sub-devices */ void espattach(struct device *parent, struct device *self, void *aux) { struct confargs *ca = aux; struct esp_softc *esc = (void *)self; struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; u_int *reg; int sz, error; /* * Set up glue for MI code early; we use some of it here. */ sc->sc_glue = &esp_glue; esc->sc_node = ca->ca_node; esc->sc_intr = ca->ca_intr[0]; printf(" irq %d", esc->sc_intr); /* * Map my registers in. */ reg = ca->ca_reg; esc->sc_reg = mapiodev(ca->ca_baseaddr + reg[0], reg[1]); esc->sc_dmareg = mapiodev(ca->ca_baseaddr + reg[2], reg[3]); esc->sc_dmat = ca->ca_dmat; if ((error = bus_dmamap_create(esc->sc_dmat, ESP_DMALIST_MAX * DBDMA_COUNT_MAX, ESP_DMALIST_MAX, DBDMA_COUNT_MAX, NBPG, BUS_DMA_NOWAIT, &esc->sc_dmamap)) != 0) { printf(": cannot create dma map, error = %d\n", error); return; } /* Allocate 16-byte aligned DMA command space */ esc->sc_dbdma = dbdma_alloc(esc->sc_dmat, ESP_DMALIST_MAX); esc->sc_dmacmd = esc->sc_dbdma->d_addr; /* Other settings */ sc->sc_id = 7; sz = OF_getprop(ca->ca_node, "clock-frequency", &sc->sc_freq, sizeof(int)); if (sz != sizeof(int)) sc->sc_freq = 25000000; /* gimme MHz */ sc->sc_freq /= 1000000; /* * Set up static configuration info. */ sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; sc->sc_cfg2 = NCRCFG2_SCSI2; /* | NCRCFG2_FE */ sc->sc_cfg3 = NCRCFG3_CDB; sc->sc_rev = NCR_VARIANT_NCR53C94; /* * This is the value used to start sync negotiations * Note that the NCR register "SYNCTP" is programmed * in "clocks per byte", and has a minimum value of 4. * The SCSI period used in negotiation is one-fourth * of the time (in nanoseconds) needed to transfer one byte. * Since the chip's clock is given in MHz, we have the following * formula: 4 * period = (1000 / freq) * 4 */ sc->sc_minsync = 1000 / sc->sc_freq; sc->sc_maxxfer = 64 * 1024; /* and the interuppts */ mac_intr_establish(parent, esc->sc_intr, IST_LEVEL, IPL_BIO, ncr53c9x_intr, sc, sc->sc_dev.dv_xname); /* Turn on target selection using the `DMA' method */ sc->sc_features |= NCR_F_DMASELECT; ncr53c9x_attach(sc); }
void wdc_obio_attach(struct device *parent, struct device *self, void *aux) { struct wdc_obio_softc *sc = (void *)self; struct confargs *ca = aux; struct channel_softc *chp = &sc->wdc_channel; int intr, error; bus_addr_t cmdbase; sc->sc_use_dma = 0; if (ca->ca_nreg >= 16) sc->sc_use_dma = 1; /* Enable dma */ sc->sc_dmat = ca->ca_dmat; if ((error = bus_dmamap_create(sc->sc_dmat, WDC_DMALIST_MAX * DBDMA_COUNT_MAX, WDC_DMALIST_MAX, DBDMA_COUNT_MAX, NBPG, BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { printf(": cannot create dma map, error = %d\n", error); return; } if (ca->ca_nintr >= 4 && ca->ca_nreg >= 8) { intr = ca->ca_intr[0]; printf(" irq %d", intr); } else if (ca->ca_nintr == -1) { intr = WDC_DEFAULT_PIO_IRQ; printf(" irq property not found; using %d", intr); } else { printf(": couldn't get irq property\n"); return; } if (sc->sc_use_dma) printf(": DMA"); printf("\n"); chp->cmd_iot = chp->ctl_iot = ca->ca_iot; chp->_vtbl = &wdc_obio_vtbl; cmdbase = ca->ca_reg[0]; sc->sc_cmdsize = ca->ca_reg[1]; if (bus_space_map(chp->cmd_iot, cmdbase, sc->sc_cmdsize, 0, &chp->cmd_ioh) || bus_space_subregion(chp->cmd_iot, chp->cmd_ioh, /* WDC_AUXREG_OFFSET<<4 */ 0x160, 1, &chp->ctl_ioh)) { printf("%s: couldn't map registers\n", sc->sc_wdcdev.sc_dev.dv_xname); return; } chp->data32iot = chp->cmd_iot; chp->data32ioh = chp->cmd_ioh; sc->sc_ih = mac_intr_establish(parent, intr, IST_LEVEL, IPL_BIO, wdcintr, chp, sc->sc_wdcdev.sc_dev.dv_xname); sc->sc_wdcdev.set_modes = wdc_obio_adjust_timing; if (sc->sc_use_dma) { sc->sc_dbdma = dbdma_alloc(sc->sc_dmat, WDC_DMALIST_MAX + 1); sc->sc_dmacmd = sc->sc_dbdma->d_addr; sc->sc_dmareg = mapiodev(ca->ca_baseaddr + ca->ca_reg[2], sc->sc_dmasize = ca->ca_reg[3]); sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; sc->sc_wdcdev.DMA_cap = 2; if (strcmp(ca->ca_name, "ata-4") == 0) { sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA | WDC_CAPABILITY_MODE; sc->sc_wdcdev.UDMA_cap = 4; sc->sc_wdcdev.set_modes = wdc_obio_ata4_adjust_timing; } if (strcmp(ca->ca_name, "ata-6") == 0) { sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA | WDC_CAPABILITY_MODE; sc->sc_wdcdev.UDMA_cap = 5; sc->sc_wdcdev.set_modes = wdc_obio_ata6_adjust_timing; } } sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; sc->sc_wdcdev.PIO_cap = 4; sc->wdc_chanptr = chp; sc->sc_wdcdev.channels = &sc->wdc_chanptr; sc->sc_wdcdev.nchannels = 1; sc->sc_wdcdev.dma_arg = sc; sc->sc_wdcdev.dma_init = wdc_obio_dma_init; sc->sc_wdcdev.dma_start = wdc_obio_dma_start; sc->sc_wdcdev.dma_finish = wdc_obio_dma_finish; chp->channel = 0; chp->wdc = &sc->sc_wdcdev; chp->ch_queue = malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); if (chp->ch_queue == NULL) { printf("%s: can't allocate memory for command queue", sc->sc_wdcdev.sc_dev.dv_xname); return; } wdcattach(chp); sc->sc_wdcdev.set_modes(chp); wdc_print_current_modes(chp); }
void bmac_attach(struct device *parent, struct device *self, void *aux) { struct confargs *ca = aux; struct bmac_softc *sc = (void *)self; struct ifnet *ifp = &sc->arpcom.ac_if; struct mii_data *mii = &sc->sc_mii; u_char laddr[6]; int nseg, error; timeout_set(&sc->sc_tick_ch, bmac_mii_tick, sc); sc->sc_flags =0; if (strcmp(ca->ca_name, "ethernet") == 0) { sc->sc_flags |= BMAC_BMACPLUS; } ca->ca_reg[0] += ca->ca_baseaddr; ca->ca_reg[2] += ca->ca_baseaddr; ca->ca_reg[4] += ca->ca_baseaddr; sc->sc_regs = (vaddr_t)mapiodev(ca->ca_reg[0], NBPG); bmac_write_reg(sc, INTDISABLE, NoEventsMask); if (OF_getprop(ca->ca_node, "local-mac-address", laddr, 6) == -1 && OF_getprop(ca->ca_node, "mac-address", laddr, 6) == -1) { printf(": cannot get mac-address\n"); return; } bcopy(laddr, sc->arpcom.ac_enaddr, 6); sc->sc_dmat = ca->ca_dmat; sc->sc_txdma = mapiodev(ca->ca_reg[2], 0x100); sc->sc_rxdma = mapiodev(ca->ca_reg[4], 0x100); sc->sc_txdbdma = dbdma_alloc(sc->sc_dmat, BMAC_TXBUFS); sc->sc_txcmd = sc->sc_txdbdma->d_addr; sc->sc_rxdbdma = dbdma_alloc(sc->sc_dmat, BMAC_RXBUFS + 1); sc->sc_rxcmd = sc->sc_rxdbdma->d_addr; error = bus_dmamem_alloc(sc->sc_dmat, BMAC_BUFSZ, PAGE_SIZE, 0, sc->sc_bufseg, 1, &nseg, BUS_DMA_NOWAIT); if (error) { printf(": cannot allocate buffers (%d)\n", error); return; } error = bus_dmamem_map(sc->sc_dmat, sc->sc_bufseg, nseg, BMAC_BUFSZ, &sc->sc_txbuf, BUS_DMA_NOWAIT); if (error) { printf(": cannot map buffers (%d)\n", error); bus_dmamem_free(sc->sc_dmat, sc->sc_bufseg, 1); return; } error = bus_dmamap_create(sc->sc_dmat, BMAC_BUFSZ, 1, BMAC_BUFSZ, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sc->sc_bufmap); if (error) { printf(": cannot create buffer dmamap (%d)\n", error); bus_dmamem_unmap(sc->sc_dmat, sc->sc_txbuf, BMAC_BUFSZ); bus_dmamem_free(sc->sc_dmat, sc->sc_bufseg, 1); return; } error = bus_dmamap_load(sc->sc_dmat, sc->sc_bufmap, sc->sc_txbuf, BMAC_BUFSZ, NULL, BUS_DMA_NOWAIT); if (error) { printf(": cannot load buffers dmamap (%d)\n", error); bus_dmamap_destroy(sc->sc_dmat, sc->sc_bufmap); bus_dmamem_unmap(sc->sc_dmat, sc->sc_txbuf, BMAC_BUFSZ); bus_dmamem_free(sc->sc_dmat, sc->sc_bufseg, nseg); return; } sc->sc_txbuf_pa = sc->sc_bufmap->dm_segs->ds_addr; sc->sc_rxbuf = sc->sc_txbuf + BMAC_BUFLEN * BMAC_TXBUFS; sc->sc_rxbuf_pa = sc->sc_txbuf_pa + BMAC_BUFLEN * BMAC_TXBUFS; printf(" irq %d,%d: address %s\n", ca->ca_intr[0], ca->ca_intr[2], ether_sprintf(laddr)); mac_intr_establish(parent, ca->ca_intr[0], IST_LEVEL, IPL_NET, bmac_intr, sc, sc->sc_dev.dv_xname); mac_intr_establish(parent, ca->ca_intr[2], IST_LEVEL, IPL_NET, bmac_rint, sc, sc->sc_dev.dv_xname); bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); ifp->if_softc = sc; ifp->if_ioctl = bmac_ioctl; ifp->if_start = bmac_start; ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; ifp->if_watchdog = bmac_watchdog; IFQ_SET_READY(&ifp->if_snd); mii->mii_ifp = ifp; mii->mii_readreg = bmac_mii_readreg; mii->mii_writereg = bmac_mii_writereg; mii->mii_statchg = bmac_mii_statchg; ifmedia_init(&mii->mii_media, 0, bmac_mediachange, bmac_mediastatus); mii_attach(&sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0); /* Choose a default media. */ if (LIST_FIRST(&mii->mii_phys) == NULL) { ifmedia_add(&mii->mii_media, IFM_ETHER|IFM_10_T, 0, NULL); ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_10_T); } else ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_AUTO); bmac_reset_chip(sc); if_attach(ifp); ether_ifattach(ifp); }
void mc_attach(struct device *parent, struct device *self, void *aux) { struct confargs *ca = aux; struct mc_softc *sc = (struct mc_softc *)self; struct ifnet *ifp = &sc->sc_arpcom.ac_if; u_int8_t lladdr[ETHER_ADDR_LEN]; int nseg, error; if (OF_getprop(ca->ca_node, "local-mac-address", lladdr, ETHER_ADDR_LEN) != ETHER_ADDR_LEN) { printf(": failed to get MAC address.\n"); return; } ca->ca_reg[0] += ca->ca_baseaddr; ca->ca_reg[2] += ca->ca_baseaddr; ca->ca_reg[4] += ca->ca_baseaddr; if ((sc->sc_reg = mapiodev(ca->ca_reg[0], ca->ca_reg[1])) == NULL) { printf(": cannot map registers\n"); return; } sc->sc_dmat = ca->ca_dmat; sc->sc_tail = 0; if ((sc->sc_txdma = mapiodev(ca->ca_reg[2], ca->ca_reg[3])) == NULL) { printf(": cannot map TX DMA registers\n"); goto notxdma; } if ((sc->sc_rxdma = mapiodev(ca->ca_reg[4], ca->ca_reg[5])) == NULL) { printf(": cannot map RX DMA registers\n"); goto norxdma; } if ((sc->sc_txdbdma = dbdma_alloc(sc->sc_dmat, 2)) == NULL) { printf(": cannot alloc TX DMA descriptors\n"); goto notxdbdma; } sc->sc_txdmacmd = sc->sc_txdbdma->d_addr; if ((sc->sc_rxdbdma = dbdma_alloc(sc->sc_dmat, 8 + 1)) == NULL) { printf(": cannot alloc RX DMA descriptors\n"); goto norxdbdma; } sc->sc_rxdmacmd = sc->sc_rxdbdma->d_addr; if ((error = bus_dmamem_alloc(sc->sc_dmat, MACE_BUFSZ, PAGE_SIZE, 0, sc->sc_bufseg, 1, &nseg, BUS_DMA_NOWAIT))) { printf(": cannot allocate DMA mem (%d)\n", error); goto nodmamem; } if ((error = bus_dmamem_map(sc->sc_dmat, sc->sc_bufseg, nseg, MACE_BUFSZ, &sc->sc_txbuf, BUS_DMA_NOWAIT))) { printf(": cannot map DMA mem (%d)\n", error); goto nodmamap; } if ((error = bus_dmamap_create(sc->sc_dmat, MACE_BUFSZ, 1, MACE_BUFSZ, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sc->sc_bufmap))) { printf(": cannot create DMA map (%d)\n", error); goto nodmacreate; } if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_bufmap, sc->sc_txbuf, MACE_BUFSZ, NULL, BUS_DMA_NOWAIT))) { printf(": cannot load DMA map (%d)\n", error); goto nodmaload; } sc->sc_txbuf_pa = sc->sc_bufmap->dm_segs->ds_addr; sc->sc_rxbuf = sc->sc_txbuf + MACE_BUFLEN * MACE_TXBUFS; sc->sc_rxbuf_pa = sc->sc_txbuf_pa + MACE_BUFLEN * MACE_TXBUFS; printf(": irq %d,%d,%d", ca->ca_intr[0], ca->ca_intr[1], ca->ca_intr[2]); /* disable receive DMA */ dbdma_reset(sc->sc_rxdma); /* disable transmit DMA */ dbdma_reset(sc->sc_txdma); /* install interrupt handlers */ mac_intr_establish(parent, ca->ca_intr[2], IST_LEVEL, IPL_NET, mc_dmaintr, sc, sc->sc_dev.dv_xname); mac_intr_establish(parent, ca->ca_intr[0], IST_LEVEL, IPL_NET, mc_intr, sc, sc->sc_dev.dv_xname); sc->sc_biucc = XMTSP_64; sc->sc_fifocc = XMTFW_16 | RCVFW_64 | XMTFWU | RCVFWU | XMTBRST | RCVBRST; sc->sc_plscc = PORTSEL_GPSI | ENPLSIO; /* reset the chip and disable all interrupts */ NIC_PUT(sc, MACE_BIUCC, SWRST); DELAY(100); NIC_PUT(sc, MACE_IMR, ~0); bcopy(lladdr, sc->sc_enaddr, ETHER_ADDR_LEN); bcopy(sc->sc_enaddr, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN); printf(": address %s\n", ether_sprintf(lladdr)); bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); ifp->if_softc = sc; ifp->if_ioctl = mc_ioctl; ifp->if_start = mc_start; ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; ifp->if_watchdog = mc_watchdog; ifp->if_timer = 0; IFQ_SET_READY(&ifp->if_snd); if_attach(ifp); ether_ifattach(ifp); return; nodmaload: bus_dmamap_destroy(sc->sc_dmat, sc->sc_bufmap); nodmacreate: bus_dmamem_unmap(sc->sc_dmat, sc->sc_txbuf, MACE_BUFSZ); nodmamap: bus_dmamem_free(sc->sc_dmat, sc->sc_bufseg, 1); nodmamem: dbdma_free(sc->sc_rxdbdma); norxdbdma: dbdma_free(sc->sc_txdbdma); notxdbdma: unmapiodev((void *)sc->sc_rxdma, ca->ca_reg[5]); norxdma: unmapiodev((void *)sc->sc_txdma, ca->ca_reg[3]); notxdma: unmapiodev(sc->sc_reg, ca->ca_reg[1]); }
void bmac_attach(struct device *parent, struct device *self, void *aux) { struct confargs *ca = aux; struct bmac_softc *sc = (void *)self; struct ifnet *ifp = &sc->sc_if; struct mii_data *mii = &sc->sc_mii; u_char laddr[6]; callout_init(&sc->sc_tick_ch, 0); sc->sc_flags =0; if (strcmp(ca->ca_name, "ethernet") == 0) { char name[64]; memset(name, 0, 64); OF_package_to_path(ca->ca_node, name, sizeof(name)); OF_open(name); sc->sc_flags |= BMAC_BMACPLUS; } ca->ca_reg[0] += ca->ca_baseaddr; ca->ca_reg[2] += ca->ca_baseaddr; ca->ca_reg[4] += ca->ca_baseaddr; sc->sc_iot = ca->ca_tag; if (bus_space_map(sc->sc_iot, ca->ca_reg[0], ca->ca_reg[1], 0, &sc->sc_ioh) != 0) { aprint_error(": couldn't map %#x", ca->ca_reg[0]); return; } bmac_write_reg(sc, INTDISABLE, NoEventsMask); if (OF_getprop(ca->ca_node, "local-mac-address", laddr, 6) == -1 && OF_getprop(ca->ca_node, "mac-address", laddr, 6) == -1) { printf(": cannot get mac-address\n"); return; } memcpy(sc->sc_enaddr, laddr, 6); sc->sc_txdma = mapiodev(ca->ca_reg[2], PAGE_SIZE); sc->sc_rxdma = mapiodev(ca->ca_reg[4], PAGE_SIZE); sc->sc_txcmd = dbdma_alloc(BMAC_TXBUFS * sizeof(dbdma_command_t)); sc->sc_rxcmd = dbdma_alloc((BMAC_RXBUFS + 1) * sizeof(dbdma_command_t)); sc->sc_txbuf = malloc(BMAC_BUFLEN * BMAC_TXBUFS, M_DEVBUF, M_NOWAIT); sc->sc_rxbuf = malloc(BMAC_BUFLEN * BMAC_RXBUFS, M_DEVBUF, M_NOWAIT); if (sc->sc_txbuf == NULL || sc->sc_rxbuf == NULL || sc->sc_txcmd == NULL || sc->sc_rxcmd == NULL) { printf("cannot allocate memory\n"); return; } printf(" irq %d,%d: address %s\n", ca->ca_intr[0], ca->ca_intr[2], ether_sprintf(laddr)); intr_establish(ca->ca_intr[0], IST_EDGE, IPL_NET, bmac_intr, sc); intr_establish(ca->ca_intr[2], IST_EDGE, IPL_NET, bmac_rint, sc); memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); ifp->if_softc = sc; ifp->if_ioctl = bmac_ioctl; ifp->if_start = bmac_start; ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; ifp->if_watchdog = bmac_watchdog; IFQ_SET_READY(&ifp->if_snd); mii->mii_ifp = ifp; mii->mii_readreg = bmac_mii_readreg; mii->mii_writereg = bmac_mii_writereg; mii->mii_statchg = bmac_mii_statchg; sc->sc_ethercom.ec_mii = mii; ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); mii_attach(&sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0); /* Choose a default media. */ if (LIST_FIRST(&mii->mii_phys) == NULL) { ifmedia_add(&mii->mii_media, IFM_ETHER|IFM_10_T, 0, NULL); ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_10_T); } else ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_AUTO); bmac_reset_chip(sc); if_attach(ifp); ether_ifattach(ifp, sc->sc_enaddr); }
void xlights_attach(struct device *parent, struct device *self, void *aux) { struct xlights_softc *sc = (struct xlights_softc *)self; struct confargs *ca = aux; int nseg, error, intr[6]; u_int32_t reg[4]; int type; sc->sc_node = OF_child(ca->ca_node); OF_getprop(sc->sc_node, "reg", reg, sizeof(reg)); ca->ca_reg[0] += ca->ca_baseaddr; ca->ca_reg[2] += ca->ca_baseaddr; if ((sc->sc_reg = mapiodev(ca->ca_reg[0], ca->ca_reg[1])) == NULL) { printf(": cannot map registers\n"); return; } sc->sc_dmat = ca->ca_dmat; if ((sc->sc_dma = mapiodev(ca->ca_reg[2], ca->ca_reg[3])) == NULL) { printf(": cannot map DMA registers\n"); goto nodma; } if ((sc->sc_dbdma = dbdma_alloc(sc->sc_dmat, BL_DBDMA_CMDS)) == NULL) { printf(": cannot alloc DMA descriptors\n"); goto nodbdma; } sc->sc_dmacmd = sc->sc_dbdma->d_addr; if ((error = bus_dmamem_alloc(sc->sc_dmat, BL_BUFSZ, 0, 0, sc->sc_bufseg, 1, &nseg, BUS_DMA_NOWAIT))) { printf(": cannot allocate DMA mem (%d)\n", error); goto nodmamem; } if ((error = bus_dmamem_map(sc->sc_dmat, sc->sc_bufseg, nseg, BL_BUFSZ, (caddr_t *)&sc->sc_buf, BUS_DMA_NOWAIT))) { printf(": cannot map DMA mem (%d)\n", error); goto nodmamap; } sc->sc_bufpos = sc->sc_buf; if ((error = bus_dmamap_create(sc->sc_dmat, BL_BUFSZ, 1, BL_BUFSZ, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sc->sc_bufmap))) { printf(": cannot create DMA map (%d)\n", error); goto nodmacreate; } if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_bufmap, sc->sc_buf, BL_BUFSZ, NULL, BUS_DMA_NOWAIT))) { printf(": cannot load DMA map (%d)\n", error); goto nodmaload; } /* XXX: Should probably extract this from the clock data * property of the soundchip node */ sc->sc_freq = 16384; OF_getprop(sc->sc_node, "interrupts", intr, sizeof(intr)); /* output interrupt */ sc->sc_intr = intr[2]; type = intr[3] ? IST_LEVEL : IST_EDGE; printf(": irq %d\n", sc->sc_intr); macobio_enable(I2SClockOffset, I2S0EN); out32rb(sc->sc_reg + I2S_INT, I2S_INT_CLKSTOPPEND); macobio_disable(I2SClockOffset, I2S0CLKEN); for (error = 0; error < 1000; error++) { if (in32rb(sc->sc_reg + I2S_INT) & I2S_INT_CLKSTOPPEND) { error = 0; break; } delay(1); } if (error) { printf("%s: i2s timeout\n", sc->sc_dev.dv_xname); goto nodmaload; } mac_intr_establish(parent, sc->sc_intr, intr[3] ? IST_LEVEL : type, IPL_AUDIO, xlights_intr, sc, sc->sc_dev.dv_xname); out32rb(sc->sc_reg + I2S_FORMAT, CLKSRC_VS); macobio_enable(I2SClockOffset, I2S0CLKEN); kthread_create_deferred(xlights_deferred, sc); timeout_set(&sc->sc_tmo, xlights_timeout, sc); return; nodmaload: bus_dmamap_destroy(sc->sc_dmat, sc->sc_bufmap); nodmacreate: bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_buf, BL_BUFSZ); nodmamap: bus_dmamem_free(sc->sc_dmat, sc->sc_bufseg, nseg); nodmamem: dbdma_free(sc->sc_dbdma); nodbdma: unmapiodev((void *)sc->sc_dma, ca->ca_reg[3]); nodma: unmapiodev(sc->sc_reg, ca->ca_reg[1]); }
void wdc_obio_attach(device_t parent, device_t self, void *aux) { struct wdc_obio_softc *sc = device_private(self); struct wdc_regs *wdr; struct confargs *ca = aux; struct ata_channel *chp = &sc->sc_channel; int intr, i, type = IST_EDGE; int use_dma = 0; char path[80]; sc->sc_wdcdev.sc_atac.atac_dev = self; if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags & WDC_OPTIONS_DMA) { if (ca->ca_nreg >= 16 || ca->ca_nintr == -1) use_dma = 1; /* XXX Don't work yet. */ } if (ca->ca_nintr >= 4 && ca->ca_nreg >= 8) { intr = ca->ca_intr[0]; aprint_normal(" irq %d", intr); if (ca->ca_nintr > 8) { type = ca->ca_intr[1] ? IST_LEVEL : IST_EDGE; } aprint_normal(", %s triggered", (type == IST_EDGE) ? "edge" : "level"); } else if (ca->ca_nintr == -1) { intr = WDC_DEFAULT_PIO_IRQ; aprint_normal(" irq property not found; using %d", intr); } else { aprint_error(": couldn't get irq property\n"); return; } if (use_dma) aprint_normal(": DMA transfer"); aprint_normal("\n"); sc->sc_wdcdev.regs = wdr = &sc->sc_wdc_regs; wdr->cmd_iot = wdr->ctl_iot = ca->ca_tag; if (bus_space_map(wdr->cmd_iot, ca->ca_baseaddr + ca->ca_reg[0], WDC_REG_NPORTS << 4, 0, &wdr->cmd_baseioh) || bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, WDC_AUXREG_OFFSET << 4, 1, &wdr->ctl_ioh)) { aprint_error_dev(self, "couldn't map registers\n"); return; } for (i = 0; i < WDC_NREG; i++) { if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, i << 4, i == 0 ? 4 : 1, &wdr->cmd_iohs[i]) != 0) { bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, WDC_REG_NPORTS << 4); aprint_error_dev(self, "couldn't subregion registers\n"); return; } } #if 0 wdr->data32iot = wdr->cmd_iot; wdr->data32ioh = wdr->cmd_ioh; #endif sc->sc_ih = intr_establish(intr, type, IPL_BIO, wdcintr, chp); if (use_dma) { sc->sc_dmacmd = dbdma_alloc(sizeof(dbdma_command_t) * 20); /* * XXX * we don't use ca->ca_reg[3] for size here because at least * on the PB3400c it says 0x200 for both IDE channels ( the * one on the mainboard and the other on the mediabay ) but * their start addresses are only 0x100 apart. Since those * DMA registers are always 0x100 or less we don't really * have to care though */ if (bus_space_map(wdr->cmd_iot, ca->ca_baseaddr + ca->ca_reg[2], 0x100, BUS_SPACE_MAP_LINEAR, &sc->sc_dmaregh)) { aprint_error_dev(self, "unable to map DMA registers (%08x)\n", ca->ca_reg[2]); /* should unmap stuff here */ return; } sc->sc_dmareg = bus_space_vaddr(wdr->cmd_iot, sc->sc_dmaregh); sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; if (strcmp(ca->ca_name, "ata-4") == 0) { sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; sc->sc_wdcdev.sc_atac.atac_set_modes = ata4_adjust_timing; } else { sc->sc_wdcdev.sc_atac.atac_set_modes = adjust_timing; } #ifdef notyet /* Minimum cycle time is 150ns (DMA MODE 1) on ohare. */ if (ohare) { sc->sc_wdcdev.sc_atac.atac_pio_cap = 3; sc->sc_wdcdev.sc_atac.atac_dma_cap = 1; } #endif } else { /* all non-DMA controllers can use adjust_timing */ sc->sc_wdcdev.sc_atac.atac_set_modes = adjust_timing; } sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16; sc->sc_chanptr = chp; sc->sc_wdcdev.sc_atac.atac_channels = &sc->sc_chanptr; sc->sc_wdcdev.sc_atac.atac_nchannels = 1; sc->sc_wdcdev.wdc_maxdrives = 2; sc->sc_wdcdev.dma_arg = sc; sc->sc_wdcdev.dma_init = wdc_obio_dma_init; sc->sc_wdcdev.dma_start = wdc_obio_dma_start; sc->sc_wdcdev.dma_finish = wdc_obio_dma_finish; chp->ch_channel = 0; chp->ch_atac = &sc->sc_wdcdev.sc_atac; chp->ch_queue = &sc->sc_chqueue; wdc_init_shadow_regs(chp); #define OHARE_FEATURE_REG 0xf3000038 /* XXX Enable wdc1 by feature reg. */ memset(path, 0, sizeof(path)); OF_package_to_path(ca->ca_node, path, sizeof(path)); if (strcmp(path, "/bandit@F2000000/ohare@10/ata@21000") == 0) { u_int x; x = in32rb(OHARE_FEATURE_REG); x |= 8; out32rb(OHARE_FEATURE_REG, x); } wdcattach(chp); }