// Data Cache Block Zero Locked static bool dcbz_l(PPCEmuAssembler& a, Instruction instr) { return dcbz(a, instr); }
long int initdram (int board_type) { long dram_size = 0; #if !defined(CONFIG_RAM_AS_FLASH) volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); sys_info_t sysinfo; uint temp_lbcdll = 0; #endif #if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL) volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); #endif #if defined(CONFIG_DDR_DLL) uint temp_ddrdll = 0; /* Work around to stabilize DDR DLL */ temp_ddrdll = gur->ddrdllcr; gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; asm("sync;isync;msync"); #endif #if defined(CONFIG_SPD_EEPROM) dram_size = spd_sdram (); #else dram_size = fixed_sdram (); #endif #if defined(CFG_RAMBOOT) return dram_size; #endif #if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */ get_sys_info(&sysinfo); /* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */ if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) { lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000; } else { lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff; udelay(200); temp_lbcdll = gur->lbcdllcr; gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000; asm("sync;isync;msync"); } lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */ lbc->br2 = CFG_BR2_PRELIM; lbc->lbcr = CFG_LBC_LBCR; lbc->lsdmr = CFG_LBC_LSDMR_1; asm("sync"); * (ulong *)0 = 0x000000ff; lbc->lsdmr = CFG_LBC_LSDMR_2; asm("sync"); * (ulong *)0 = 0x000000ff; lbc->lsdmr = CFG_LBC_LSDMR_3; asm("sync"); * (ulong *)0 = 0x000000ff; lbc->lsdmr = CFG_LBC_LSDMR_4; asm("sync"); * (ulong *)0 = 0x000000ff; lbc->lsdmr = CFG_LBC_LSDMR_5; asm("sync"); lbc->lsrt = CFG_LBC_LSRT; asm("sync"); lbc->mrtpr = CFG_LBC_MRTPR; asm("sync"); #endif #if defined(CONFIG_DDR_ECC) { /* Initialize all of memory for ECC, then * enable errors */ uint *p = 0; uint i = 0; volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR); dma_init(); for (*p = 0; p < (uint *)(8 * 1024); p++) { if (((unsigned int)p & 0x1f) == 0) { dcbz(p); } *p = (unsigned int)0xdeadbeef; if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); } } /* 8K */ dma_xfer((uint *)0x2000,0x2000,(uint *)0); /* 16K */ dma_xfer((uint *)0x4000,0x4000,(uint *)0); /* 32K */ dma_xfer((uint *)0x8000,0x8000,(uint *)0); /* 64K */ dma_xfer((uint *)0x10000,0x10000,(uint *)0); /* 128k */ dma_xfer((uint *)0x20000,0x20000,(uint *)0); /* 256k */ dma_xfer((uint *)0x40000,0x40000,(uint *)0); /* 512k */ dma_xfer((uint *)0x80000,0x80000,(uint *)0); /* 1M */ dma_xfer((uint *)0x100000,0x100000,(uint *)0); /* 2M */ dma_xfer((uint *)0x200000,0x200000,(uint *)0); /* 4M */ dma_xfer((uint *)0x400000,0x400000,(uint *)0); for (i = 1; i < dram_size / 0x800000; i++) { dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0); } /* Enable errors for ECC */ ddr->err_disable = 0x00000000; asm("sync;isync;msync"); } #endif return dram_size; }
void C1_MacroAssembler::initialize_body(Register obj, Register tmp1, Register tmp2, int obj_size_in_bytes, int hdr_size_in_bytes) { const int index = (obj_size_in_bytes - hdr_size_in_bytes) / HeapWordSize; const int cl_size = VM_Version::L1_data_cache_line_size(), cl_dwords = cl_size>>3, cl_dw_addr_bits = exact_log2(cl_dwords); const Register tmp = R0, base_ptr = tmp1, cnt_dwords = tmp2; if (index <= 6) { // Use explicit NULL stores. if (index > 0) { li(tmp, 0); } for (int i = 0; i < index; ++i) { std(tmp, hdr_size_in_bytes + i * HeapWordSize, obj); } } else if (index < (2<<cl_dw_addr_bits)-1) { // simple loop Label loop; li(cnt_dwords, index); addi(base_ptr, obj, hdr_size_in_bytes); // Compute address of first element. li(tmp, 0); mtctr(cnt_dwords); // Load counter. bind(loop); std(tmp, 0, base_ptr); // Clear 8byte aligned block. addi(base_ptr, base_ptr, 8); bdnz(loop); } else { // like clear_memory_doubleword Label startloop, fast, fastloop, restloop, done; addi(base_ptr, obj, hdr_size_in_bytes); // Compute address of first element. load_const_optimized(cnt_dwords, index); rldicl_(tmp, base_ptr, 64-3, 64-cl_dw_addr_bits); // Extract dword offset within first cache line. beq(CCR0, fast); // Already 128byte aligned. subfic(tmp, tmp, cl_dwords); mtctr(tmp); // Set ctr to hit 128byte boundary (0<ctr<cl_dwords). subf(cnt_dwords, tmp, cnt_dwords); // rest. li(tmp, 0); bind(startloop); // Clear at the beginning to reach 128byte boundary. std(tmp, 0, base_ptr); // Clear 8byte aligned block. addi(base_ptr, base_ptr, 8); bdnz(startloop); bind(fast); // Clear 128byte blocks. srdi(tmp, cnt_dwords, cl_dw_addr_bits); // Loop count for 128byte loop (>0). andi(cnt_dwords, cnt_dwords, cl_dwords-1); // Rest in dwords. mtctr(tmp); // Load counter. bind(fastloop); dcbz(base_ptr); // Clear 128byte aligned block. addi(base_ptr, base_ptr, cl_size); bdnz(fastloop); cmpdi(CCR0, cnt_dwords, 0); // size 0? beq(CCR0, done); // rest == 0 li(tmp, 0); mtctr(cnt_dwords); // Load counter. bind(restloop); // Clear rest. std(tmp, 0, base_ptr); // Clear 8byte aligned block. addi(base_ptr, base_ptr, 8); bdnz(restloop); bind(done); } }
// Data Cache Block Zero Locked static void dcbz_l(ThreadState *state, Instruction instr) { dcbz(state, instr); }