int
aipc_ISR( u32_t irq , void *data )
{
int n = MAX_HANDLE_CNT;
u32_t fid;
interrupt_mask( irq );
deassert( AIPC_CPU_INT_IP );
while(1) {
if( !aipc_int_cpu_hiq_empty() ){ //handle elements in hi queue
for( ; n>0 ; n-- )
{
if( !aipc_int_cpu_hiq_empty() ){ //For hi queue
//Get element from hi queue
if( OK == aipc_int_cpu_hiq_dequeue( &fid ))
;//aipc_exec_callback( fid , data ); //Run callback
else
break;
}
}
}
if( !aipc_int_cpu_lowq_empty() ){ //handle elements in low queue
for( ; n>0 ; n-- )
{
if( !aipc_int_cpu_lowq_empty() ){ //For low queue
//Get element from low queue
if( OK == aipc_int_cpu_lowq_dequeue( &fid ) )
;//aipc_exec_callback( fid , data ); //Run callback
else
break;
}
}
}
if( read_register( AIPC_CPU_INT_IP ) )
deassert( AIPC_CPU_INT_IP );
else
break;
}
interrupt_unmask( irq );
return IRQ_HANDLED;
}
void
ShiftConnection::setupChannel() const {
pinMode(_cs, OUTPUT);
pinMode(_sclk, OUTPUT);
deassert();
}
void
SpiConnection::setupChannel() const {
SPI.begin();
pinMode(_cs, OUTPUT);
deassert();
}
