static void lpc47n227_pnp_set_resource(device_t dev, struct resource *resource)
{
if (!(resource->flags & IORESOURCE_ASSIGNED)) {
printk(BIOS_ERR, "ERROR: %s %02lx not allocated\n",
dev_path(dev), resource->index);
return;
}
/* Now store the resource */
// NOTE: Cannot use pnp_set_XXX() here because they assume chip
// support for logical devices, which the LPC47N227 doesn't have
if (resource->flags & IORESOURCE_IO) {
lpc47n227_pnp_set_iobase(dev, resource->base);
} else if (resource->flags & IORESOURCE_DRQ) {
lpc47n227_pnp_set_drq(dev, resource->base);
} else if (resource->flags & IORESOURCE_IRQ) {
lpc47n227_pnp_set_irq(dev, resource->base);
} else {
printk(BIOS_ERR, "ERROR: %s %02lx unknown resource type\n",
dev_path(dev), resource->index);
return;
}
resource->flags |= IORESOURCE_STORED;
report_resource_stored(dev, resource, "");
}
void scan_smbus(device_t bus)
{
device_t child;
struct bus *link;
static int smbus_max = 0;
printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(bus));
for (link = bus->link_list; link; link = link->next) {
link->secondary = ++smbus_max;
for (child = link->children; child; child = child->sibling) {
if (child->chip_ops && child->chip_ops->enable_dev)
child->chip_ops->enable_dev(child);
if (child->ops && child->ops->enable)
child->ops->enable(child);
printk(BIOS_DEBUG, "smbus: %s[%d]->", dev_path(child->bus->dev),
child->bus->link_num);
printk(BIOS_DEBUG, "%s %s\n", dev_path(child),
child->enabled ? "enabled" : "disabled");
}
}
printk(BIOS_SPEW, "%s for %s done\n", __func__, dev_path(bus));
}
/**
* Read the resources on all devices of a given bus.
*
* @param bus Bus to read the resources on.
*/
static void read_resources(struct bus *bus)
{
struct device *curdev;
printk(BIOS_SPEW, "%s %s bus %x link: %d\n", dev_path(bus->dev),
__func__, bus->secondary, bus->link_num);
/* Walk through all devices and find which resources they need. */
for (curdev = bus->children; curdev; curdev = curdev->sibling) {
struct bus *link;
if (!curdev->enabled)
continue;
if (!curdev->ops || !curdev->ops->read_resources) {
printk(BIOS_ERR, "%s missing read_resources\n",
dev_path(curdev));
continue;
}
curdev->ops->read_resources(curdev);
/* Read in the resources behind the current device's links. */
for (link = curdev->link_list; link; link = link->next)
read_resources(link);
}
printk(BIOS_SPEW, "%s read_resources bus %d link: %d done\n",
dev_path(bus->dev), bus->secondary, bus->link_num);
}
static void constrain_resources(struct device *dev, struct constraints* limits)
{
struct device *child;
struct resource *res;
struct resource *lim;
struct bus *link;
printk(BIOS_SPEW, "%s: %s\n", __func__, dev_path(dev));
/* Constrain limits based on the fixed resources of this device. */
for (res = dev->resource_list; res; res = res->next) {
if (!(res->flags & IORESOURCE_FIXED))
continue;
if (!res->size) {
/* It makes no sense to have 0-sized, fixed resources.*/
printk(BIOS_ERR, "skipping %s@%lx fixed resource, "
"size=0!\n", dev_path(dev), res->index);
continue;
}
/* PREFETCH, MEM, or I/O - skip any others. */
if ((res->flags & MEM_MASK) == PREF_TYPE)
lim = &limits->pref;
else if ((res->flags & MEM_MASK) == MEM_TYPE)
lim = &limits->mem;
else if ((res->flags & IO_MASK) == IO_TYPE)
lim = &limits->io;
else
continue;
/*
* Is it a fixed resource outside the current known region?
* If so, we don't have to consider it - it will be handled
* correctly and doesn't affect current region's limits.
*/
if (((res->base + res->size -1) < lim->base)
|| (res->base > lim->limit))
continue;
/*
* Choose to be above or below fixed resources. This check is
* signed so that "negative" amounts of space are handled
* correctly.
*/
if ((signed long long)(lim->limit - (res->base + res->size -1))
> (signed long long)(res->base - lim->base))
lim->base = res->base + res->size;
else
lim->limit = res->base -1;
}
/* Descend into every enabled child and look for fixed resources. */
for (link = dev->link_list; link; link = link->next) {
for (child = link->children; child; child = child->sibling) {
if (child->enabled)
constrain_resources(child, limits);
}
}
}
void scan_lpc_bus(device_t bus)
{
printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(bus));
scan_static_bus(bus);
printk(BIOS_SPEW, "%s for %s done\n", __func__, dev_path(bus));
}
static void pcixx12_set_resources(device_t dev)
{
printk(BIOS_DEBUG, "%s In set resources \n",dev_path(dev));
pci_dev_set_resources(dev);
printk(BIOS_DEBUG, "%s done set resources \n",dev_path(dev));
}
static void pci7420_cardbus_set_resources(struct device *dev)
{
printk(BIOS_DEBUG, "%s In set resources\n",dev_path(dev));
pci_dev_set_resources(dev);
printk(BIOS_DEBUG, "%s done set resources\n",dev_path(dev));
}
void get_bus_conf(void)
{
unsigned apicid_base;
struct device *dev;
int i;
struct mb_sysconf_t *m;
sysconf.mb = &mb_sysconf;
m = sysconf.mb;
memset(m, 0, sizeof(struct mb_sysconf_t));
get_default_pci1234(32);
sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff;
m->sbdn2 = sysconf.hcdn[0] & 0xff; // bcm5780
m->bus_bcm5785_0 = (sysconf.pci1234[0] >> 12) & 0xff;
m->bus_bcm5780[0] = m->bus_bcm5785_0;
/* bcm5785 */
printk(BIOS_DEBUG, "search for def %d.0 on bus %d\n",sysconf.sbdn,m->bus_bcm5785_0);
dev = dev_find_slot(m->bus_bcm5785_0, PCI_DEVFN(sysconf.sbdn,0));
if (dev) {
printk(BIOS_DEBUG, "found dev %s...\n",dev_path(dev));
m->bus_bcm5785_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
printk(BIOS_DEBUG, "secondary is %d...\n",m->bus_bcm5785_1);
dev = dev_find_slot(m->bus_bcm5785_1, PCI_DEVFN(0xd,0));
printk(BIOS_DEBUG, "now found %s...\n",dev_path(dev));
if (dev)
m->bus_bcm5785_1_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_bcm5785_0, sysconf.sbdn);
}
/* bcm5780 */
for (i = 1; i < 6; i++) {
dev = dev_find_slot(m->bus_bcm5780[0], PCI_DEVFN(m->sbdn2 + i - 1,0));
if (dev)
m->bus_bcm5780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
else
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_bcm5780[0], m->sbdn2+i-1);
}
/*I/O APICs: APIC ID Version State Address*/
apicid_base = 0x10;
for (i = 0; i < 3; i++)
m->apicid_bcm5785[i] = apicid_base+i;
}
/**
* Scan root bus for generic systems.
*
* This function is the default scan_bus() method of the root device.
*
* @param root The root device structure.
*/
static void root_dev_scan_bus(device_t bus)
{
struct bus *link;
printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(bus));
scan_static_bus(bus);
for (link = bus->link_list; link; link = link->next)
scan_bridges(link);
printk(BIOS_SPEW, "%s for %s done\n", __func__, dev_path(bus));
}
/*
* The only consumer of the return value of get_pbus() is pci_bus_ops().
* pci_bus_ops() can handle being passed NULL and auto-picks working ops.
*/
static struct bus *get_pbus(struct device *dev)
{
struct bus *pbus = NULL;
if (!dev)
die("get_pbus: dev is NULL!\n");
else
pbus = dev->bus;
while (pbus && pbus->dev && !pci_bus_ops(pbus, dev)) {
if (pbus == pbus->dev->bus) {
printk(BIOS_ALERT, "%s in endless loop looking for a "
"parent bus with pci_bus_ops for %s, breaking "
"out.\n", __func__, dev_path(dev));
break;
}
pbus = pbus->dev->bus;
}
if (!pbus || !pbus->dev || !pbus->dev->ops
|| !pbus->dev->ops->ops_pci_bus) {
/* This can happen before the device tree is fully set up. */
// printk(BIOS_EMERG, "%s: Cannot find PCI bus operations.\n",
// dev_path(dev));
pbus = NULL;
}
return pbus;
}
/* Common PCI device function disable. */
void southcluster_enable_dev(device_t dev)
{
uint32_t reg32;
printk(BIOS_SPEW, "%s/%s ( %s )\n",
__FILE__, __func__, dev_name(dev));
if (!dev->enabled) {
int slot = PCI_SLOT(dev->path.pci.devfn);
int func = PCI_FUNC(dev->path.pci.devfn);
printk(BIOS_DEBUG, "%s: Disabling device: %02x.%01x\n",
dev_path(dev), slot, func);
/* Ensure memory, io, and bus master are all disabled */
reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 &= ~(PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
pci_write_config32(dev, PCI_COMMAND, reg32);
/* Place device in D3Hot */
if (place_device_in_d3hot(dev) < 0) {
printk(BIOS_WARNING,
"Could not place %02x.%01x into D3Hot. "
"Keeping device visible.\n", slot, func);
return;
}
/* Disable this device if possible */
sc_disable_devfn(dev);
} else {
/* Enable SERR */
reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_SERR;
pci_write_config32(dev, PCI_COMMAND, reg32);
}
}
/**
* Initialize a specific device.
*
* The parent should be initialized first to avoid having an ordering problem.
* This is done by calling the parent's init() method before its childrens'
* init() methods.
*
* @param dev The device to be initialized.
*/
static void init_dev(struct device *dev)
{
if (!dev->enabled)
return;
if (!dev->initialized && dev->ops && dev->ops->init) {
if (dev->path.type == DEVICE_PATH_I2C) {
printk(BIOS_DEBUG, "smbus: %s[%d]->",
dev_path(dev->bus->dev), dev->bus->link_num);
}
printk(BIOS_DEBUG, "%s init\n", dev_path(dev));
dev->initialized = 1;
dev->ops->init(dev);
}
}
void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
u32 io_min, u32 io_max)
{
u32 i;
u32 tempreg;
/* io range allocation */
tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit
for (i=0; i<sysconf.nodes; i++)
pci_write_config32(__f1_dev[i], reg+4, tempreg);
tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?
#if 0
// FIXME: can we use VGA reg instead?
if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link %s\n",
__func__, dev_path(dev), link);
tempreg |= PCI_IO_BASE_VGA_EN;
}
if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) {
tempreg |= PCI_IO_BASE_NO_ISA;
}
#endif
for (i=0; i<sysconf.nodes; i++)
pci_write_config32(__f1_dev[i], reg, tempreg);
}
static void rl5c476_set_resources(device_t dev)
{
struct resource *resource;
printk(BIOS_DEBUG, "%s In set resources \n",dev_path(dev));
if( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){
resource = find_resource(dev,1);
if( !(resource->flags & IORESOURCE_STORED) ){
resource->flags |= IORESOURCE_STORED ;
printk(BIOS_DEBUG, "%s 1 ==> %llx\n", dev_path(dev), resource->base);
cf_base = resource->base;
}
}
pci_dev_set_resources(dev);
}
struct bus *i2c_link(struct device *const dev)
{
if (!dev || !dev->bus)
return NULL;
struct bus *link = dev->bus;
while (link) {
struct device *const parent = link->dev;
if (parent && parent->ops &&
(parent->ops->ops_i2c_bus || parent->ops->ops_smbus_bus))
break;
if (parent && parent->bus)
link = parent->bus;
else
link = NULL;
}
if (!link) {
printk(BIOS_ALERT, "%s Cannot find I2C or SMBus bus operations",
dev_path(dev));
}
return link;
}
void broadwell_pch_enable_dev(device_t dev)
{
u32 reg32;
/* These devices need special enable/disable handling */
switch (PCI_SLOT(dev->path.pci.devfn)) {
case PCH_DEV_SLOT_PCIE:
case PCH_DEV_SLOT_EHCI:
case PCH_DEV_SLOT_HDA:
return;
}
if (!dev->enabled) {
printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));
/* Ensure memory, io, and bus master are all disabled */
reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 &= ~(PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
pci_write_config32(dev, PCI_COMMAND, reg32);
/* Disable this device if possible */
pch_disable_devfn(dev);
} else {
/* Enable SERR */
reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_SERR;
pci_write_config32(dev, PCI_COMMAND, reg32);
}
}
static void vt1211_pnp_set_resources(struct device *dev)
{
struct resource *res;
#if IS_ENABLED(CONFIG_CONSOLE_SERIAL) && IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)
/* TODO: Do the same for SP2? */
if (dev->path.pnp.device == VT1211_SP1) {
for (res = dev->resource_list; res; res = res->next) {
res->flags |= IORESOURCE_STORED;
report_resource_stored(dev, res, "");
}
return;
}
#endif
pnp_enter_conf_mode(dev);
pnp_set_logical_device(dev);
/* Paranoia says I should disable the device here... */
for (res = dev->resource_list; res; res = res->next) {
if (!(res->flags & IORESOURCE_ASSIGNED)) {
printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010Lx "
"not assigned\n", dev_path(dev), res->index,
resource_type(res), res->size);
continue;
}
/* Now store the resource. */
if (res->flags & IORESOURCE_IO) {
vt1211_set_iobase(dev, res->index, res->base);
} else if (res->flags & IORESOURCE_DRQ) {
pnp_set_drq(dev, res->index, res->base);
} else if (res->flags & IORESOURCE_IRQ) {
pnp_set_irq(dev, res->index, res->base);
} else {
printk(BIOS_ERR, "ERROR: %s %02lx unknown resource "
"type\n", dev_path(dev), res->index);
return;
}
res->flags |= IORESOURCE_STORED;
report_resource_stored(dev, res, "");
}
pnp_exit_conf_mode(dev);
}
void show_devs_subtree(struct device *root, int debug_level, const char *msg)
{
printf("Show all devs in subtree %s...%s\n",
dev_path(root), msg);
printf("%s\n", msg);
show_devs_tree(root, debug_level, 0, -1);
}
static void ich_pci_dev_enable_resources(struct device *dev)
{
uint16_t command;
command = pci_read_config16(dev, PCI_COMMAND);
command |= dev->command;
printk(BIOS_DEBUG, "%s cmd <- %02x\n", dev_path(dev), command);
pci_write_config16(dev, PCI_COMMAND, command);
}
void show_all_devs(int debug_level, const char *msg)
{
struct device *dev;
printf("Show all devs...%s\n", msg);
for (dev = all_devices; dev; dev = dev->next) {
printf("%s: enabled %d%s\n",
dev_path(dev), dev->enabled,
dev->chip_ops ? ":has a chip":"");
}
}
static void enable_dev(struct device *dev)
{
printk(BIOS_SPEW, "In VX800 enable_dev for device %s.\n", dev_path(dev));
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_DOMAIN) {
dev->ops = &pci_domain_ops;
} else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
dev->ops = &cpu_bus_ops;
}
}
/**
* Assign the computed resources to the devices on the bus.
*
* Use the device specific set_resources() method to store the computed
* resources to hardware. For bridge devices, the set_resources() method
* has to recurse into every down stream buses.
*
* Mutual recursion:
* assign_resources() -> device_operation::set_resources()
* device_operation::set_resources() -> assign_resources()
*
* @param bus Pointer to the structure for this bus.
*/
void assign_resources(struct bus *bus)
{
struct device *curdev;
printk(BIOS_SPEW, "%s assign_resources, bus %d link: %d\n",
dev_path(bus->dev), bus->secondary, bus->link_num);
for (curdev = bus->children; curdev; curdev = curdev->sibling) {
if (!curdev->enabled || !curdev->resource_list)
continue;
if (!curdev->ops || !curdev->ops->set_resources) {
printk(BIOS_ERR, "%s missing set_resources\n",
dev_path(curdev));
continue;
}
curdev->ops->set_resources(curdev);
}
printk(BIOS_SPEW, "%s assign_resources, bus %d link: %d\n",
dev_path(bus->dev), bus->secondary, bus->link_num);
}
/**
* Do some S2881-specific HWM initialization for the ADT7463 chip.
*
* Should be factored out so that it can be more general.
*
* See Analog Devices ADT7463 datasheet, Rev C (2004):
* http://www.analog.com/en/prod/0,,766_825_ADT7463,00.html
*/
static void adt7463_init(struct device *adt7463)
{
int result;
printk(BIOS_DEBUG, "ADT7463 is %s\n", dev_path(adt7463));
/* Set all fans to 'Fastest Speed Calculated by All 3 Temperature
* Channels Controls PWMx'.
*/
result = smbus_write_byte(adt7463, 0x5c, 0xc2);
result = smbus_write_byte(adt7463, 0x5d, 0xc2);
result = smbus_write_byte(adt7463, 0x5e, 0xc2);
/* Make sure that our fans never stop when temp. falls below Tmin,
* but rather keep going at minimum duty cycle (applies to automatic
* fan control mode only).
*/
result = smbus_write_byte(adt7463, 0x62, 0xc0);
/* Set minimum PWM duty cycle to 25%, rather than the default 50%. */
result = smbus_write_byte(adt7463, 0x64, 0x40);
result = smbus_write_byte(adt7463, 0x65, 0x40);
result = smbus_write_byte(adt7463, 0x66, 0x40);
/* Set Tmin to 55C, rather than the default 90C. Above this temperature
* the fans will start blowing harder as temperature increases
* (automatic mode only).
*/
result = smbus_write_byte(adt7463, 0x67, 0x37);
result = smbus_write_byte(adt7463, 0x68, 0x37);
result = smbus_write_byte(adt7463, 0x69, 0x37);
/* Set THERM limit to 70C, rather than the default 100C.
* The fans will kick in at 100% if the sensors reach this temperature,
* (only in automatic mode, but supposedly even when hardware is
* locked up). This is a failsafe measure.
*/
result = smbus_write_byte(adt7463, 0x6a, 0x46);
result = smbus_write_byte(adt7463, 0x6b, 0x46);
result = smbus_write_byte(adt7463, 0x6c, 0x46);
/* Remote temperature 1 offset (LSB == 0.25C). */
result = smbus_write_byte(adt7463, 0x70, 0x02);
/* Remote temperature 2 offset (LSB == 0.25C). */
result = smbus_write_byte(adt7463, 0x72, 0x01);
/* Set TACH measurements to normal (1/second). */
result = smbus_write_byte(adt7463, 0x78, 0xf0);
printk(BIOS_DEBUG, "ADT7463 properly initialized\n");
}
static int smbios_walk_device_tree(device_t tree, int *handle, unsigned long *current)
{
device_t dev;
int len = 0;
for(dev = tree; dev; dev = dev->next) {
printk(BIOS_INFO, "%s (%s)\n", dev_path(dev), dev_name(dev));
if (dev->ops && dev->ops->get_smbios_data)
len += dev->ops->get_smbios_data(dev, handle, current);
}
return len;
}
static void usb_i_init(struct device *dev)
{
#if CONFIG_EPIA_VT8237R_INIT
u8 reg8;
printk(BIOS_DEBUG, "Entering %s\n", __func__);
reg8 = pci_read_config8(dev, 0x04);
printk(BIOS_SPEW, "%s Read %02X from PCI Command Reg\n", dev_path(dev), reg8);
reg8 = reg8 | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_write_config8(dev, 0x04, reg8);
printk(BIOS_SPEW, "%s Wrote %02X to PCI Command Reg\n", dev_path(dev), reg8);
/* Set Cache Line Size and Latency Timer */
pci_write_config8(dev, 0x0c, 0x08);
pci_write_config8(dev, 0x0d, 0x20);
/* Enable Sub Device ID Back Door and set Generic */
reg8 = pci_read_config8(dev, 0x42);
reg8 |= 0x10;
pci_write_config8(dev, 0x42, reg8);
pci_write_config16(dev, 0x2e, 0xAA07);
reg8 &= ~0x10;
pci_write_config8(dev, 0x42, reg8);
pci_write_config8(dev, 0x41, 0x12);
pci_write_config8(dev, 0x49, 0x0B);
/* Clear PCI Status */
pci_write_config16(dev, 0x06, 0x7A10);
#endif
return;
}
/**
* Enable resources for children devices.
*
* @param dev The device whos children's resources are to be enabled.
*/
static void sis966_lpc_enable_childrens_resources(device_t dev)
{
struct bus *link;
uint32_t reg, reg_var[4];
int i;
int var_num = 0;
reg = pci_read_config32(dev, 0xa0);
for (link = dev->link_list; link; link = link->next) {
device_t child;
for (child = link->children; child; child = child->sibling) {
if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
struct resource *res;
for(res = child->resource_list; res; res = res->next) {
unsigned long base, end; // don't need long long
if(!(res->flags & IORESOURCE_IO)) continue;
base = res->base;
end = resource_end(res);
printk(BIOS_DEBUG, "sis966 lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end);
switch(base) {
case 0x3f8: // COM1
reg |= (1<<0); break;
case 0x2f8: // COM2
reg |= (1<<1); break;
case 0x378: // Parallal 1
reg |= (1<<24); break;
case 0x3f0: // FD0
reg |= (1<<20); break;
case 0x220: // Aduio 0
reg |= (1<<8); break;
case 0x300: // Midi 0
reg |= (1<<12); break;
}
if( (base == 0x290) || (base >= 0x400)) {
if(var_num>=4) continue; // only 4 var ; compact them ?
reg |= (1<<(28+var_num));
reg_var[var_num++] = (base & 0xffff)|((end & 0xffff)<<16);
}
}
}
}
}
pci_write_config32(dev, 0xa0, reg);
for(i=0;i<var_num;i++) {
pci_write_config32(dev, 0xa8 + i*4, reg_var[i]);
}
}
static void pcie_common_init(struct device *dev)
{
u8 reg;
int i, up;
/* Disable downstream read cycle retry,
* otherwise the bus scan will hang if no device is plugged in. */
reg = pci_read_config8(dev, 0xa3);
pci_write_config8(dev, 0xa3, reg & ~0x01);
/* Use PHY negotiation for lane config */
reg = pci_read_config8(dev, 0xc1);
pci_write_config8(dev, 0xc1, reg & ~0x1f);
/* Award has 0xb, VIA recommends 0xd, default 0x8.
* bit4: receive polarity change control
* bits3:2: squelch window select 64~175mv
* bit1: Number of non-idle bits detected before exiting idle state
* 0: 10 bits, 1: 2 bits
* bit0: Number of idle bits detected before entering idle state
* 0: 10 bits, 1: 2 bits
*/
pci_write_config8(dev, 0xe1, 0xb);
/* Set replay timer limit. */
pci_write_config8(dev, 0xb1, 0xf0);
/* Enable link. */
reg = pci_read_config8(dev, 0x50);
pci_write_config8(dev, 0x50, reg & ~0x10);
/* Wait up to 100ms for link to come up */
up = 0;
for (i=0; i<1000; i++) {
if (pci_read_config16(dev, 0x52) & (1<<13)) {
up = 1;
break;
}
udelay(100);
}
printk(BIOS_SPEW, "%s PCIe link ", dev_path(dev));
if (up)
printk(BIOS_SPEW, "up after %d us\n", i*100);
else
printk(BIOS_SPEW, "timeout\n");
dump_south(dev);
}
static u32 find_verb(u32 viddid, u32 ** verb)
{
device_t azalia_dev = dev_find_slot(0, PCI_DEVFN(0x14, 2));
struct southbridge_amd_sb600_config *cfg =
(struct southbridge_amd_sb600_config *)azalia_dev->chip_info;
if (!cfg)
return 0;
printk(BIOS_DEBUG, "Dev=%s\n", dev_path(azalia_dev));
printk(BIOS_DEBUG, "Default viddid=%x\n", cfg->hda_viddid);
printk(BIOS_DEBUG, "Reading viddid=%x\n", viddid);
if (viddid != cfg->hda_viddid)
return 0;
*verb = (u32 *) cim_verb_data;
return sizeof(cim_verb_data) / sizeof(u32);
}
static void ich_pci_bus_enable_resources(struct device *dev)
{
uint16_t ctrl;
/* enable IO in command register if there is VGA card
* connected with (even it does not claim IO resource)
*/
if (dev->link_list->bridge_ctrl & PCI_BRIDGE_CTL_VGA)
dev->command |= PCI_COMMAND_IO;
ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
ctrl |= dev->link_list->bridge_ctrl;
ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* error check */
printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
/* This is the reason we need our own pci_bus_enable_resources */
ich_pci_dev_enable_resources(dev);
}
static void init_this_cpu(void *arg)
{
struct cpu_info *ci = arg;
device_t dev = ci->cpu;
cpu_set_device_operations(dev);
printk(BIOS_DEBUG, "CPU%x: MPIDR: %llx\n", ci->id, ci->mpidr);
/* Initialize the GIC. */
gic_init();
if (dev->ops != NULL && dev->ops->init != NULL) {
dev->initialized = 1;
printk(BIOS_DEBUG, "%s init\n", dev_path(dev));
dev->ops->init(dev);
}
}
