static int clps711x_gpio_probe(struct device_d *dev)
{
struct resource *iores;
int err, id = dev->id;
void __iomem *dat, *dir = NULL, *dir_inv = NULL;
struct bgpio_chip *bgc;
if (dev->device_node)
id = of_alias_get_id(dev->device_node, "gpio");
if (id < 0 || id > 4)
return -ENODEV;
iores = dev_request_mem_resource(dev, 0);
if (IS_ERR(iores))
return PTR_ERR(iores);
dat = IOMEM(iores->start);
switch (id) {
case 3:
iores = dev_request_mem_resource(dev, 1);
if (IS_ERR(iores))
return PTR_ERR(iores);
dir_inv = IOMEM(iores->start);
break;
default:
iores = dev_request_mem_resource(dev, 1);
if (IS_ERR(iores))
return PTR_ERR(iores);
dir = IOMEM(iores->start);
break;
}
bgc = xzalloc(sizeof(struct bgpio_chip));
err = bgpio_init(bgc, dev, 1, dat, NULL, NULL, dir, dir_inv, 0);
if (err)
goto out_err;
bgc->gc.base = id * 8;
switch (id) {
case 4:
bgc->gc.ngpio = 3;
break;
default:
break;
}
err = gpiochip_add(&bgc->gc);
out_err:
if (err)
free(bgc);
return err;
}
static int s3c_serial_probe(struct device_d *dev)
{
struct resource *iores;
struct s3c_uart *priv;
struct console_device *cdev;
priv = xzalloc(sizeof(struct s3c_uart));
cdev = &priv->cdev;
iores = dev_request_mem_resource(dev, 0);
if (IS_ERR(iores))
return PTR_ERR(iores);
priv->regs = IOMEM(iores->start);
dev->priv = priv;
cdev->dev = dev;
cdev->tstc = s3c_serial_tstc;
cdev->putc = s3c_serial_putc;
cdev->getc = s3c_serial_getc;
cdev->flush = s3c_serial_flush;
cdev->setbrg = s3c_serial_setbaudrate;
s3c_serial_init_port(cdev);
/* Enable UART */
console_register(cdev);
return 0;
}
static int imx_ocotp_probe(struct device_d *dev)
{
struct resource *iores;
void __iomem *base;
struct ocotp_priv *priv;
int ret = 0;
struct imx_ocotp_data *data;
ret = dev_get_drvdata(dev, (const void **)&data);
if (ret)
return ret;
iores = dev_request_mem_resource(dev, 0);
if (IS_ERR(iores))
return PTR_ERR(iores);
base = IOMEM(iores->start);
imx_ocotp_init_dt(dev, base);
priv = xzalloc(sizeof(*priv));
priv->base = base;
priv->clk = clk_get(dev, NULL);
if (IS_ERR(priv->clk))
return PTR_ERR(priv->clk);
strcpy(priv->dev.name, "ocotp");
priv->dev.parent = dev;
register_device(&priv->dev);
priv->map_config.reg_bits = 32;
priv->map_config.val_bits = 32;
priv->map_config.reg_stride = 4;
priv->map_config.max_register = data->num_regs - 1;
priv->map = regmap_init(dev, &imx_ocotp_regmap_bus, priv, &priv->map_config);
if (IS_ERR(priv->map))
return PTR_ERR(priv->map);
ret = regmap_register_cdev(priv->map, "imx-ocotp");
if (ret)
return ret;
if (IS_ENABLED(CONFIG_IMX_OCOTP_WRITE)) {
dev_add_param_bool(&(priv->dev), "permanent_write_enable",
NULL, NULL, &priv->permanent_write_enable, NULL);
}
if (IS_ENABLED(CONFIG_NET))
dev_add_param_mac(&(priv->dev), "mac_addr", imx_ocotp_set_mac,
imx_ocotp_get_mac, priv->ethaddr, priv);
dev_add_param_bool(&(priv->dev), "sense_enable", NULL, NULL, &priv->sense_enable, priv);
return 0;
}
static int davinci_gpio_probe(struct device_d *dev)
{
struct resource *iores;
void __iomem *gpio_base;
int ret;
u32 val;
int i, base;
unsigned ngpio;
struct davinci_gpio_controller *chips;
ret = of_property_read_u32(dev->device_node, "ti,ngpio", &val);
if (ret) {
dev_err(dev, "could not read 'ti,ngpio' property\n");
return -EINVAL;
}
ngpio = val;
if (WARN_ON(ARCH_NR_GPIOS < ngpio))
ngpio = ARCH_NR_GPIOS;
chips = xzalloc((ngpio / 32 + 1) * sizeof(*chips));
iores = dev_request_mem_resource(dev, 0);
if (IS_ERR(iores)) {
dev_err(dev, "could not get memory region\n");
return PTR_ERR(iores);
}
gpio_base = IOMEM(iores->start);
for (i = 0, base = 0; base < ngpio; i++, base += 32) {
struct davinci_gpio_regs __iomem *regs;
struct gpio_chip *gc;
gc = &chips[i].chip;
gc->ops = &davinci_gpio_ops;
gc->dev = dev;
gc->base = base;
gc->ngpio = ngpio - base;
if (gc->ngpio > 32)
gc->ngpio = 32;
regs = gpio2regs(gpio_base, base);
chips[i].regs = regs;
chips[i].set_data = ®s->set_data;
chips[i].clr_data = ®s->clr_data;
chips[i].in_data = ®s->in_data;
gpiochip_add(gc);
}
return 0;
}
static int imx1_ccm_probe(struct device_d *dev)
{
struct resource *iores;
void __iomem *regs;
iores = dev_request_mem_resource(dev, 0);
if (IS_ERR(iores))
return PTR_ERR(iores);
regs = IOMEM(iores->start);
mx1_clocks_init(regs, 32000);
return 0;
}
static int zynq_clock_probe(struct device_d *dev)
{
struct resource *iores;
void __iomem *slcr_base;
unsigned long ps_clk_rate = 33333330;
iores = dev_request_mem_resource(dev, 0);
if (IS_ERR(iores))
return PTR_ERR(iores);
slcr_base = IOMEM(iores->start);
clks[ps_clk] = clk_fixed("ps_clk", ps_clk_rate);
clks[arm_pll] = zynq_pll_clk(ZYNQ_PLL_ARM, "arm_pll", slcr_base + 0x100);
clks[ddr_pll] = zynq_pll_clk(ZYNQ_PLL_DDR, "ddr_pll", slcr_base + 0x104);
clks[io_pll] = zynq_pll_clk(ZYNQ_PLL_IO, "io_pll", slcr_base + 0x108);
clks[uart_clk] = zynq_periph_clk("uart_clk", slcr_base + 0x154);
clks[uart0] = clk_gate("uart0", "uart_clk", slcr_base + 0x154, 0, 0, 0);
clks[uart1] = clk_gate("uart1", "uart_clk", slcr_base + 0x154, 1, 0, 0);
clks[gem0] = clk_gate("gem0", "io_pll", slcr_base + 0x140, 0, 0, 0);
clks[gem1] = clk_gate("gem1", "io_pll", slcr_base + 0x144, 1, 0, 0);
clks[cpu_clk] = zynq_cpu_clk("cpu_clk", slcr_base + 0x120);
clks[cpu_6x4x] = zynq_cpu_subclk("cpu_6x4x", CPU_SUBCLK_6X4X,
slcr_base + 0x120, slcr_base + 0x1C4);
clks[cpu_3x2x] = zynq_cpu_subclk("cpu_3x2x", CPU_SUBCLK_3X2X,
slcr_base + 0x120, slcr_base + 0x1C4);
clks[cpu_2x] = zynq_cpu_subclk("cpu_2x", CPU_SUBCLK_2X,
slcr_base + 0x120, slcr_base + 0x1C4);
clks[cpu_1x] = zynq_cpu_subclk("cpu_1x", CPU_SUBCLK_1X,
slcr_base + 0x120, slcr_base + 0x1C4);
clk_register_clkdev(clks[cpu_3x2x], NULL, "arm_smp_twd");
clk_register_clkdev(clks[uart0], NULL, "zynq_serial0");
clk_register_clkdev(clks[uart1], NULL, "zynq_serial1");
clk_register_clkdev(clks[gem0], NULL, "macb0");
clk_register_clkdev(clks[gem1], NULL, "macb1");
clkdev_add_physbase(clks[cpu_3x2x], CORTEXA9_SCU_TIMER_BASE_ADDR, NULL);
clkdev_add_physbase(clks[uart1], ZYNQ_UART1_BASE_ADDR, NULL);
return 0;
}
static int digic_gpio_probe(struct device_d *dev)
{
struct resource *iores;
struct digic_gpio_chip *chip;
struct resource *res;
resource_size_t rsize;
int ret = -EINVAL;
chip = xzalloc(sizeof(*chip));
res = dev_get_resource(dev, IORESOURCE_MEM, 0);
if (!res)
goto err;
rsize = resource_size(res);
chip->gc.ngpio = rsize / sizeof(int32_t);
iores = dev_request_mem_resource(dev, 0);
if (IS_ERR(iores))
return PTR_ERR(iores);
chip->base = IOMEM(iores->start);
chip->gc.ops = &digic_gpio_ops;
chip->gc.base = 0;
chip->gc.dev = dev;
ret = gpiochip_add(&chip->gc);
if (ret) {
dev_err(dev, "couldn't add gpiochip, ret = %d\n", ret);
goto err;
}
dev_info(dev, "probed gpiochip%d with base %d\n",
dev->id, chip->gc.base);
return 0;
err:
kfree(chip);
return ret;
}
static int netx_serial_probe(struct device_d *dev)
{
struct resource *iores;
struct console_device *cdev;
cdev = xzalloc(sizeof(struct console_device));
iores = dev_request_mem_resource(dev, 0);
if (IS_ERR(iores))
return PTR_ERR(iores);
dev->priv = IOMEM(iores->start);
cdev->dev = dev;
cdev->tstc = netx_serial_tstc;
cdev->putc = netx_serial_putc;
cdev->getc = netx_serial_getc;
cdev->setbrg = netx_serial_setbaudrate;
netx_serial_init_port(cdev);
console_register(cdev);
return 0;
}
static int am335x_phy_probe(struct device_d *dev)
{
struct resource *iores;
int ret;
am_usbphy = xzalloc(sizeof(*am_usbphy));
if (!am_usbphy)
return -ENOMEM;
iores = dev_request_mem_resource(dev, 0);
if (IS_ERR(iores)) {
ret = PTR_ERR(iores);
goto err_free;
}
am_usbphy->base = IOMEM(iores->start);
am_usbphy->phy_ctrl = am335x_get_phy_control(dev);
if (!am_usbphy->phy_ctrl)
return -ENODEV;
am_usbphy->id = of_alias_get_id(dev->device_node, "phy");
if (am_usbphy->id < 0) {
dev_err(dev, "Missing PHY id: %d\n", am_usbphy->id);
return am_usbphy->id;
}
am_usbphy->phy.init = am335x_init;
dev->priv = am_usbphy;
dev_info(dev, "am_usbphy %p enabled\n", &am_usbphy->phy);
return 0;
err_free:
free(am_usbphy);
return ret;
};
static int armada_xp_pinctrl_probe(struct device_d *dev)
{
struct resource *iores;
const struct of_device_id *match =
of_match_node(armada_xp_pinctrl_of_match, dev->device_node);
struct mvebu_pinctrl_soc_info *soc = &armada_xp_pinctrl_info;
iores = dev_request_mem_resource(dev, 0);
if (IS_ERR(iores))
return PTR_ERR(iores);
mpp_base = IOMEM(iores->start);
soc->variant = (enum armada_xp_variant)match->data;
/*
* We don't necessarily want the full list of the armada_xp_mpp_modes,
* but only the first 'n' ones that are available on this SoC
*/
if (soc->variant == V_MV78230)
soc->nmodes = 49;
return mvebu_pinctrl_probe(dev, soc);
}
static int dw_mmc_probe(struct device_d *dev)
{
struct resource *iores;
struct dwmci_host *host;
struct dw_mmc_platform_data *pdata = dev->platform_data;
host = xzalloc(sizeof(*host));
host->clk_biu = clk_get(dev, "biu");
if (IS_ERR(host->clk_biu))
return PTR_ERR(host->clk_biu);
host->clk_ciu = clk_get(dev, "ciu");
if (IS_ERR(host->clk_ciu))
return PTR_ERR(host->clk_ciu);
clk_enable(host->clk_biu);
clk_enable(host->clk_ciu);
host->dev = dev;
iores = dev_request_mem_resource(dev, 0);
if (IS_ERR(iores))
return PTR_ERR(iores);
host->ioaddr = IOMEM(iores->start);
host->idmac = dma_alloc_coherent(sizeof(*host->idmac) * DW_MMC_NUM_IDMACS,
DMA_ADDRESS_BROKEN);
host->mci.send_cmd = dwmci_cmd;
host->mci.set_ios = dwmci_set_ios;
host->mci.init = dwmci_init;
host->mci.card_present = dwmci_card_present;
host->mci.hw_dev = dev;
host->mci.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
host->mci.host_caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA;
host->mci.host_caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED_52MHZ |
MMC_CAP_SD_HIGHSPEED;
if (pdata) {
host->ciu_div = pdata->ciu_div;
host->mci.host_caps &= ~MMC_CAP_BIT_DATA_MASK;
host->mci.host_caps |= pdata->bus_width_caps;
} else if (dev->device_node) {
const char *alias = of_alias_get(dev->device_node);
if (alias)
host->mci.devname = xstrdup(alias);
of_property_read_u32(dev->device_node, "dw-mshc-ciu-div",
&host->ciu_div);
}
/* divider is 0 based in pdata and 1 based in our private struct */
host->ciu_div++;
if (of_device_is_compatible(dev->device_node,
"rockchip,rk2928-dw-mshc"))
host->pwren_value = 0;
else
host->pwren_value = 1;
dev->detect = dw_mmc_detect;
host->clkrate = clk_get_rate(host->clk_ciu);
host->mci.f_min = host->clkrate / 510 / host->ciu_div;
if (host->mci.f_min < 200000)
host->mci.f_min = 200000;
host->mci.f_max = host->clkrate / host->ciu_div;
mci_of_parse(&host->mci);
dev->priv = host;
return mci_register(&host->mci);
}
static int imx25_ccm_probe(struct device_d *dev)
{
struct resource *iores;
void __iomem *base;
iores = dev_request_mem_resource(dev, 0);
if (IS_ERR(iores))
return PTR_ERR(iores);
base = IOMEM(iores->start);
writel((1 << 3) | (1 << 4) | (1 << 5) | (1 << 6) | (1 << 8) | (1 << 9) |
(1 << 10) | (1 << 15) | (1 << 19) | (1 << 21) | (1 << 22) |
(1 << 23) | (1 << 24) | (1 << 28),
base + CCM_CGCR0);
writel((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 13) | (1 << 14) |
(1 << 15) | (1 << 19) | (1 << 20) | (1 << 21) | (1 << 22) |
(1 << 26) | (1 << 31),
base + CCM_CGCR1);
writel((1 << 0) | (1 << 1) | (1 << 2) | (1 << 10) | (1 << 13) | (1 << 14) |
(1 << 15) | (1 << 16) | (1 << 17) | (1 << 18),
base + CCM_CGCR2);
clks[dummy] = clk_fixed("dummy", 0);
clks[osc] = clk_fixed("osc", 24000000);
clks[mpll] = imx_clk_pllv1("mpll", "osc", base + CCM_MPCTL);
clks[upll] = imx_clk_pllv1("upll", "osc", base + CCM_UPCTL);
clks[mpll_cpu_3_4] = imx_clk_fixed_factor("mpll_cpu_3_4", "mpll", 3, 4);
clks[cpu_sel] = imx_clk_mux("cpu_sel", base + CCM_CCTL, 14, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks));
clks[cpu] = imx_clk_divider("cpu", "cpu_sel", base + CCM_CCTL, 30, 2);
clks[ahb] = imx_clk_divider("ahb", "cpu", base + CCM_CCTL, 28, 2);
clks[usb_div] = imx_clk_divider("usb_div", "upll", base + CCM_CCTL, 16, 6);
clks[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2);
clks[per0_sel] = imx_clk_mux("per0_sel", base + CCM_MCR, 0, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
clks[per1_sel] = imx_clk_mux("per1_sel", base + CCM_MCR, 1, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
clks[per2_sel] = imx_clk_mux("per2_sel", base + CCM_MCR, 2, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
clks[per3_sel] = imx_clk_mux("per3_sel", base + CCM_MCR, 3, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
clks[per4_sel] = imx_clk_mux("per4_sel", base + CCM_MCR, 4, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
clks[per5_sel] = imx_clk_mux("per5_sel", base + CCM_MCR, 5, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
clks[per6_sel] = imx_clk_mux("per6_sel", base + CCM_MCR, 6, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
clks[per7_sel] = imx_clk_mux("per7_sel", base + CCM_MCR, 7, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
clks[per8_sel] = imx_clk_mux("per8_sel", base + CCM_MCR, 8, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
clks[per9_sel] = imx_clk_mux("per9_sel", base + CCM_MCR, 9, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
clks[per10_sel] = imx_clk_mux("per10_sel", base + CCM_MCR, 10, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
clks[per11_sel] = imx_clk_mux("per11_sel", base + CCM_MCR, 11, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
clks[per12_sel] = imx_clk_mux("per12_sel", base + CCM_MCR, 12, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
clks[per13_sel] = imx_clk_mux("per13_sel", base + CCM_MCR, 13, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
clks[per14_sel] = imx_clk_mux("per14_sel", base + CCM_MCR, 14, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
clks[per15_sel] = imx_clk_mux("per15_sel", base + CCM_MCR, 15, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
clks[per0] = imx_clk_divider("per0", "per0_sel", base + CCM_PCDR0, 0, 6);
clks[per1] = imx_clk_divider("per1", "per1_sel", base + CCM_PCDR0, 8, 6);
clks[per2] = imx_clk_divider("per2", "per2_sel", base + CCM_PCDR0, 16, 6);
clks[per3] = imx_clk_divider("per3", "per3_sel", base + CCM_PCDR0, 24, 6);
clks[per4] = imx_clk_divider("per4", "per4_sel", base + CCM_PCDR1, 0, 6);
clks[per5] = imx_clk_divider("per5", "per5_sel", base + CCM_PCDR1, 8, 6);
clks[per6] = imx_clk_divider("per6", "per6_sel", base + CCM_PCDR1, 16, 6);
clks[per7] = imx_clk_divider("per7", "per7_sel", base + CCM_PCDR1, 24, 6);
clks[per8] = imx_clk_divider("per8", "per8_sel", base + CCM_PCDR2, 0, 6);
clks[per9] = imx_clk_divider("per9", "per9_sel", base + CCM_PCDR2, 8, 6);
clks[per10] = imx_clk_divider("per10", "per10_sel", base + CCM_PCDR2, 16, 6);
clks[per11] = imx_clk_divider("per11", "per11_sel", base + CCM_PCDR2, 24, 6);
clks[per12] = imx_clk_divider("per12", "per12_sel", base + CCM_PCDR3, 0, 6);
clks[per13] = imx_clk_divider("per13", "per13_sel", base + CCM_PCDR3, 8, 6);
clks[per14] = imx_clk_divider("per14", "per14_sel", base + CCM_PCDR3, 16, 6);
clks[per15] = imx_clk_divider("per15", "per15_sel", base + CCM_PCDR3, 24, 6);
clks[lcdc_ahb] = imx_clk_gate("lcdc_ahb", "ahb", base + CCM_CGCR0, 24);
clks[lcdc_ipg] = imx_clk_gate("lcdc_ipg", "ipg", base + CCM_CGCR1, 29);
clks[lcdc_ipg_per] = imx_clk_gate("lcdc_ipg_per", "per7", base + CCM_CGCR0, 7);
clkdev_add_physbase(clks[per15], MX25_UART1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per15], MX25_UART2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per15], MX25_UART3_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per15], MX25_UART4_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per15], MX25_UART5_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per5], MX25_GPT1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per5], MX25_GPT2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per5], MX25_GPT3_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per5], MX25_GPT4_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ipg], MX25_FEC_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ipg], MX25_I2C1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ipg], MX25_I2C2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ipg], MX25_I2C3_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ipg], MX25_CSPI1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ipg], MX25_CSPI2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ipg], MX25_CSPI3_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per3], MX25_ESDHC1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per4], MX25_ESDHC2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per8], MX25_NFC_BASE_ADDR, NULL);
clkdev_add_physbase(clks[lcdc_ipg_per], MX25_LCDC_BASE_ADDR, "per");
clkdev_add_physbase(clks[lcdc_ipg], MX25_LCDC_BASE_ADDR, "ipg");
clkdev_add_physbase(clks[lcdc_ahb], MX25_LCDC_BASE_ADDR, "ahb");
return 0;
}
static int davinci_emac_probe(struct device_d *dev)
{
struct resource *iores;
struct davinci_emac_platform_data *pdata;
struct davinci_emac_priv *priv;
uint64_t start;
uint32_t phy_mask;
dev_dbg(dev, "+ emac_probe\n");
if (!dev->platform_data) {
dev_err(dev, "no platform_data\n");
return -ENODEV;
}
pdata = dev->platform_data;
priv = xzalloc(sizeof(*priv));
dev->priv = priv;
priv->dev = dev;
iores = dev_request_mem_resource(dev, 0);
if (IS_ERR(iores))
return PTR_ERR(iores);
priv->adap_emac = IOMEM(iores->start);
iores = dev_request_mem_resource(dev, 1);
if (IS_ERR(iores))
return PTR_ERR(iores);
priv->adap_ewrap = IOMEM(iores->start);
iores = dev_request_mem_resource(dev, 2);
if (IS_ERR(iores))
return PTR_ERR(iores);
priv->adap_mdio = IOMEM(iores->start);
iores = dev_request_mem_resource(dev, 3);
if (IS_ERR(iores))
return PTR_ERR(iores);
priv->emac_desc_base = IOMEM(iores->start);
/* EMAC descriptors */
priv->emac_rx_desc = priv->emac_desc_base + EMAC_RX_DESC_BASE;
priv->emac_tx_desc = priv->emac_desc_base + EMAC_TX_DESC_BASE;
priv->emac_rx_active_head = NULL;
priv->emac_rx_active_tail = NULL;
priv->emac_rx_queue_active = 0;
/* Receive packet buffers */
priv->emac_rx_buffers = xmemalign(4096, EMAC_MAX_RX_BUFFERS * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN));
priv->edev.priv = priv;
priv->edev.init = davinci_emac_init;
priv->edev.open = davinci_emac_open;
priv->edev.halt = davinci_emac_halt;
priv->edev.send = davinci_emac_send;
priv->edev.recv = davinci_emac_recv;
priv->edev.get_ethaddr = davinci_emac_get_ethaddr;
priv->edev.set_ethaddr = davinci_emac_set_ethaddr;
priv->edev.parent = dev;
davinci_eth_mdio_enable(priv);
start = get_time_ns();
while (1) {
phy_mask = readl(priv->adap_mdio + EMAC_MDIO_ALIVE);
if (phy_mask) {
dev_info(dev, "detected phy mask 0x%x\n", phy_mask);
phy_mask = ~phy_mask;
break;
}
if (is_timeout(start, 256 * MSECOND)) {
dev_err(dev, "no live phy, scanning all\n");
phy_mask = 0;
break;
}
}
if (pdata->interface_rmii)
priv->interface = PHY_INTERFACE_MODE_RMII;
else
priv->interface = PHY_INTERFACE_MODE_MII;
priv->phy_addr = pdata->phy_addr;
priv->phy_flags = pdata->force_link ? PHYLIB_FORCE_LINK : 0;
priv->miibus.read = davinci_miibus_read;
priv->miibus.write = davinci_miibus_write;
priv->miibus.priv = priv;
priv->miibus.parent = dev;
priv->miibus.phy_mask = phy_mask;
mdiobus_register(&priv->miibus);
eth_register(&priv->edev);
dev_dbg(dev, "- emac_probe\n");
return 0;
}
static int pinctrl_tegra_xusb_probe(struct device_d *dev)
{
struct resource *iores;
struct tegra_xusb_padctl *padctl;
struct phy *phy;
int err;
padctl = xzalloc(sizeof(*padctl));
dev->priv = padctl;
padctl->dev = dev;
dev_get_drvdata(dev, (const void **)&padctl->soc);
iores = dev_request_mem_resource(dev, 0);
if (IS_ERR(iores)) {
dev_err(dev, "Could not get iomem region\n");
return PTR_ERR(iores);
}
padctl->regs = IOMEM(iores->start);
padctl->rst = reset_control_get(dev, NULL);
if (IS_ERR(padctl->rst))
return PTR_ERR(padctl->rst);
err = reset_control_deassert(padctl->rst);
if (err < 0)
return err;
padctl->pinctrl.dev = dev;
padctl->pinctrl.ops = &pinctrl_tegra_xusb_ops;
err = pinctrl_register(&padctl->pinctrl);
if (err) {
dev_err(dev, "failed to register pincontrol\n");
err = -ENODEV;
goto reset;
}
phy = phy_create(dev, NULL, &pcie_phy_ops, NULL);
if (IS_ERR(phy)) {
err = PTR_ERR(phy);
goto unregister;
}
padctl->phys[TEGRA_XUSB_PADCTL_PCIE] = phy;
phy_set_drvdata(phy, padctl);
phy = phy_create(dev, NULL, &sata_phy_ops, NULL);
if (IS_ERR(phy)) {
err = PTR_ERR(phy);
goto unregister;
}
padctl->phys[TEGRA_XUSB_PADCTL_SATA] = phy;
phy_set_drvdata(phy, padctl);
padctl->provider = of_phy_provider_register(dev, tegra_xusb_padctl_xlate);
if (IS_ERR(padctl->provider)) {
err = PTR_ERR(padctl->provider);
dev_err(dev, "failed to register PHYs: %d\n", err);
goto unregister;
}
return 0;
unregister:
pinctrl_unregister(&padctl->pinctrl);
reset:
reset_control_assert(padctl->rst);
return err;
}
static int mv_sata_probe(struct device_d *dev)
{
struct resource *iores;
void __iomem *base;
struct ide_port *ide;
u32 scontrol;
int ret, i;
iores = dev_request_mem_resource(dev, 0);
if (IS_ERR(iores)) {
dev_err(dev, "Failed to request mem resources\n");
return PTR_ERR(iores);
}
base = IOMEM(iores->start);
/* disable MBus windows */
for (i = 0; i < 4; ++i) {
writel(0, base + REG_WINDOW_CONTROL(i));
writel(0, base + REG_WINDOW_BASE(i));
}
/* enable first window */
writel(0x7fff0e01, base + REG_WINDOW_CONTROL(0));
writel(0, base + REG_WINDOW_BASE(0));
writel(REG_EDMA_COMMAND__EATARST, base + REG_EDMA_COMMAND(0));
udelay(25);
writel(0x0, base + REG_EDMA_COMMAND(0));
scontrol = readl(base + REG_SCONTROL(0));
scontrol &= ~(REG_SCONTROL__DET | REG_SCONTROL__IPM);
/* disable power management */
scontrol |= REG_SCONTROL__IPM__PARTIAL | REG_SCONTROL__IPM__SLUMBER;
/* perform interface communication initialization */
writel(scontrol | REG_SCONTROL__DET__INIT, base + REG_SCONTROL(0));
writel(scontrol, base + REG_SCONTROL(0));
ret = wait_on_timeout(10 * MSECOND,
(readl(base + REG_SSTATUS(0)) & REG_SCONTROL__DET) == (REG_SCONTROL__DET__INIT | REG_SCONTROL__DET__PHYOK));
if (ret) {
dev_err(dev, "Failed to wait for phy (sstatus=0x%08x)\n",
readl(base + REG_SSTATUS(0)));
return ret;
}
ide = xzalloc(sizeof(*ide));
ide->port.dev = dev;
ata_ioports_init(&ide->io, base + REG_ATA_BASE, base + REG_ATA_BASE,
NULL, 4);
dev->priv = ide;
ret = ide_port_register(ide);
if (ret)
free(ide);
return ret;
}
static int imx6_ccm_probe(struct device_d *dev)
{
struct resource *iores;
void __iomem *base, *anatop_base, *ccm_base;
anatop_base = (void *)MX6_ANATOP_BASE_ADDR;
iores = dev_request_mem_resource(dev, 0);
if (IS_ERR(iores))
return PTR_ERR(iores);
ccm_base = IOMEM(iores->start);
base = anatop_base;
/* type name parent_name base div_mask */
clks[IMX6QDL_CLK_PLL1_SYS] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f);
clks[IMX6QDL_CLK_PLL2_BUS] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1);
clks[IMX6QDL_CLK_PLL3_USB_OTG] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3);
clks[IMX6QDL_CLK_PLL4_AUDIO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f);
clks[IMX6QDL_CLK_PLL5_VIDEO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f);
clks[IMX6QDL_CLK_PLL8_MLB] = imx_clk_pllv3(IMX_PLLV3_MLB, "pll8_mlb", "osc", base + 0xd0, 0x0);
clks[IMX6QDL_CLK_PLL7_USB_HOST] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x3);
clks[IMX6QDL_CLK_PLL6_ENET] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3);
clks[IMX6QDL_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 6);
clks[IMX6QDL_CLK_USBPHY2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 6);
clks[IMX6QDL_CLK_SATA_REF] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5);
clks[IMX6QDL_CLK_PCIE_REF] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4);
clks[IMX6QDL_CLK_SATA_REF_100M] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20);
clks[IMX6QDL_CLK_PCIE_REF_125M] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
clks[IMX6QDL_CLK_ENET_REF] = imx_clk_divider_table("enet_ref", "pll6_enet", base + 0xe0, 0, 2, clk_enet_ref_table);
clks[IMX6QDL_CLK_LVDS1_SEL] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
clks[IMX6QDL_CLK_LVDS2_SEL] = imx_clk_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
clks[IMX6QDL_CLK_LVDS1_GATE] = imx_clk_gate_exclusive("lvds1_gate", "lvds1_sel", base + 0x160, 10, BIT(12));
clks[IMX6QDL_CLK_LVDS2_GATE] = imx_clk_gate_exclusive("lvds2_gate", "lvds2_sel", base + 0x160, 11, BIT(13));
/* name parent_name reg idx */
clks[IMX6QDL_CLK_PLL2_PFD0_352M] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
clks[IMX6QDL_CLK_PLL2_PFD1_594M] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1);
clks[IMX6QDL_CLK_PLL2_PFD2_396M] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2);
clks[IMX6QDL_CLK_PLL3_PFD0_720M] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0);
clks[IMX6QDL_CLK_PLL3_PFD1_540M] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1);
clks[IMX6QDL_CLK_PLL3_PFD2_508M] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2);
clks[IMX6QDL_CLK_PLL3_PFD3_454M] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3);
/* name parent_name mult div */
clks[IMX6QDL_CLK_PLL2_198M] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2);
clks[IMX6QDL_CLK_PLL3_120M] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4);
clks[IMX6QDL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);
clks[IMX6QDL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
clks[IMX6QDL_CLK_TWD] = imx_clk_fixed_factor("twd", "arm", 1, 2);
base = ccm_base;
/* name reg shift width parent_names num_parents */
clks[IMX6QDL_CLK_STEP] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels));
clks[IMX6QDL_CLK_PLL1_SW] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels));
clks[IMX6QDL_CLK_PERIPH_PRE] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
clks[IMX6QDL_CLK_PERIPH2_PRE] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
clks[IMX6QDL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 1, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
clks[IMX6QDL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
clks[IMX6QDL_CLK_AXI_SEL] = imx_clk_mux("axi_sel", base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels));
clks[IMX6QDL_CLK_USDHC1_SEL] = imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
clks[IMX6QDL_CLK_USDHC2_SEL] = imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
clks[IMX6QDL_CLK_USDHC3_SEL] = imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
clks[IMX6QDL_CLK_USDHC4_SEL] = imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
clks[IMX6QDL_CLK_ENFC_SEL] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels));
clks[IMX6QDL_CLK_EIM_SEL] = imx_clk_mux("eim_sel", base + 0x1c, 27, 2, eim_sels, ARRAY_SIZE(eim_sels));
clks[IMX6QDL_CLK_EIM_SLOW_SEL] = imx_clk_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_sels, ARRAY_SIZE(eim_sels));
clks[IMX6QDL_CLK_VDO_AXI_SEL] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels));
clks[IMX6QDL_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels));
clks[IMX6QDL_CLK_CKO2_SEL] = imx_clk_mux("cko2_sel", base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels));
clks[IMX6QDL_CLK_CKO] = imx_clk_mux("cko", base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels));
clks[IMX6QDL_CLK_PCIE_AXI_SEL] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels));
/* name reg shift width busy: reg, shift parent_names num_parents */
clks[IMX6QDL_CLK_PERIPH] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels));
clks[IMX6QDL_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels));
/* name parent_name reg shift width */
clks[IMX6QDL_CLK_PERIPH_CLK2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3);
clks[IMX6QDL_CLK_PERIPH2_CLK2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3);
clks[IMX6QDL_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2);
clks[IMX6QDL_CLK_IPG_PER] = imx_clk_divider("ipg_per", "ipg", base + 0x1c, 0, 6);
clks[IMX6QDL_CLK_CAN_ROOT] = imx_clk_divider("can_root", "pll3_usb_otg", base + 0x20, 2, 6);
clks[IMX6QDL_CLK_ECSPI_ROOT] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6);
clks[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6);
clks[IMX6QDL_CLK_USDHC1_PODF] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3);
clks[IMX6QDL_CLK_USDHC2_PODF] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3);
clks[IMX6QDL_CLK_USDHC3_PODF] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3);
clks[IMX6QDL_CLK_USDHC4_PODF] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3);
clks[IMX6QDL_CLK_ENFC_PRED] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3);
clks[IMX6QDL_CLK_ENFC_PODF] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6);
clks[IMX6QDL_CLK_EIM_PODF] = imx_clk_divider("eim_podf", "eim_sel", base + 0x1c, 20, 3);
clks[IMX6QDL_CLK_EIM_SLOW_PODF] = imx_clk_divider("eim_slow_podf", "eim_slow_sel", base + 0x1c, 23, 3);
clks[IMX6QDL_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3);
clks[IMX6QDL_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3);
/* name parent_name reg shift width busy: reg, shift */
clks[IMX6QDL_CLK_AXI] = imx_clk_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0);
clks[IMX6QDL_CLK_MMDC_CH0_AXI_PODF] = imx_clk_busy_divider("mmdc_ch0_axi_podf", "periph", base + 0x14, 19, 3, base + 0x48, 4);
clks[IMX6QDL_CLK_MMDC_CH1_AXI_PODF] = imx_clk_busy_divider("mmdc_ch1_axi_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2);
clks[IMX6QDL_CLK_ARM] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16);
clks[IMX6QDL_CLK_AHB] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1);
/* name parent_name reg shift */
clks[IMX6QDL_CLK_APBH_DMA] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4);
clks[IMX6QDL_CLK_CAAM_MEM] = imx_clk_gate2("caam_mem", "ahb", base + 0x68, 8);
clks[IMX6QDL_CLK_CAAM_ACLK] = imx_clk_gate2("caam_aclk", "ahb", base + 0x68, 10);
clks[IMX6QDL_CLK_CAAM_IPG] = imx_clk_gate2("caam_ipg", "ipg", base + 0x68, 12);
clks[IMX6QDL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0);
clks[IMX6QDL_CLK_ECSPI2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2);
clks[IMX6QDL_CLK_ECSPI3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4);
clks[IMX6QDL_CLK_ECSPI4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6);
if (cpu_is_mx6dl())
clks[IMX6DL_CLK_I2C4] = imx_clk_gate2("i2c4", "ipg_per", base + 0x6c, 8);
else
clks[IMX6Q_CLK_ECSPI5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8);
clks[IMX6QDL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10);
clks[IMX6QDL_CLK_GPT_IPG] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20);
clks[IMX6QDL_CLK_GPT_IPG_PER] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22);
clks[IMX6QDL_CLK_I2C1] = imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6);
clks[IMX6QDL_CLK_I2C2] = imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8);
clks[IMX6QDL_CLK_I2C3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10);
clks[IMX6QDL_CLK_IIM] = imx_clk_gate2("iim", "ipg", base + 0x70, 12);
clks[IMX6QDL_CLK_ENFC] = imx_clk_gate2("enfc", "enfc_podf", base + 0x70, 14);
clks[IMX6QDL_CLK_PCIE_AXI] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0);
clks[IMX6QDL_CLK_PER1_BCH] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12);
clks[IMX6QDL_CLK_PWM1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16);
clks[IMX6QDL_CLK_PWM2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18);
clks[IMX6QDL_CLK_PWM3] = imx_clk_gate2("pwm3", "ipg_per", base + 0x78, 20);
clks[IMX6QDL_CLK_PWM4] = imx_clk_gate2("pwm4", "ipg_per", base + 0x78, 22);
clks[IMX6QDL_CLK_GPMI_BCH_APB] = imx_clk_gate2("gpmi_bch_apb", "usdhc3", base + 0x78, 24);
clks[IMX6QDL_CLK_GPMI_BCH] = imx_clk_gate2("gpmi_bch", "usdhc4", base + 0x78, 26);
clks[IMX6QDL_CLK_GPMI_IO] = imx_clk_gate2("gpmi_io", "enfc", base + 0x78, 28);
clks[IMX6QDL_CLK_GPMI_APB] = imx_clk_gate2("gpmi_apb", "usdhc3", base + 0x78, 30);
clks[IMX6QDL_CLK_SATA] = imx_clk_gate2("sata", "ipg", base + 0x7c, 4);
clks[IMX6QDL_CLK_UART_IPG] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24);
clks[IMX6QDL_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26);
clks[IMX6QDL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0);
clks[IMX6QDL_CLK_USDHC1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2);
clks[IMX6QDL_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4);
clks[IMX6QDL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
clks[IMX6QDL_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
clks[IMX6QDL_CLK_EIM_SLOW] = imx_clk_gate2("eim_slow", "eim_slow_podf", base + 0x80, 10);
clks[IMX6QDL_CLK_CKO1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7);
clks[IMX6QDL_CLK_CKO2] = imx_clk_gate("cko2", "cko2_podf", base + 0x60, 24);
clkdev_add_physbase(clks[IMX6QDL_CLK_IPG], MX6_OCOTP_BASE_ADDR, NULL);
if (IS_ENABLED(CONFIG_DRIVER_VIDEO_IMX_IPUV3))
imx6_add_video_clks(anatop_base, ccm_base);
writel(0xffffffff, ccm_base + CCGR0);
writel(0xf0ffffff, ccm_base + CCGR1); /* gate GPU3D, GPU2D */
writel(0xffffffff, ccm_base + CCGR2);
if (IS_ENABLED(CONFIG_DRIVER_VIDEO_IMX_IPUV3))
writel(0xffffffff, ccm_base + CCGR3); /* gate OpenVG */
else
writel(0x3fffffff, ccm_base + CCGR3); /* gate OpenVG, LDB, IPU1, IPU2 */
writel(0xffffffff, ccm_base + CCGR4);
writel(0xffffffff, ccm_base + CCGR5);
writel(0xffff3fff, ccm_base + CCGR6); /* gate VPU */
writel(0xffffffff, ccm_base + CCGR7);
clk_data.clks = clks;
clk_data.clk_num = IMX6QDL_CLK_END;
of_clk_add_provider(dev->device_node, of_clk_src_onecell_get, &clk_data);
clk_enable(clks[IMX6QDL_CLK_MMDC_CH0_AXI_PODF]);
clk_enable(clks[IMX6QDL_CLK_PLL6_ENET]);
clk_enable(clks[IMX6QDL_CLK_SATA_REF_100M]);
clk_enable(clks[IMX6QDL_CLK_ENFC_PODF]);
clk_set_parent(clks[IMX6QDL_CLK_LVDS1_SEL], clks[IMX6QDL_CLK_SATA_REF_100M]);
return 0;
}
static int imx_chipidea_probe(struct device_d *dev)
{
struct resource *iores;
struct imxusb_platformdata *pdata = dev->platform_data;
int ret;
void __iomem *base;
struct imx_chipidea *ci;
uint32_t portsc;
ci = xzalloc(sizeof(*ci));
ci->dev = dev;
ci->role_registered = IMX_USB_MODE_OTG;
if (IS_ENABLED(CONFIG_OFDEVICE) && dev->device_node) {
ret = imx_chipidea_probe_dt(ci);
if (ret)
return ret;
} else {
if (!pdata) {
dev_err(dev, "no pdata!\n");
return -EINVAL;
}
ci->portno = dev->id;
ci->flags = pdata->flags;
ci->phymode = pdata->phymode;
ci->mode = pdata->mode;
}
ci->vbus = regulator_get(dev, "vbus");
if (IS_ERR(ci->vbus))
ci->vbus = NULL;
if (of_property_read_bool(dev->device_node, "fsl,usbphy")) {
ci->phy = of_phy_get_by_phandle(dev, "fsl,usbphy", 0);
if (IS_ERR(ci->phy)) {
ret = PTR_ERR(ci->phy);
dev_err(dev, "Cannot get phy: %s\n", strerror(-ret));
return ret;
} else {
ci->usbphy = phy_to_usbphy(ci->phy);
if (IS_ERR(ci->usbphy))
return PTR_ERR(ci->usbphy);
ret = phy_init(ci->phy);
if (ret)
return ret;
}
}
iores = dev_request_mem_resource(dev, 0);
if (IS_ERR(iores))
return PTR_ERR(iores);
base = IOMEM(iores->start);
ci->base = base;
ci->data.init = imx_chipidea_port_init;
ci->data.post_init = imx_chipidea_port_post_init;
ci->data.drvdata = ci;
ci->data.usbphy = ci->usbphy;
if ((ci->flags & MXC_EHCI_PORTSC_MASK) == MXC_EHCI_MODE_HSIC)
imx_chipidea_port_init(ci);
if (ci->phymode != USBPHY_INTERFACE_MODE_UNKNOWN) {
portsc = readl(base + 0x184);
portsc &= ~MXC_EHCI_PORTSC_MASK;
portsc |= ci->flags & MXC_EHCI_PORTSC_MASK;
writel(portsc, base + 0x184);
}
ci->data.hccr = base + 0x100;
ci->data.hcor = base + 0x140;
ci->data.flags = EHCI_HAS_TT;
if (ci->mode == IMX_USB_MODE_OTG)
ret = ci_register_otg_device(ci);
else
ret = ci_register_role(ci);
return ret;
};
static int __init i2c_fsl_probe(struct device_d *pdev)
{
struct resource *iores;
struct fsl_i2c_struct *i2c_fsl;
struct i2c_platform_data *pdata;
int ret;
pdata = pdev->platform_data;
i2c_fsl = xzalloc(sizeof(*i2c_fsl));
#ifdef CONFIG_COMMON_CLK
i2c_fsl->clk = clk_get(pdev, NULL);
if (IS_ERR(i2c_fsl->clk)) {
ret = PTR_ERR(i2c_fsl->clk);
goto fail;
}
clk_enable(i2c_fsl->clk);
#endif
if (IS_ENABLED(CONFIG_OFDEVICE)) {
i2c_fsl->hwdata = of_device_get_match_data(pdev);
if (!i2c_fsl->hwdata) {
ret = -EINVAL;
goto fail;
}
} else {
i2c_fsl->hwdata = &imx21_i2c_hwdata;
}
/* Setup i2c_fsl driver structure */
i2c_fsl->adapter.master_xfer = i2c_fsl_xfer;
i2c_fsl->adapter.nr = pdev->id;
i2c_fsl->adapter.dev.parent = pdev;
i2c_fsl->adapter.dev.device_node = pdev->device_node;
iores = dev_request_mem_resource(pdev, 0);
if (IS_ERR(iores)) {
ret = PTR_ERR(iores);
goto fail;
}
i2c_fsl->base = IOMEM(iores->start);
i2c_fsl_init_recovery(i2c_fsl, pdev);
i2c_fsl->dfsrr = -1;
/* Set up clock divider */
if (pdata && pdata->bitrate)
i2c_fsl_set_clk(i2c_fsl, pdata->bitrate);
else
i2c_fsl_set_clk(i2c_fsl, FSL_I2C_BIT_RATE);
/* Set up chip registers to defaults */
fsl_i2c_write_reg(i2c_fsl->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
i2c_fsl, FSL_I2C_I2CR);
fsl_i2c_write_reg(i2c_fsl->hwdata->i2sr_clr_opcode, i2c_fsl, FSL_I2C_I2SR);
/* Add I2C adapter */
ret = i2c_add_numbered_adapter(&i2c_fsl->adapter);
if (ret < 0) {
dev_err(pdev, "registration failed\n");
goto fail;
}
return 0;
fail:
kfree(i2c_fsl);
return ret;
}
static int imx_ocotp_probe(struct device_d *dev)
{
struct resource *iores;
struct ocotp_priv *priv;
int ret = 0;
const struct imx_ocotp_data *data;
struct nvmem_device *nvmem;
ret = dev_get_drvdata(dev, (const void **)&data);
if (ret)
return ret;
iores = dev_request_mem_resource(dev, 0);
if (IS_ERR(iores))
return PTR_ERR(iores);
priv = xzalloc(sizeof(*priv));
priv->data = data;
priv->base = IOMEM(iores->start);
priv->clk = clk_get(dev, NULL);
if (IS_ERR(priv->clk))
return PTR_ERR(priv->clk);
strcpy(priv->dev.name, "ocotp");
priv->dev.parent = dev;
register_device(&priv->dev);
priv->map_config.reg_bits = 32;
priv->map_config.val_bits = 32;
priv->map_config.reg_stride = 4;
priv->map_config.max_register = data->num_regs - 1;
priv->map = regmap_init(dev, &imx_ocotp_regmap_bus, priv, &priv->map_config);
if (IS_ERR(priv->map))
return PTR_ERR(priv->map);
priv->config.name = "imx-ocotp";
priv->config.dev = dev;
priv->config.stride = 4;
priv->config.word_size = 4;
priv->config.size = data->num_regs;
priv->config.bus = &imx_ocotp_nvmem_bus;
dev->priv = priv;
nvmem = nvmem_register(&priv->config);
if (IS_ERR(nvmem))
return PTR_ERR(nvmem);
imx_ocotp = priv;
if (IS_ENABLED(CONFIG_IMX_OCOTP_WRITE)) {
dev_add_param_bool(&(priv->dev), "permanent_write_enable",
NULL, NULL, &priv->permanent_write_enable, NULL);
}
if (IS_ENABLED(CONFIG_NET)) {
int i;
struct ocotp_priv_ethaddr *ethaddr;
for (i = 0; i < priv->data->mac_offsets_num; i++) {
ethaddr = &priv->ethaddr[i];
ethaddr->map = priv->map;
ethaddr->offset = priv->data->mac_offsets[i];
ethaddr->data = data;
dev_add_param_mac(&priv->dev, xasprintf("mac_addr%d", i),
imx_ocotp_set_mac, imx_ocotp_get_mac,
ethaddr->value, ethaddr);
}
/*
* Alias to mac_addr0 for backwards compatibility
*/
ethaddr = &priv->ethaddr[0];
dev_add_param_mac(&priv->dev, "mac_addr",
imx_ocotp_set_mac, imx_ocotp_get_mac,
ethaddr->value, ethaddr);
}
imx_ocotp_init_dt(priv);
dev_add_param_bool(&(priv->dev), "sense_enable", NULL, NULL, &priv->sense_enable, priv);
return 0;
}
