static int zynqmp_qspi_ofdata_to_platdata(struct udevice *bus)
{
struct zynqmp_qspi_platdata *plat = bus->platdata;
int is_dual;
debug("%s\n", __func__);
plat->regs = (struct zynqmp_qspi_regs *)(devfdt_get_addr(bus) +
GQSPI_REG_OFFSET);
plat->dma_regs = (struct zynqmp_qspi_dma_regs *)
(devfdt_get_addr(bus) + GQSPI_DMA_REG_OFFSET);
is_dual = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus), "is-dual", -1);
if (is_dual < 0)
plat->is_dual = SF_SINGLE_FLASH;
else if (is_dual == 1)
plat->is_dual = SF_DUAL_PARALLEL_FLASH;
else
if (fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus),
"is-stacked", -1) < 0)
plat->is_dual = SF_SINGLE_FLASH;
else
plat->is_dual = SF_DUAL_STACKED_FLASH;
plat->io_mode = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(bus),
"has-io-mode");
return 0;
}
static int ftgmac100_ofdata_to_platdata(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct ftgmac100_data *priv = dev_get_priv(dev);
const char *phy_mode;
pdata->iobase = devfdt_get_addr(dev);
pdata->phy_interface = -1;
phy_mode = dev_read_string(dev, "phy-mode");
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
if (pdata->phy_interface == -1) {
dev_err(dev, "Invalid PHY interface '%s'\n", phy_mode);
return -EINVAL;
}
pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
if (dev_get_driver_data(dev) == FTGMAC100_MODEL_ASPEED) {
priv->rxdes0_edorr_mask = BIT(30);
priv->txdes0_edotr_mask = BIT(30);
} else {
priv->rxdes0_edorr_mask = BIT(15);
priv->txdes0_edotr_mask = BIT(15);
}
return clk_get_bulk(dev, &priv->clks);
}
static int atmel_spi_probe(struct udevice *bus)
{
struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus);
int ret;
ret = atmel_spi_enable_clk(bus);
if (ret)
return ret;
bus_plat->regs = (struct at91_spi *)devfdt_get_addr(bus);
#ifdef CONFIG_DM_GPIO
struct atmel_spi_priv *priv = dev_get_priv(bus);
int i;
ret = gpio_request_list_by_name(bus, "cs-gpios", priv->cs_gpios,
ARRAY_SIZE(priv->cs_gpios), 0);
if (ret < 0) {
pr_err("Can't get %s gpios! Error: %d", bus->name, ret);
return ret;
}
for(i = 0; i < ARRAY_SIZE(priv->cs_gpios); i++) {
if (!dm_gpio_is_valid(&priv->cs_gpios[i]))
continue;
dm_gpio_set_dir_flags(&priv->cs_gpios[i],
GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
}
#endif
writel(ATMEL_SPI_CR_SWRST, &bus_plat->regs->cr);
return 0;
}
/**
* We have a top-level GPIO device with no actual GPIOs. It has a child
* device for each Sunxi bank.
*/
static int gpio_sunxi_bind(struct udevice *parent)
{
struct sunxi_gpio_soc_data *soc_data =
(struct sunxi_gpio_soc_data *)dev_get_driver_data(parent);
struct sunxi_gpio_platdata *plat = parent->platdata;
struct sunxi_gpio_reg *ctlr;
int bank, ret;
/* If this is a child device, there is nothing to do here */
if (plat)
return 0;
ctlr = (struct sunxi_gpio_reg *)devfdt_get_addr(parent);
for (bank = 0; bank < soc_data->no_banks; bank++) {
struct sunxi_gpio_platdata *plat;
struct udevice *dev;
plat = calloc(1, sizeof(*plat));
if (!plat)
return -ENOMEM;
plat->regs = &ctlr->gpio_bank[bank];
plat->bank_name = gpio_bank_name(soc_data->start + bank);
plat->gpio_count = SUNXI_GPIOS_PER_BANK;
ret = device_bind(parent, parent->driver,
plat->bank_name, plat, -1, &dev);
if (ret)
return ret;
dev_set_of_offset(dev, dev_of_offset(parent));
}
return 0;
}
static int emaclite_ofdata_to_platdata(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct xemaclite *emaclite = dev_get_priv(dev);
int offset = 0;
pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
emaclite->regs = (struct emaclite_regs *)ioremap_nocache(pdata->iobase,
0x10000);
emaclite->phyaddr = -1;
offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
"phy-handle");
if (offset > 0)
emaclite->phyaddr = fdtdec_get_int(gd->fdt_blob, offset,
"reg", -1);
emaclite->txpp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"xlnx,tx-ping-pong", 0);
emaclite->rxpp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"xlnx,rx-ping-pong", 0);
printf("EMACLITE: %lx, phyaddr %d, %d/%d\n", (ulong)emaclite->regs,
emaclite->phyaddr, emaclite->txpp, emaclite->rxpp);
return 0;
}
static int atmel_hlcdc_ofdata_to_platdata(struct udevice *dev)
{
struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
const void *blob = gd->fdt_blob;
int node = dev_of_offset(dev);
priv->regs = (struct atmel_hlcd_regs *)devfdt_get_addr(dev);
if (!priv->regs) {
debug("%s: No display controller address\n", __func__);
return -EINVAL;
}
if (fdtdec_decode_display_timing(blob, dev_of_offset(dev),
0, &priv->timing)) {
debug("%s: Failed to decode display timing\n", __func__);
return -EINVAL;
}
if (priv->timing.hactive.typ > LCD_MAX_WIDTH)
priv->timing.hactive.typ = LCD_MAX_WIDTH;
if (priv->timing.vactive.typ > LCD_MAX_HEIGHT)
priv->timing.vactive.typ = LCD_MAX_HEIGHT;
priv->vl_bpix = fdtdec_get_int(blob, node, "atmel,vl-bpix", 0);
if (!priv->vl_bpix) {
debug("%s: Failed to get bits per pixel\n", __func__);
return -EINVAL;
}
priv->output_mode = fdtdec_get_int(blob, node, "atmel,output-mode", 24);
priv->guard_time = fdtdec_get_int(blob, node, "atmel,guard-time", 1);
return 0;
}
static int ehci_atmel_probe(struct udevice *dev)
{
struct ehci_hccr *hccr;
struct ehci_hcor *hcor;
fdt_addr_t hcd_base;
int ret;
ret = ehci_atmel_enable_clk(dev);
if (ret) {
debug("Failed to enable USB Host clock\n");
return ret;
}
/*
* Get the base address for EHCI controller from the device node
*/
hcd_base = devfdt_get_addr(dev);
if (hcd_base == FDT_ADDR_T_NONE) {
debug("Can't get the EHCI register base address\n");
return -ENXIO;
}
hccr = (struct ehci_hccr *)hcd_base;
hcor = (struct ehci_hcor *)
((u32)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
debug("echi-atmel: init hccr %x and hcor %x hc_length %d\n",
(u32)hccr, (u32)hcor,
(u32)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
return ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST);
}
static int ti_qspi_ofdata_to_platdata(struct udevice *bus)
{
struct ti_qspi_priv *priv = dev_get_priv(bus);
const void *blob = gd->fdt_blob;
int node = dev_of_offset(bus);
fdt_addr_t mmap_addr;
fdt_addr_t mmap_size;
priv->ctrl_mod_mmap = map_syscon_chipselects(bus);
priv->base = map_physmem(devfdt_get_addr(bus),
sizeof(struct ti_qspi_regs), MAP_NOCACHE);
mmap_addr = devfdt_get_addr_size_index(bus, 1, &mmap_size);
priv->memory_map = map_physmem(mmap_addr, mmap_size, MAP_NOCACHE);
priv->mmap_size = mmap_size;
priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1);
if (priv->max_hz < 0) {
debug("Error: Max frequency missing\n");
return -ENODEV;
}
priv->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);
debug("%s: regs=<0x%x>, max-frequency=%d\n", __func__,
(int)priv->base, priv->max_hz);
return 0;
}
static int tegra20_sflash_ofdata_to_platdata(struct udevice *bus)
{
struct tegra_spi_platdata *plat = bus->platdata;
const void *blob = gd->fdt_blob;
int node = dev_of_offset(bus);
plat->base = devfdt_get_addr(bus);
plat->periph_id = clock_decode_periph_id(bus);
if (plat->periph_id == PERIPH_ID_NONE) {
debug("%s: could not decode periph id %d\n", __func__,
plat->periph_id);
return -FDT_ERR_NOTFOUND;
}
/* Use 500KHz as a suitable default */
plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
500000);
plat->deactivate_delay_us = fdtdec_get_int(blob, node,
"spi-deactivate-delay", 0);
debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
__func__, plat->base, plat->periph_id, plat->frequency,
plat->deactivate_delay_us);
return 0;
}
static int msm_spmi_probe(struct udevice *dev)
{
struct udevice *parent = dev->parent;
struct msm_spmi_priv *priv = dev_get_priv(dev);
int node = dev_of_offset(dev);
int i;
priv->arb_chnl = devfdt_get_addr(dev);
priv->spmi_core = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
dev_of_offset(parent), node, "reg", 1, NULL, false);
priv->spmi_obs = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
dev_of_offset(parent), node, "reg", 2, NULL, false);
if (priv->arb_chnl == FDT_ADDR_T_NONE ||
priv->spmi_core == FDT_ADDR_T_NONE ||
priv->spmi_obs == FDT_ADDR_T_NONE)
return -EINVAL;
/* Scan peripherals connected to each SPMI channel */
for (i = 0; i < SPMI_MAX_CHANNELS ; i++) {
uint32_t periph = readl(priv->arb_chnl + ARB_CHANNEL_OFFSET(i));
uint8_t slave_id = (periph & 0xf0000) >> 16;
uint8_t pid = (periph & 0xff00) >> 8;
priv->channel_map[slave_id][pid] = i;
}
return 0;
}
static int rcar_gpio_probe(struct udevice *dev)
{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct rcar_gpio_priv *priv = dev_get_priv(dev);
struct fdtdec_phandle_args args;
struct clk clk;
int node = dev_of_offset(dev);
int ret;
priv->regs = (void __iomem *)devfdt_get_addr(dev);
uc_priv->bank_name = dev->name;
ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, node, "gpio-ranges",
NULL, 3, 0, &args);
uc_priv->gpio_count = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
ret = clk_get_by_index(dev, 0, &clk);
if (ret < 0) {
dev_err(dev, "Failed to get GPIO bank clock\n");
return ret;
}
ret = clk_enable(&clk);
clk_free(&clk);
if (ret) {
dev_err(dev, "Failed to enable GPIO bank clock\n");
return ret;
}
return 0;
}
static int ftsdc010_mmc_ofdata_to_platdata(struct udevice *dev)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct ftsdc_priv *priv = dev_get_priv(dev);
struct ftsdc010_chip *chip = &priv->chip;
chip->name = dev->name;
chip->ioaddr = (void *)devfdt_get_addr(dev);
chip->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"bus-width", 4);
chip->priv = dev;
priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"fifo-depth", 0);
priv->fifo_mode = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
"fifo-mode");
if (fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
"clock-freq-min-max", priv->minmax, 2)) {
int val = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"max-frequency", -EINVAL);
if (val < 0)
return val;
priv->minmax[0] = 400000; /* 400 kHz */
priv->minmax[1] = val;
} else {
debug("%s: 'clock-freq-min-max' property was deprecated.\n",
__func__);
}
#endif
chip->sclk = priv->minmax[1];
chip->regs = chip->ioaddr;
return 0;
}
static int macb_eth_ofdata_to_platdata(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
pdata->iobase = devfdt_get_addr(dev);
return 0;
}
static int xenon_sdhci_ofdata_to_platdata(struct udevice *dev)
{
struct sdhci_host *host = dev_get_priv(dev);
struct xenon_sdhci_priv *priv = dev_get_priv(dev);
const char *name;
host->name = dev->name;
host->ioaddr = (void *)devfdt_get_addr(dev);
if (device_is_compatible(dev, "marvell,armada-3700-sdhci"))
priv->pad_ctrl_reg = (void *)devfdt_get_addr_index(dev, 1);
name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "marvell,pad-type",
NULL);
if (name) {
if (0 == strncmp(name, "sd", 2)) {
priv->pad_type = SOC_PAD_SD;
} else if (0 == strncmp(name, "fixed-1-8v", 10)) {
priv->pad_type = SOC_PAD_FIXED_1_8V;
} else {
printf("Unsupported SOC PHY PAD ctrl type %s\n", name);
return -EINVAL;
}
}
return 0;
}
static int rk3036_clk_probe(struct udevice *dev)
{
struct rk3036_clk_priv *priv = dev_get_priv(dev);
priv->cru = (struct rk3036_cru *)devfdt_get_addr(dev);
rkclk_init(priv->cru);
return 0;
}
static int omap_timer_ofdata_to_platdata(struct udevice *dev)
{
struct omap_timer_priv *priv = dev_get_priv(dev);
priv->regs = map_physmem(devfdt_get_addr(dev),
sizeof(struct omap_gptimer_regs), MAP_NOCACHE);
return 0;
}
static int altera_sysid_ofdata_to_platdata(struct udevice *dev)
{
struct altera_sysid_platdata *plat = dev_get_platdata(dev);
plat->regs = map_physmem(devfdt_get_addr(dev),
sizeof(struct altera_sysid_regs),
MAP_NOCACHE);
return 0;
}
static int stm32_serial_ofdata_to_platdata(struct udevice *dev)
{
struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
plat->base = devfdt_get_addr(dev);
if (plat->base == FDT_ADDR_T_NONE)
return -EINVAL;
return 0;
}
static int bcm2835_gpio_ofdata_to_platdata(struct udevice *dev)
{
struct bcm2835_gpio_platdata *plat = dev_get_platdata(dev);
fdt_addr_t addr;
addr = devfdt_get_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
plat->base = addr;
return 0;
}
static int mvebu_gpio_probe(struct udevice *dev)
{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct mvebu_gpio_priv *priv = dev_get_priv(dev);
priv->regs = (struct mvebu_gpio_regs *)devfdt_get_addr(dev);
uc_priv->gpio_count = MVEBU_GPIOS_PER_BANK;
priv->name[0] = 'A' + dev->req_seq;
uc_priv->bank_name = priv->name;
return 0;
}
static int meson_mmc_ofdata_to_platdata(struct udevice *dev)
{
struct meson_mmc_platdata *pdata = dev_get_platdata(dev);
fdt_addr_t addr;
addr = devfdt_get_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
pdata->regbase = (void *)addr;
return 0;
}
static int at91_i2c_ofdata_to_platdata(struct udevice *dev)
{
const void *blob = gd->fdt_blob;
struct at91_i2c_bus *bus = dev_get_priv(dev);
int node = dev_of_offset(dev);
bus->regs = (struct at91_i2c_regs *)devfdt_get_addr(dev);
bus->pdata = (struct at91_i2c_pdata *)dev_get_driver_data(dev);
bus->clock_frequency = fdtdec_get_int(blob, node,
"clock-frequency", 100000);
return 0;
}
static int vf_usb_ofdata_to_platdata(struct udevice *dev)
{
struct ehci_vf_priv_data *priv = dev_get_priv(dev);
const void *dt_blob = gd->fdt_blob;
int node = dev_of_offset(dev);
const char *mode;
priv->portnr = dev->seq;
priv->ehci = (struct usb_ehci *)devfdt_get_addr(dev);
mode = fdt_getprop(dt_blob, node, "dr_mode", NULL);
if (mode) {
if (0 == strcmp(mode, "host")) {
priv->dr_mode = DR_MODE_HOST;
priv->init_type = USB_INIT_HOST;
} else if (0 == strcmp(mode, "peripheral")) {
priv->dr_mode = DR_MODE_DEVICE;
priv->init_type = USB_INIT_DEVICE;
} else if (0 == strcmp(mode, "otg")) {
priv->dr_mode = DR_MODE_OTG;
/*
* We set init_type to device by default when OTG
* mode is requested. If a valid gpio is provided
* we will switch the init_type based on the state
* of the gpio pin.
*/
priv->init_type = USB_INIT_DEVICE;
} else {
debug("%s: Cannot decode dr_mode '%s'\n",
__func__, mode);
return -EINVAL;
}
} else {
priv->dr_mode = DR_MODE_HOST;
priv->init_type = USB_INIT_HOST;
}
if (priv->dr_mode == DR_MODE_OTG) {
gpio_request_by_name_nodev(offset_to_ofnode(node),
"fsl,cdet-gpio", 0, &priv->cdet_gpio,
GPIOD_IS_IN);
if (dm_gpio_is_valid(&priv->cdet_gpio)) {
if (dm_gpio_get_value(&priv->cdet_gpio))
priv->init_type = USB_INIT_DEVICE;
else
priv->init_type = USB_INIT_HOST;
}
}
return 0;
}
static int axi_emac_ofdata_to_platdata(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct axidma_priv *priv = dev_get_priv(dev);
int node = dev_of_offset(dev);
int offset = 0;
const char *phy_mode;
pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
priv->iobase = (struct axi_regs *)pdata->iobase;
offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
"axistream-connected");
if (offset <= 0) {
printf("%s: axistream is not found\n", __func__);
return -EINVAL;
}
priv->dmatx = (struct axidma_reg *)fdtdec_get_addr(gd->fdt_blob,
offset, "reg");
if (!priv->dmatx) {
printf("%s: axi_dma register space not found\n", __func__);
return -EINVAL;
}
/* RX channel offset is 0x30 */
priv->dmarx = (struct axidma_reg *)((u32)priv->dmatx + 0x30);
priv->phyaddr = -1;
offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle");
if (offset > 0)
priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
if (pdata->phy_interface == -1) {
printf("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
return -EINVAL;
}
priv->interface = pdata->phy_interface;
priv->eth_hasnobuf = fdtdec_get_bool(gd->fdt_blob, node,
"xlnx,eth-hasnobuf");
printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase,
priv->phyaddr, phy_string_for_interface(priv->interface));
return 0;
}
static int sun4i_spi_ofdata_to_platdata(struct udevice *bus)
{
struct sun4i_spi_platdata *plat = dev_get_platdata(bus);
int node = dev_of_offset(bus);
plat->base_addr = devfdt_get_addr(bus);
plat->max_hz = fdtdec_get_int(gd->fdt_blob, node,
"spi-max-frequency",
SUN4I_SPI_DEFAULT_RATE);
if (plat->max_hz > SUN4I_SPI_MAX_RATE)
plat->max_hz = SUN4I_SPI_MAX_RATE;
return 0;
}
static int xhci_usb_ofdata_to_platdata(struct udevice *dev)
{
struct mvebu_xhci_platdata *plat = dev_get_platdata(dev);
/*
* Get the base address for XHCI controller from the device node
*/
plat->hcd_base = devfdt_get_addr(dev);
if (plat->hcd_base == FDT_ADDR_T_NONE) {
debug("Can't get the XHCI register base address\n");
return -ENXIO;
}
return 0;
}
static int uniphier_reset_probe(struct udevice *dev)
{
struct uniphier_reset_priv *priv = dev_get_priv(dev);
fdt_addr_t addr;
addr = devfdt_get_addr(dev->parent);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
priv->base = devm_ioremap(dev, addr, SZ_4K);
if (!priv->base)
return -ENOMEM;
priv->data = (void *)dev_get_driver_data(dev);
return 0;
}
static int ehci_usb_ofdata_to_platdata(struct udevice *dev)
{
struct msm_ehci_priv *priv = dev_get_priv(dev);
priv->ulpi_vp.port_num = 0;
priv->ehci = (void *)devfdt_get_addr(dev);
if (priv->ehci == (void *)FDT_ADDR_T_NONE)
return -EINVAL;
/* Warning: this will not work if viewport address is > 64 bit due to
* ULPI design.
*/
priv->ulpi_vp.viewport_addr = (phys_addr_t)&priv->ehci->ulpi_viewpoint;
return 0;
}
static int sdhci_cdns_probe(struct udevice *dev)
{
DECLARE_GLOBAL_DATA_PTR;
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct sdhci_cdns_plat *plat = dev_get_platdata(dev);
struct sdhci_host *host = dev_get_priv(dev);
fdt_addr_t base;
int ret;
base = devfdt_get_addr(dev);
if (base == FDT_ADDR_T_NONE)
return -EINVAL;
plat->hrs_addr = devm_ioremap(dev, base, SZ_1K);
if (!plat->hrs_addr)
return -ENOMEM;
host->name = dev->name;
host->ioaddr = plat->hrs_addr + SDHCI_CDNS_SRS_BASE;
host->ops = &sdhci_cdns_ops;
host->quirks |= SDHCI_QUIRK_WAIT_SEND_CMD;
sdhci_cdns_mmc_ops = sdhci_ops;
#ifdef MMC_SUPPORTS_TUNING
sdhci_cdns_mmc_ops.execute_tuning = sdhci_cdns_execute_tuning;
#endif
ret = mmc_of_parse(dev, &plat->cfg);
if (ret)
return ret;
ret = sdhci_cdns_phy_init(plat, gd->fdt_blob, dev_of_offset(dev));
if (ret)
return ret;
ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);
if (ret)
return ret;
upriv->mmc = &plat->mmc;
host->mmc = &plat->mmc;
host->mmc->priv = host;
return sdhci_probe(dev);
}
static int uniphier_gpio_probe(struct udevice *dev)
{
struct uniphier_gpio_priv *priv = dev_get_priv(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
fdt_addr_t addr;
addr = devfdt_get_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
priv->regs = devm_ioremap(dev, addr, SZ_512);
if (!priv->regs)
return -ENOMEM;
uc_priv->gpio_count = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
"ngpios", 0);
return 0;
}
