static int bd82x6x_northbridge_early_init(struct udevice *dev)
{
const int chipset_type = SANDYBRIDGE_MOBILE;
u32 capid0_a;
u8 reg8;
/* Device ID Override Enable should be done very early */
dm_pci_read_config32(dev, 0xe4, &capid0_a);
if (capid0_a & (1 << 10)) {
dm_pci_read_config8(dev, 0xf3, ®8);
reg8 &= ~7; /* Clear 2:0 */
if (chipset_type == SANDYBRIDGE_MOBILE)
reg8 |= 1; /* Set bit 0 */
dm_pci_write_config8(dev, 0xf3, reg8);
}
sandybridge_setup_northbridge_bars(dev);
/* Device Enable */
dm_pci_write_config32(dev, DEVEN, DEVEN_HOST | DEVEN_IGD);
return 0;
}
/*
* Enable Prefetching and Caching.
*/
static void enable_spi_prefetch(struct udevice *pch)
{
u8 reg8;
dm_pci_read_config8(pch, 0xdc, ®8);
reg8 &= ~(3 << 2);
reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
dm_pci_write_config8(pch, 0xdc, reg8);
}
static void pch_disable_smm_only_flashing(struct udevice *pch)
{
u8 reg8;
debug("Enabling BIOS updates outside of SMM... ");
dm_pci_read_config8(pch, 0xdc, ®8); /* BIOS_CNTL */
reg8 &= ~(1 << 5);
dm_pci_write_config8(pch, 0xdc, reg8);
}
int pch_silicon_type(struct udevice *dev)
{
u8 val;
if (pch_type < 0) {
dm_pci_read_config8(dev, PCI_DEVICE_ID + 1, &val);
pch_type = val;
}
return pch_type;
}
/**
* pch_silicon_revision() - Read silicon revision ID from the PCH
*
* @dev: PCH device
* @return silicon revision ID
*/
static int pch_silicon_revision(struct udevice *dev)
{
u8 val;
if (pch_revision_id < 0) {
dm_pci_read_config8(dev, PCI_REVISION_ID, &val);
pch_revision_id = val;
}
return pch_revision_id;
}
static int pch7_set_spi_protect(struct udevice *dev, bool protect)
{
uint8_t bios_cntl;
/* Adjust the BIOS write protect to dis/allow write commands */
dm_pci_read_config8(dev, BIOS_CTRL, &bios_cntl);
if (protect)
bios_cntl &= ~BIOS_CTRL_BIOSWE;
else
bios_cntl |= BIOS_CTRL_BIOSWE;
dm_pci_write_config8(dev, BIOS_CTRL, bios_cntl);
return 0;
}
static void pch_fixups(struct udevice *pch)
{
u8 gen_pmcon_2;
/* Indicate DRAM init done for MRC S3 to know it can resume */
dm_pci_read_config8(pch, GEN_PMCON_2, &gen_pmcon_2);
gen_pmcon_2 |= (1 << 7);
dm_pci_write_config8(pch, GEN_PMCON_2, gen_pmcon_2);
/* Enable DMI ASPM in the PCH */
clrbits_le32(RCB_REG(0x2304), 1 << 10);
setbits_le32(RCB_REG(0x21a4), (1 << 11) | (1 << 10));
setbits_le32(RCB_REG(0x21a8), 0x3);
}
static void pch_rtc_init(struct udevice *pch)
{
int rtc_failed;
u8 reg8;
dm_pci_read_config8(pch, GEN_PMCON_3, ®8);
rtc_failed = reg8 & RTC_BATTERY_DEAD;
if (rtc_failed) {
reg8 &= ~RTC_BATTERY_DEAD;
dm_pci_write_config8(pch, GEN_PMCON_3, reg8);
}
debug("rtc_failed = 0x%x\n", rtc_failed);
/* TODO: Handle power failure */
if (rtc_failed)
printf("RTC power failed\n");
}
static void report_pch_info(struct udevice *dev)
{
const char *pch_type = "Unknown";
int i;
u16 dev_id;
uint8_t rev_id;
dm_pci_read_config16(dev, 2, &dev_id);
for (i = 0; i < ARRAY_SIZE(pch_table); i++) {
if (pch_table[i].dev_id == dev_id) {
pch_type = pch_table[i].dev_name;
break;
}
}
dm_pci_read_config8(dev, 8, &rev_id);
debug("PCH type: %s, device id: %x, rev id %x\n", pch_type, dev_id,
rev_id);
}
bool pirq_check_irq_routed(struct udevice *dev, int link, u8 irq)
{
struct irq_router *priv = dev_get_priv(dev);
u8 pirq;
int base = priv->link_base;
if (priv->config == PIRQ_VIA_PCI)
dm_pci_read_config8(dev->parent, LINK_N2V(link, base), &pirq);
else
pirq = readb(priv->ibase + LINK_N2V(link, base));
pirq &= 0xf;
/* IRQ# 0/1/2/8/13 are reserved */
if (pirq < 3 || pirq == 8 || pirq == 13)
return false;
return pirq == irq ? true : false;
}
int pci_bar_show(struct udevice *dev)
{
u8 header_type;
int bar_cnt, bar_id, mem_type;
bool is_64, is_io;
u32 base_low, base_high;
u32 size_low, size_high;
u64 base, size;
u32 reg_addr;
int prefetchable;
dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
if (header_type == PCI_HEADER_TYPE_CARDBUS) {
printf("CardBus doesn't support BARs\n");
return -ENOSYS;
}
bar_cnt = (header_type == PCI_HEADER_TYPE_NORMAL) ? 6 : 2;
printf("ID Base Size Width Type\n");
printf("----------------------------------------------------------\n");
bar_id = 0;
reg_addr = PCI_BASE_ADDRESS_0;
while (bar_cnt) {
dm_pci_read_config32(dev, reg_addr, &base_low);
dm_pci_write_config32(dev, reg_addr, 0xffffffff);
dm_pci_read_config32(dev, reg_addr, &size_low);
dm_pci_write_config32(dev, reg_addr, base_low);
reg_addr += 4;
base = base_low & ~0xf;
size = size_low & ~0xf;
base_high = 0x0;
size_high = 0xffffffff;
is_64 = 0;
prefetchable = base_low & PCI_BASE_ADDRESS_MEM_PREFETCH;
is_io = base_low & PCI_BASE_ADDRESS_SPACE_IO;
mem_type = base_low & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
if (mem_type == PCI_BASE_ADDRESS_MEM_TYPE_64) {
dm_pci_read_config32(dev, reg_addr, &base_high);
dm_pci_write_config32(dev, reg_addr, 0xffffffff);
dm_pci_read_config32(dev, reg_addr, &size_high);
dm_pci_write_config32(dev, reg_addr, base_high);
bar_cnt--;
reg_addr += 4;
is_64 = 1;
}
base = base | ((u64)base_high << 32);
size = size | ((u64)size_high << 32);
if ((!is_64 && size_low) || (is_64 && size)) {
size = ~size + 1;
printf(" %d %#016llx %#016llx %d %s %s\n",
bar_id, (unsigned long long)base,
(unsigned long long)size, is_64 ? 64 : 32,
is_io ? "I/O" : "MEM",
prefetchable ? "Prefetchable" : "");
}
bar_id++;
bar_cnt--;
}
return 0;
}
