void sCPU::dma_run() { dma_add_clocks(8); cycle_edge(); for(unsigned i = 0; i < 8; i++) { if(channel[i].dma_enabled == false) continue; dma_add_clocks(8); cycle_edge(); unsigned index = 0; do { dma_transfer(channel[i].direction, dma_bbus(i, index++), dma_addr(i)); } while(channel[i].dma_enabled && --channel[i].xfersize); channel[i].dma_enabled = false; } status.irq_lock = true; event.enqueue(2, EventIrqLockRelease); }
void CPU::dma_run() { add_clocks(8); dma_edge(); for(unsigned i = 0; i < 8; i++) { if(channel[i].dma_enabled == false) continue; add_clocks(8); dma_edge(); unsigned index = 0; do { dma_transfer(channel[i].direction, dma_bbus(i, index++), dma_addr(i)); dma_edge(); } while(channel[i].dma_enabled && --channel[i].transfer_size); channel[i].dma_enabled = false; } status.irq_lock = true; }