void run_scu_operation(machinecode *program, int *pc, int *convert, union bit *reg) {
switch(program[*pc].opcode) {
case 0: /* set reg */
reg_set(reg, program[*pc].dr, reg_ref(reg,program[*pc].sr2,convert), convert);
(*pc)++;
break;
case (0 + IMD_SIZE): /* set imd */
reg_set(reg, program[*pc].dr, program[*pc].imd, convert);
(*pc)++;
break;
case 1: /* + reg */
reg_set(reg, program[*pc].dr, do_plus(reg_ref(reg,program[*pc].sr1,convert),reg_ref(reg,program[*pc].sr2,convert)), convert);
(*pc)++;
break;
case (1 + IMD_SIZE): /* + imd */
reg_set(reg, program[*pc].dr, do_plus(reg_ref(reg,program[*pc].sr1,convert),program[*pc].imd), convert);
(*pc)++;
break;
case 2: /* - reg */
reg_set(reg, program[*pc].dr, do_minus(reg_ref(reg,program[*pc].sr1,convert),reg_ref(reg,program[*pc].sr2,convert)), convert);
(*pc)++;
break;
case (2 + IMD_SIZE): /* - imd */
reg_set(reg, program[*pc].dr, do_minus(reg_ref(reg,program[*pc].sr1,convert),program[*pc].imd), convert);
(*pc)++;
break;
case 3: /* xor reg */
reg_set(reg, program[*pc].dr, do_xor(reg_ref(reg,program[*pc].sr1,convert),reg_ref(reg,program[*pc].sr2,convert)), convert);
(*pc)++;
break;
case (3 + IMD_SIZE): /* xor imd */
reg_set(reg, program[*pc].dr, do_xor(reg_ref(reg,program[*pc].sr1,convert),program[*pc].imd), convert);
(*pc)++;
break;
case 4: /* or reg */
reg_set(reg, program[*pc].dr, do_or(reg_ref(reg,program[*pc].sr1,convert),reg_ref(reg,program[*pc].sr2,convert)), convert);
(*pc)++;
break;
case (4 + IMD_SIZE): /* or imd */
reg_set(reg, program[*pc].dr, do_or(reg_ref(reg,program[*pc].sr1,convert),program[*pc].imd), convert);
(*pc)++;
break;
case 5: /* and reg */
reg_set(reg, program[*pc].dr, do_and(reg_ref(reg,program[*pc].sr1,convert),reg_ref(reg,program[*pc].sr2,convert)), convert);
(*pc)++;
break;
case (5 + IMD_SIZE): /* adn imd */
reg_set(reg, program[*pc].dr, do_and(reg_ref(reg,program[*pc].sr1,convert),program[*pc].imd), convert);
(*pc)++;
break;
case 6: /* not reg */
reg_set(reg, program[*pc].dr, do_not(reg_ref(reg,program[*pc].sr2,convert)), convert);
(*pc)++;
break;
case (6 + IMD_SIZE): /* not imd */
reg_set(reg, program[*pc].dr, do_not(program[*pc].imd), convert);
(*pc)++;
break;
default:
fprintf(stderr, "%2x : unknown instruction\n", (program[*pc].info)+(program[*pc].opcode));
exit(EXIT_FAILURE);
}
}
static void
codegen14(enum node_op op,
enum size_tag size,
gp_boolean is_const,
int value,
char *name)
{
switch (op) {
case op_assign:
assert(0);
break;
case op_add:
do_add(size, is_const, value, name);
break;
case op_sub:
do_sub(size, is_const, value, name);
break;
case op_neg:
do_neg(size, is_const, value, name);
break;
case op_com:
do_com(size, is_const, value, name);
break;
case op_and:
do_and(size, is_const, value, name);
break;
case op_or:
do_or(size, is_const, value, name);
break;
case op_xor:
do_xor(size, is_const, value, name);
break;
case op_not:
do_not(size, is_const, value, name);
break;
case op_lsh:
do_lsh(size, is_const, value, name);
break;
case op_rsh:
do_rsh(size, is_const, value, name);
break;
case op_land:
do_and(size_uint8, is_const, value, name);
break;
case op_lor:
do_or(size_uint8, is_const, value, name);
break;
case op_eq:
do_eq(size, is_const, value, name);
break;
case op_ne:
do_ne(size, is_const, value, name);
break;
case op_lt:
do_lt(size, is_const, value, name);
break;
case op_lte:
do_lte(size, is_const, value, name);
break;
case op_gt:
case op_gte:
/* This is replaced in the optimizer.*/
assert(0);
break;
case op_mult:
do_mult(size, is_const, value, name);
break;
case op_div:
do_div(size, is_const, value, name);
break;
case op_mod:
do_mod(size, is_const, value, name);
break;
case op_clr:
case op_inc:
case op_dec:
/* Shoud use unopgen14.*/
assert(0);
break;
default:
assert(0); /* Unhandled binary operator */
}
}
