Ejemplo n.º 1
0
void late_recalibrate_iodelay(struct pad_conf_entry const *pad, int npads,
			      struct iodelay_cfg_entry const *iodelay,
			      int niodelays)
{
	int ret = 0;

	/* unlock IODELAY CONFIG registers */
	writel(CFG_IODELAY_UNLOCK_KEY, (*ctrl)->iodelay_config_base +
	       CFG_REG_8_OFFSET);

	ret = calibrate_iodelay((*ctrl)->iodelay_config_base);
	if (ret)
		goto err;

	ret = update_delay_mechanism((*ctrl)->iodelay_config_base);

	/* Configure Mux settings */
	do_set_mux32((*ctrl)->control_padconf_core_base, pad, npads);

	/* Configure Manual IO timing modes */
	ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
	if (ret)
		goto err;

err:
	/* lock IODELAY CONFIG registers */
	writel(CFG_IODELAY_LOCK_KEY, (*ctrl)->iodelay_config_base +
	       CFG_REG_8_OFFSET);
}
Ejemplo n.º 2
0
void __recalibrate_iodelay(struct pad_conf_entry const *pad, int npads,
			   struct iodelay_cfg_entry const *iodelay,
			   int niodelays)
{
	int ret = 0;

	/* IO recalibration should be done only from SRAM */
	if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context()) {
		puts("IODELAY recalibration called from invalid context - use only from SPL in SRAM\n");
		return;
	}

	ret = __recalibrate_iodelay_start();
	if (ret)
		goto err;

	/* Configure Mux settings */
	do_set_mux32((*ctrl)->control_padconf_core_base, pad, npads);

	/* Configure Manual IO timing modes */
	ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
	if (ret)
		goto err;

err:
	__recalibrate_iodelay_end(ret);

}
Ejemplo n.º 3
0
void recalibrate_iodelay(void)
{
	const struct pad_conf_entry *pconf;
	const struct iodelay_cfg_entry *iod;
	int pconf_sz, iod_sz;
	int ret;

	if (board_is_am572x_idk()) {
		pconf = core_padconf_array_essential_am572x_idk;
		pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
		iod = iodelay_cfg_array_am572x_idk;
		iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
	} else if (board_is_am571x_idk()) {
		pconf = core_padconf_array_essential_am571x_idk;
		pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk);
		iod = iodelay_cfg_array_am571x_idk;
		iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk);
	} else {
		/* Common for X15/GPEVM */
		pconf = core_padconf_array_essential_x15;
		pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
		/* There never was an SR1.0 X15.. So.. */
		if (omap_revision() == DRA752_ES1_1) {
			iod = iodelay_cfg_array_x15_sr1_1;
			iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr1_1);
		} else {
			/* Since full production should switch to SR2.0  */
			iod = iodelay_cfg_array_x15_sr2_0;
			iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr2_0);
		}
	}

	/* Setup I/O isolation */
	ret = __recalibrate_iodelay_start();
	if (ret)
		goto err;

	/* Do the muxing here */
	do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);

	/* Now do the weird minor deltas that should be safe */
	if (board_is_x15() || board_is_am572x_evm()) {
		if (board_is_x15_revb1() || board_is_am572x_evm_reva3()) {
			pconf = core_padconf_array_delta_x15_sr2_0;
			pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr2_0);
		} else {
			pconf = core_padconf_array_delta_x15_sr1_1;
			pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr1_1);
		}
		do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
	}

	if (board_is_am571x_idk()) {
		if (am571x_idk_needs_lcd()) {
			pconf = core_padconf_array_vout_am571x_idk;
			pconf_sz = ARRAY_SIZE(core_padconf_array_vout_am571x_idk);
		} else {
			pconf = core_padconf_array_icss1eth_am571x_idk;
			pconf_sz = ARRAY_SIZE(core_padconf_array_icss1eth_am571x_idk);
		}
		do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
	}

	/* Setup IOdelay configuration */
	ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz);
err:
	/* Closeup.. remove isolation */
	__recalibrate_iodelay_end(ret);
}
Ejemplo n.º 4
0
void recalibrate_iodelay(void)
{
	struct pad_conf_entry const *pads, *delta_pads = NULL;
	struct iodelay_cfg_entry const *iodelay;
	int npads, niodelays, delta_npads = 0;
	int ret;

	switch (omap_revision()) {
	case DRA722_ES1_0:
	case DRA722_ES2_0:
		pads = dra72x_core_padconf_array_common;
		npads = ARRAY_SIZE(dra72x_core_padconf_array_common);
		if (board_is_dra72x_revc_or_later()) {
			delta_pads = dra72x_rgmii_padconf_array_revc;
			delta_npads =
				ARRAY_SIZE(dra72x_rgmii_padconf_array_revc);
			iodelay = dra72_iodelay_cfg_array_revc;
			niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revc);
		} else {
			delta_pads = dra72x_rgmii_padconf_array_revb;
			delta_npads =
				ARRAY_SIZE(dra72x_rgmii_padconf_array_revb);
			iodelay = dra72_iodelay_cfg_array_revb;
			niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revb);
		}
		break;
	case DRA752_ES1_0:
	case DRA752_ES1_1:
		pads = dra74x_core_padconf_array;
		npads = ARRAY_SIZE(dra74x_core_padconf_array);
		iodelay = dra742_es1_1_iodelay_cfg_array;
		niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array);
		break;
	default:
	case DRA752_ES2_0:
		pads = dra74x_core_padconf_array;
		npads = ARRAY_SIZE(dra74x_core_padconf_array);
		iodelay = dra742_es2_0_iodelay_cfg_array;
		niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array);
		/* Setup port1 and port2 for rgmii with 'no-id' mode */
		clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK |
				      RGMII1_ID_MODE_N_MASK);
		break;
	}
	/* Setup I/O isolation */
	ret = __recalibrate_iodelay_start();
	if (ret)
		goto err;

	/* Do the muxing here */
	do_set_mux32((*ctrl)->control_padconf_core_base, pads, npads);

	/* Now do the weird minor deltas that should be safe */
	if (delta_npads)
		do_set_mux32((*ctrl)->control_padconf_core_base,
			     delta_pads, delta_npads);

	/* Setup IOdelay configuration */
	ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
err:
	/* Closeup.. remove isolation */
	__recalibrate_iodelay_end(ret);
}
Ejemplo n.º 5
0
Archivo: evm.c Proyecto: Noltari/u-boot
void recalibrate_iodelay(void)
{
	struct pad_conf_entry const *pads, *delta_pads = NULL;
	struct iodelay_cfg_entry const *iodelay;
	int npads, niodelays, delta_npads = 0;
	int ret;

	switch (omap_revision()) {
	case DRA722_ES1_0:
	case DRA722_ES2_0:
	case DRA722_ES2_1:
		pads = dra72x_core_padconf_array_common;
		npads = ARRAY_SIZE(dra72x_core_padconf_array_common);
		if (board_is_dra71x_evm()) {
			pads = dra71x_core_padconf_array;
			npads = ARRAY_SIZE(dra71x_core_padconf_array);
			iodelay = dra71_iodelay_cfg_array;
			niodelays = ARRAY_SIZE(dra71_iodelay_cfg_array);
			/* If SW8 on the EVM is set to enable NAND then
			 * overwrite the pins used by VOUT3 with NAND.
			 */
			if (!nand_sw_detect()) {
				delta_pads = dra71x_nand_padconf_array;
				delta_npads =
					ARRAY_SIZE(dra71x_nand_padconf_array);
			} else {
				delta_pads = dra71x_vout3_padconf_array;
				delta_npads =
					ARRAY_SIZE(dra71x_vout3_padconf_array);
			}

		} else if (board_is_dra72x_revc_or_later()) {
			delta_pads = dra72x_rgmii_padconf_array_revc;
			delta_npads =
				ARRAY_SIZE(dra72x_rgmii_padconf_array_revc);
			iodelay = dra72_iodelay_cfg_array_revc;
			niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revc);
		} else {
			delta_pads = dra72x_rgmii_padconf_array_revb;
			delta_npads =
				ARRAY_SIZE(dra72x_rgmii_padconf_array_revb);
			iodelay = dra72_iodelay_cfg_array_revb;
			niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revb);
		}
		break;
	case DRA752_ES1_0:
	case DRA752_ES1_1:
		pads = dra74x_core_padconf_array;
		npads = ARRAY_SIZE(dra74x_core_padconf_array);
		iodelay = dra742_es1_1_iodelay_cfg_array;
		niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array);
		break;
	case DRA762_ACD_ES1_0:
	case DRA762_ES1_0:
		pads = dra76x_core_padconf_array;
		npads = ARRAY_SIZE(dra76x_core_padconf_array);
		iodelay = dra76x_es1_0_iodelay_cfg_array;
		niodelays = ARRAY_SIZE(dra76x_es1_0_iodelay_cfg_array);
		break;
	default:
	case DRA752_ES2_0:
	case DRA762_ABZ_ES1_0:
		pads = dra74x_core_padconf_array;
		npads = ARRAY_SIZE(dra74x_core_padconf_array);
		iodelay = dra742_es2_0_iodelay_cfg_array;
		niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array);
		/* Setup port1 and port2 for rgmii with 'no-id' mode */
		clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK |
				      RGMII1_ID_MODE_N_MASK);
		break;
	}
	/* Setup I/O isolation */
	ret = __recalibrate_iodelay_start();
	if (ret)
		goto err;

	/* Do the muxing here */
	do_set_mux32((*ctrl)->control_padconf_core_base, pads, npads);

	/* Now do the weird minor deltas that should be safe */
	if (delta_npads)
		do_set_mux32((*ctrl)->control_padconf_core_base,
			     delta_pads, delta_npads);

	if (is_dra76x())
		/* Set mux for MCAN instead of DCAN1 */
		clrsetbits_le32((*ctrl)->control_core_control_spare_rw,
				MCAN_SEL_ALT_MASK, MCAN_SEL);

	/* Setup IOdelay configuration */
	ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
err:
	/* Closeup.. remove isolation */
	__recalibrate_iodelay_end(ret);
}