static void setup_dplls(void) { u32 sysclk_ind, temp; const struct dpll_params *params; debug("setup_dplls\n"); sysclk_ind = get_sys_clk_index(); /* CORE dpll */ params = get_core_dpll_params(); /* default - safest */ /* * Do not lock the core DPLL now. Just set it up. * Core DPLL will be locked after setting up EMIF * using the FREQ_UPDATE method(freq_update_core()) */ do_setup_dpll(&prcm->cm_clkmode_dpll_core, params, DPLL_NO_LOCK); /* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */ temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) | (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) | (CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT); writel(temp, &prcm->cm_clksel_core); debug("Core DPLL configured\n"); /* lock PER dpll */ do_setup_dpll(&prcm->cm_clkmode_dpll_per, &per_dpll_params_1536mhz[sysclk_ind], DPLL_LOCK); debug("PER DPLL locked\n"); /* MPU dpll */ configure_mpu_dpll(); }
static void setup_dplls(void) { u32 temp; const struct dpll_params *params; struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE; debug("setup_dplls\n"); /* CORE dpll */ params = get_core_dpll_params(*dplls_data); /* default - safest */ /* * Do not lock the core DPLL now. Just set it up. * Core DPLL will be locked after setting up EMIF * using the FREQ_UPDATE method(freq_update_core()) */ if (emif_sdram_type(readl(&emif->emif_sdram_config)) == EMIF_SDRAM_TYPE_LPDDR2) do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params, DPLL_NO_LOCK, "core"); else do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params, DPLL_LOCK, "core"); /* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */ temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) | (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) | (CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT); writel(temp, (*prcm)->cm_clksel_core); debug("Core DPLL configured\n"); /* lock PER dpll */ params = get_per_dpll_params(*dplls_data); do_setup_dpll((*prcm)->cm_clkmode_dpll_per, params, DPLL_LOCK, "per"); debug("PER DPLL locked\n"); /* MPU dpll */ configure_mpu_dpll(); #if defined(CONFIG_USB_EHCI_OMAP) || defined(CONFIG_USB_XHCI_OMAP) || \ defined(CONFIG_USB_MUSB_OMAP2PLUS) setup_usb_dpll(); #endif params = get_ddr_dpll_params(*dplls_data); do_setup_dpll((*prcm)->cm_clkmode_dpll_ddrphy, params, DPLL_LOCK, "ddr"); #ifdef CONFIG_DRIVER_TI_CPSW params = get_gmac_dpll_params(*dplls_data); do_setup_dpll((*prcm)->cm_clkmode_dpll_gmac, params, DPLL_LOCK, "gmac"); #endif }
void am33xx_spl_board_init(void) { struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; /* Get the frequency */ dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); /* Set CORE Frequencies to OPP100 */ do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); /* Set MPU Frequency to what we detected now that voltages are set */ do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); }
void am33xx_spl_board_init(void) { /* debug print detect status */ (void)get_board_type(true); /* Get the frequency */ /* dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); */ dpll_mpu_opp100.m = MPUPLL_M_1000; if (i2c_probe(TPS65217_CHIP_PM)) return; /* Set the USB Current Limit */ if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_POWER_PATH, TPS65217_USB_INPUT_CUR_LIMIT_1800MA, TPS65217_USB_INPUT_CUR_LIMIT_MASK)) puts("! tps65217_reg_write: could not set USB limit\n"); /* Set the Core Voltage (DCDC3) to 1.125V */ if (tps65217_voltage_update(TPS65217_DEFDCDC3, TPS65217_DCDC_VOLT_SEL_1125MV)) { puts("! tps65217_reg_write: could not set Core Voltage\n"); return; } /* Set CORE Frequencies to OPP100 */ do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); /* Set the MPU Voltage (DCDC2) */ if (tps65217_voltage_update(TPS65217_DEFDCDC2, TPS65217_DCDC_VOLT_SEL_1325MV)) { puts("! tps65217_reg_write: could not set MPU Voltage\n"); return; } /* * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone. * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black. */ if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFLS1, TPS65217_LDO_VOLTAGE_OUT_1_8, TPS65217_LDO_MASK)) puts("! tps65217_reg_write: could not set LDO3\n"); if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFLS2, TPS65217_LDO_VOLTAGE_OUT_3_3, TPS65217_LDO_MASK)) puts("! tps65217_reg_write: could not set LDO4\n"); /* Set MPU Frequency to what we detected now that voltages are set */ do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); }
static int conf_disp_pll(int m, int n) { struct cm_perpll *cmper = (struct cm_perpll *)CM_PER; struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1}; #if defined(DISPL_PLL_SPREAD_SPECTRUM) struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP; #endif u32 *const clk_domains[] = { &cmper->lcdclkctrl, 0 }; u32 *const clk_modules_explicit_en[] = { &cmper->lcdclkctrl, &cmper->lcdcclkstctrl, &cmper->spi1clkctrl, 0 }; do_enable_clocks(clk_domains, clk_modules_explicit_en, 1); do_setup_dpll(&dpll_lcd_regs, &dpll_lcd); #if defined(DISPL_PLL_SPREAD_SPECTRUM) writel(0x64, &cmwkup->resv6[3]); /* 0x50 */ writel(0x800, &cmwkup->resv6[2]); /* 0x4c */ writel(readl(&cmwkup->clkmoddplldisp) | CM_CLKMODE_DPLL_SSC_EN_MASK, &cmwkup->clkmoddplldisp); /* 0x98 */ #endif return 0; }
/* * Lock MPU dpll * * Resulting MPU frequencies: * 4430 ES1.0 : 600 MHz * 4430 ES2.x : 792 MHz (OPP Turbo) * 4460 : 920 MHz (OPP Turbo) - DCC disabled */ void configure_mpu_dpll(void) { const struct dpll_params *params; struct dpll_regs *mpu_dpll_regs; u32 omap_rev; omap_rev = omap_revision(); /* * DCC and clock divider settings for 4460. * DCC is required, if more than a certain frequency is required. * For, 4460 > 1GHZ. * 5430 > 1.4GHZ. */ if ((omap_rev >= OMAP4460_ES1_0) && (omap_rev < OMAP5430_ES1_0)) { mpu_dpll_regs = (struct dpll_regs *)((*prcm)->cm_clkmode_dpll_mpu); bypass_dpll((*prcm)->cm_clkmode_dpll_mpu); clrbits_le32((*prcm)->cm_mpu_mpu_clkctrl, MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK); setbits_le32((*prcm)->cm_mpu_mpu_clkctrl, MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK); clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll, CM_CLKSEL_DCC_EN_MASK); } params = get_mpu_dpll_params(*dplls_data); do_setup_dpll((*prcm)->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu"); debug("MPU DPLL locked\n"); }
static void setup_usb_dpll(void) { const struct dpll_params *params; u32 sys_clk_khz, sd_div, num, den; sys_clk_khz = get_sys_clk_freq() / 1000; /* * USB: * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250) * - where CLKINP is sys_clk in MHz * Use CLKINP in KHz and adjust the denominator accordingly so * that we have enough accuracy and at the same time no overflow */ params = get_usb_dpll_params(*dplls_data); num = params->m * sys_clk_khz; den = (params->n + 1) * 250 * 1000; num += den - 1; sd_div = num / den; clrsetbits_le32((*prcm)->cm_clksel_dpll_usb, CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK, sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT); /* Now setup the dpll with the regular function */ do_setup_dpll((*prcm)->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb"); }
/* * Lock MPU dpll * * Resulting MPU frequencies: * 4430 ES1.0 : 600 MHz * 4430 ES2.x : 792 MHz (OPP Turbo) * 4460 : 920 MHz (OPP Turbo) - DCC disabled */ void configure_mpu_dpll(void) { const struct dpll_params *params; struct dpll_regs *mpu_dpll_regs; u32 omap4_rev, sysclk_ind; omap4_rev = omap_revision(); sysclk_ind = get_sys_clk_index(); if (omap4_rev == OMAP4430_ES1_0) params = &mpu_dpll_params_1200mhz[sysclk_ind]; else if (omap4_rev < OMAP4460_ES1_0) params = &mpu_dpll_params_1584mhz[sysclk_ind]; else params = &mpu_dpll_params_1840mhz[sysclk_ind]; /* DCC and clock divider settings for 4460 */ if (omap4_rev >= OMAP4460_ES1_0) { mpu_dpll_regs = (struct dpll_regs *)&prcm->cm_clkmode_dpll_mpu; bypass_dpll(&prcm->cm_clkmode_dpll_mpu); clrbits_le32(&prcm->cm_mpu_mpu_clkctrl, MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK); setbits_le32(&prcm->cm_mpu_mpu_clkctrl, MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK); clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll, CM_CLKSEL_DCC_EN_MASK); } do_setup_dpll(&prcm->cm_clkmode_dpll_mpu, params, DPLL_LOCK); debug("MPU DPLL locked\n"); }
static void setup_dplls(void) { const struct dpll_params *params; params = get_dpll_core_params(); do_setup_dpll(&dpll_core_regs, params); params = get_dpll_mpu_params(); do_setup_dpll(&dpll_mpu_regs, params); params = get_dpll_per_params(); do_setup_dpll(&dpll_per_regs, params); writel(0x300, &cmwkup->clkdcoldodpllper); params = get_dpll_ddr_params(); do_setup_dpll(&dpll_ddr_regs, params); }
static void setup_non_essential_dplls(void) { u32 abe_ref_clk; const struct dpll_params *params; /* IVA */ clrsetbits_le32((*prcm)->cm_bypclk_dpll_iva, CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2); params = get_iva_dpll_params(*dplls_data); do_setup_dpll((*prcm)->cm_clkmode_dpll_iva, params, DPLL_LOCK, "iva"); /* Configure ABE dpll */ params = get_abe_dpll_params(*dplls_data); #ifdef CONFIG_SYS_OMAP_ABE_SYSCK abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK; if (omap_revision() == DRA752_ES1_0) /* Select the sys clk for dpll_abe */ clrsetbits_le32((*prcm)->cm_abe_pll_sys_clksel, CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK, CM_ABE_PLL_SYS_CLKSEL_SYSCLK2); #else abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK; /* * We need to enable some additional options to achieve * 196.608MHz from 32768 Hz */ setbits_le32((*prcm)->cm_clkmode_dpll_abe, CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK| CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK| CM_CLKMODE_DPLL_LPMODE_EN_MASK| CM_CLKMODE_DPLL_REGM4XEN_MASK); /* Spend 4 REFCLK cycles at each stage */ clrsetbits_le32((*prcm)->cm_clkmode_dpll_abe, CM_CLKMODE_DPLL_RAMP_RATE_MASK, 1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT); #endif /* Select the right reference clk */ clrsetbits_le32((*prcm)->cm_abe_pll_ref_clksel, CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK, abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT); /* Lock the dpll */ do_setup_dpll((*prcm)->cm_clkmode_dpll_abe, params, DPLL_LOCK, "abe"); }
static void setup_dplls(void) { const struct dpll_params *params; params = get_dpll_core_params(); do_setup_dpll(&dpll_core_regs, params); params = get_dpll_mpu_params(); do_setup_dpll(&dpll_mpu_regs, params); params = get_dpll_per_params(); do_setup_dpll(&dpll_per_regs, params); writel(0x300, &cmwkup->clkdcoldodpllper); params = get_dpll_ddr_params(); printf(">>> %s vor do_setup_dpll\n", __func__); do_setup_dpll(&dpll_ddr_regs, params); printf(">>> %s nach do_setup_dpll\n", __func__); }
void am33xx_spl_board_init(void) { /* * The pengwyn board uses the TPS650250 PMIC without I2C * interface and will output the following fixed voltages: * DCDC1=3V3 (IO) DCDC2=1V5 (DDR) DCDC3=1V26 (Vmpu) * VLDO1=1V8 (IO) VLDO2=1V8(IO) * Vcore=1V1 is fixed, generated by TPS62231 */ /* Get the frequency */ dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); /* Set CORE Frequencies to OPP100 */ do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); /* 720MHz cpu, this might change on newer board revisions */ dpll_mpu_opp100.m = MPUPLL_M_720; do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); }
static int conf_disp_pll(int m, int n) { struct cm_perpll *cmper = (struct cm_perpll *)CM_PER; struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL; struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1}; u32 *const clk_domains[] = { &cmper->lcdclkctrl, 0 }; u32 *const clk_modules_explicit_en[] = { &cmper->lcdclkctrl, &cmper->lcdcclkstctrl, &cmper->epwmss0clkctrl, 0 }; do_enable_clocks(clk_domains, clk_modules_explicit_en, 1); writel(0x0, &cmdpll->clklcdcpixelclk); do_setup_dpll(&dpll_lcd_regs, &dpll_lcd); return 0; }
void am33xx_spl_board_init(void) { struct am335x_baseboard_id header; int mpu_vdd; puts("am33xx_spl_board_init \n"); if (read_eeprom(&header) < 0) puts("Could not get board ID.\n"); /* Get the frequency */ dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); if (board_is_bone(&header) || board_is_bone_lt(&header)) { /* BeagleBone PMIC Code */ int usb_cur_lim; /* * Only perform PMIC configurations if board rev > A1 * on Beaglebone White */ //if (board_is_bone(&header) && !strncmp(header.version, // "00A1", 4)) // return; //if (i2c_probe(TPS65217_CHIP_PM)) // return; /* * On Beaglebone White we need to ensure we have AC power * before increasing the frequency. */ /* if (board_is_bone(&header)) { uchar pmic_status_reg; if (tps65217_reg_read(TPS65217_STATUS, &pmic_status_reg)) return; if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) { puts("No AC power, disabling frequency switch\n"); return; } }*/ /* * Override what we have detected since we know if we have * a Beaglebone Black it supports 1GHz. */ // if (board_is_bone_lt(&header)) dpll_mpu_opp100.m = MPUPLL_M_1000; /* * Increase USB current limit to 1300mA or 1800mA and set * the MPU voltage controller as needed. */ // if (dpll_mpu_opp100.m == MPUPLL_M_1000) { // usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; // mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV; // } else { // usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA; // mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV; // } // if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, // TPS65217_POWER_PATH, // usb_cur_lim, // TPS65217_USB_INPUT_CUR_LIMIT_MASK)) // puts("tps65217_reg_write failure\n"); /* Set DCDC3 (CORE) voltage to 1.125V */ // if (tps65217_voltage_update(TPS65217_DEFDCDC3, // TPS65217_DCDC_VOLT_SEL_1125MV)) { // puts("tps65217_voltage_update failure\n"); // return; // } /* Set CORE Frequencies to OPP100 */ do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); /* Set DCDC2 (MPU) voltage */ // if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) { // puts("tps65217_voltage_update failure\n"); // return; // } /* * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone. * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black. */ // if (board_is_bone(&header)) { // if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, // TPS65217_DEFLS1, // TPS65217_LDO_VOLTAGE_OUT_3_3, // TPS65217_LDO_MASK)) // puts("tps65217_reg_write failure\n"); // } else { /// if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, // TPS65217_DEFLS1, // TPS65217_LDO_VOLTAGE_OUT_1_8, // TPS65217_LDO_MASK)) // puts("tps65217_reg_write failure\n"); // } // /// if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, // TPS65217_DEFLS2, // TPS65217_LDO_VOLTAGE_OUT_3_3, // TPS65217_LDO_MASK)) // puts("tps65217_reg_write failure\n"); } else { int sil_rev; /* * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all * MPU frequencies we support we use a CORE voltage of * 1.1375V. For MPU voltage we need to switch based on * the frequency we are running at. */ // if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) // return; /* * Depending on MPU clock and PG we will need a different * VDD to drive at that speed. */ // sil_rev = readl(&cdev->deviceid) >> 28; // mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, // dpll_mpu_opp100.m); // /* Tell the TPS65910 to use i2c */ // tps65910_set_i2c_control(); /* First update MPU voltage. */ // if (tps65910_voltage_update(MPU, mpu_vdd)) // return; /* Second, update the CORE voltage. */ // if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3)) // return; /* Set CORE Frequencies to OPP100 */ // do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); } /* Set MPU Frequency to what we detected now that voltages are set */ do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); puts("spl_board_init end \n"); }
void am33xx_spl_board_init(void) { struct am335x_baseboard_id header; int mpu_vdd; if (read_eeprom(&header) < 0) { puts("Wrong data in EEPROM.\n"); hang(); } if (!board_is_kalitap(&header) && !board_is_luna(&header) && !board_is_catchwire(&header)) { puts("Could not get board ID (CatchWire/KaliTAP).\n"); hang(); } /* Get the frequency */ dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); /* BeagleBone and NEWT PMIC Code */ int usb_cur_lim; if (i2c_probe(TPS65217_CHIP_PM)) return; /* * Override what we have detected since we know we have * a CatchWire/KaliTAP that supports 1GHz. */ dpll_mpu_opp100.m = MPUPLL_M_1000; /* * Increase USB current limit to 1300mA or 1800mA and set * the MPU voltage controller as needed. */ if (dpll_mpu_opp100.m == MPUPLL_M_1000) { usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV; puts("tps65217_reg_write USB_INPUT_CUR_LIMIT_1800MA\n"); } else { usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA; mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV; puts("tps65217_reg_write USB_INPUT_CUR_LIMIT_1300MA\n"); } if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_POWER_PATH, usb_cur_lim, TPS65217_USB_INPUT_CUR_LIMIT_MASK)) { puts("tps65217_reg_write POWER_PATH failure\n"); } else { uchar pmic_power_path_reg = 0; puts("tps65217_reg_write POWER_PATH success\n"); tps65217_reg_read(TPS65217_POWER_PATH, &pmic_power_path_reg); printf("POWER_PATH : 0%02X\n", pmic_power_path_reg); } /* Set DCDC3 (CORE) voltage to 1.125V */ if (tps65217_voltage_update(TPS65217_DEFDCDC3, TPS65217_DCDC_VOLT_SEL_1125MV)) { puts("tps65217_voltage_update failure\n"); return; } /* Set CORE Frequencies to OPP100 */ do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); /* Set DCDC2 (MPU) voltage */ if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) { puts("tps65217_voltage_update failure\n"); return; } else { puts("tps65217_voltage_update success\n"); } /* * Set LDO3 to 1.8V and LDO4 to 3.3V for CatchWire/KaliTAP. */ if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFLS1, TPS65217_LDO_VOLTAGE_OUT_1_8, TPS65217_LDO_MASK)) puts("tps65217_reg_write failure\n"); if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFLS2, TPS65217_LDO_VOLTAGE_OUT_3_3, TPS65217_LDO_MASK)) puts("tps65217_reg_write failure\n"); /* Set MPU Frequency to what we detected now that voltages are set */ do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); }
/* * This function is the place to do per-board things such as ramp up the * MPU clock frequency. */ __weak void am33xx_spl_board_init(void) { do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); }
void am33xx_spl_board_init(void) { int mpu_vdd; /* Get the frequency */ dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); /* BeagleBone PMIC Code */ int usb_cur_lim; if (i2c_probe(TPS65217_CHIP_PM)) return; /* * Override what we have detected since we know if we have * a Beaglebone Black it supports 1GHz. */ dpll_mpu_opp100.m = MPUPLL_M_1000; /* * Increase USB current limit to 1300mA or 1800mA and set * the MPU voltage controller as needed. */ usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV; if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_POWER_PATH, usb_cur_lim, TPS65217_USB_INPUT_CUR_LIMIT_MASK)) puts("tps65217_reg_write failure\n"); /* Set DCDC3 (CORE) voltage to 1.125V */ if (tps65217_voltage_update(TPS65217_DEFDCDC3, TPS65217_DCDC_VOLT_SEL_1125MV)) { puts("tps65217_voltage_update failure\n"); return; } /* Set CORE Frequencies to OPP100 */ do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); /* Set DCDC2 (MPU) voltage */ if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) { puts("tps65217_voltage_update failure\n"); return; } /* * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black. */ if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFLS1, TPS65217_LDO_VOLTAGE_OUT_1_8, TPS65217_LDO_MASK)) puts("tps65217_reg_write failure\n"); if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFLS2, TPS65217_LDO_VOLTAGE_OUT_3_3, TPS65217_LDO_MASK)) puts("tps65217_reg_write failure\n"); /* Set MPU Frequency to what we detected now that voltages are set */ do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); }
static void setup_non_essential_dplls(void) { u32 sys_clk_khz, abe_ref_clk; u32 sysclk_ind, sd_div, num, den; const struct dpll_params *params; sysclk_ind = get_sys_clk_index(); sys_clk_khz = get_sys_clk_freq() / 1000; /* IVA */ clrsetbits_le32(&prcm->cm_bypclk_dpll_iva, CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2); do_setup_dpll(&prcm->cm_clkmode_dpll_iva, &iva_dpll_params_1862mhz[sysclk_ind], DPLL_LOCK); /* * USB: * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250) * - where CLKINP is sys_clk in MHz * Use CLKINP in KHz and adjust the denominator accordingly so * that we have enough accuracy and at the same time no overflow */ params = &usb_dpll_params_1920mhz[sysclk_ind]; num = params->m * sys_clk_khz; den = (params->n + 1) * 250 * 1000; num += den - 1; sd_div = num / den; clrsetbits_le32(&prcm->cm_clksel_dpll_usb, CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK, sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT); /* Now setup the dpll with the regular function */ do_setup_dpll(&prcm->cm_clkmode_dpll_usb, params, DPLL_LOCK); #ifdef CONFIG_SYS_OMAP4_ABE_SYSCK params = &abe_dpll_params_sysclk_196608khz[sysclk_ind]; abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK; #else params = &abe_dpll_params_32k_196608khz; abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK; /* * We need to enable some additional options to achieve * 196.608MHz from 32768 Hz */ setbits_le32(&prcm->cm_clkmode_dpll_abe, CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK| CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK| CM_CLKMODE_DPLL_LPMODE_EN_MASK| CM_CLKMODE_DPLL_REGM4XEN_MASK); /* Spend 4 REFCLK cycles at each stage */ clrsetbits_le32(&prcm->cm_clkmode_dpll_abe, CM_CLKMODE_DPLL_RAMP_RATE_MASK, 1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT); #endif /* Select the right reference clk */ clrsetbits_le32(&prcm->cm_abe_pll_ref_clksel, CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK, abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT); /* Lock the dpll */ do_setup_dpll(&prcm->cm_clkmode_dpll_abe, params, DPLL_LOCK); }
void pmicsetup(u32 mpupll) { int mpu_vdd; int usb_cur_lim; if (i2c_probe(TPS65217_CHIP_PM)) { puts("PMIC (0x24) not found! skip further initalization.\n"); return; } /* Get the frequency which is defined by device fuses */ dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); printf("detected max. frequency: %d - ", dpll_mpu_opp100.m); if (0 != mpupll) { dpll_mpu_opp100.m = MPUPLL_M_1000; printf("retuning MPU-PLL to: %d MHz.\n", dpll_mpu_opp100.m); } else { puts("ok.\n"); } /* * Increase USB current limit to 1300mA or 1800mA and set * the MPU voltage controller as needed. */ if (dpll_mpu_opp100.m == MPUPLL_M_1000) { usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV; } else { usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA; mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV; } if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_POWER_PATH, usb_cur_lim, TPS65217_USB_INPUT_CUR_LIMIT_MASK)) puts("tps65217_reg_write failure\n"); /* Set DCDC3 (CORE) voltage to 1.125V */ if (tps65217_voltage_update(TPS65217_DEFDCDC3, TPS65217_DCDC_VOLT_SEL_1125MV)) { puts("tps65217_voltage_update failure\n"); return; } /* Set CORE Frequencies to OPP100 */ do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); /* Set DCDC2 (MPU) voltage */ if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) { puts("tps65217_voltage_update failure\n"); return; } /* Set LDO3 to 1.8V */ if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFLS1, TPS65217_LDO_VOLTAGE_OUT_1_8, TPS65217_LDO_MASK)) puts("tps65217_reg_write failure\n"); /* Set LDO4 to 3.3V */ if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFLS2, TPS65217_LDO_VOLTAGE_OUT_3_3, TPS65217_LDO_MASK)) puts("tps65217_reg_write failure\n"); /* Set MPU Frequency to what we detected now that voltages are set */ do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); /* Set PWR_EN bit in Status Register */ tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_STATUS, TPS65217_PWR_OFF, TPS65217_PWR_OFF); }