static void draw_concat_vec4(ivl_expr_t expr)
{
/* Repeat the concatenation this many times to make a
super-concatenation. */
unsigned repeat = ivl_expr_repeat(expr);
/* This is the number of expressions that go into the
concatenation. */
unsigned num_sube = ivl_expr_parms(expr);
unsigned sub_idx;
assert(num_sube > 0);
/* Start with the most-significant bits. */
draw_eval_vec4(ivl_expr_parm(expr, 0));
for (sub_idx = 1 ; sub_idx < num_sube ; sub_idx += 1) {
/* Concatenate progressively lower parts. */
ivl_expr_t sube = ivl_expr_parm(expr, sub_idx);
/* Special case: The next expression is a NUMBER that
can be concatenated using %concati/vec4
instructions. */
if (ivl_expr_type(sube) == IVL_EX_NUMBER) {
draw_concat_number_vec4(sube, 1);
continue;
}
draw_eval_vec4(sube);
fprintf(vvp_out, " %%concat/vec4; draw_concat_vec4\n");
}
if (repeat > 1) {
fprintf(vvp_out, " %%replicate %u;\n", repeat);
}
}
static void draw_binary_vec4_bitwise(ivl_expr_t expr)
{
draw_eval_vec4(ivl_expr_oper1(expr));
draw_eval_vec4(ivl_expr_oper2(expr));
switch (ivl_expr_opcode(expr)) {
case '&':
fprintf(vvp_out, " %%and;\n");
break;
case '|':
fprintf(vvp_out, " %%or;\n");
break;
case '^':
fprintf(vvp_out, " %%xor;\n");
break;
case 'A': /* ~& */
fprintf(vvp_out, " %%nand;\n");
break;
case 'O': /* ~| */
fprintf(vvp_out, " %%nor;\n");
break;
case 'X': /* ~^ */
fprintf(vvp_out, " %%xnor;\n");
break;
default:
assert(0);
break;
}
}
static void draw_select_vec4(ivl_expr_t expr)
{
// This is the sub-expression to part-select.
ivl_expr_t subexpr = ivl_expr_oper1(expr);
// This is the base of the part select
ivl_expr_t base = ivl_expr_oper2(expr);
// This is the part select width
unsigned wid = ivl_expr_width(expr);
// Is the select base expression signed or unsigned?
char sign_suff = ivl_expr_signed(base)? 's' : 'u';
// Special Case: If the sub-expression is a STRING, then this
// is a select from that string.
if (ivl_expr_value(subexpr)==IVL_VT_STRING) {
assert(base);
assert(wid==8);
draw_eval_string(subexpr);
int base_idx = allocate_word();
draw_eval_expr_into_integer(base, base_idx);
fprintf(vvp_out, " %%substr/vec4 %d, %u;\n", base_idx, wid);
fprintf(vvp_out, " %%pop/str 1;\n");
clr_word(base_idx);
return;
}
if (ivl_expr_value(subexpr)==IVL_VT_DARRAY) {
ivl_signal_t sig = ivl_expr_signal(subexpr);
assert(sig);
assert( (ivl_signal_data_type(sig)==IVL_VT_DARRAY)
|| (ivl_signal_data_type(sig)==IVL_VT_QUEUE) );
assert(base);
draw_eval_expr_into_integer(base, 3);
fprintf(vvp_out, " %%load/dar/vec4 v%p_0;\n", sig);
return;
}
if (test_immediate_vec4_ok(base)) {
unsigned long val0, valx;
unsigned base_wid;
make_immediate_vec4_words(base, &val0, &valx, &base_wid);
assert(valx == 0);
draw_eval_vec4(subexpr);
fprintf(vvp_out, " %%parti/%c %u, %lu, %u;\n",
sign_suff, wid, val0, base_wid);
} else {
draw_eval_vec4(subexpr);
draw_eval_vec4(base);
fprintf(vvp_out, " %%part/%c %u;\n", sign_suff, wid);
}
}
static void draw_binary_vec4_lrs(ivl_expr_t expr)
{
ivl_expr_t le = ivl_expr_oper1(expr);
ivl_expr_t re = ivl_expr_oper2(expr);
// Push the left expression onto the stack.
draw_eval_vec4(le);
// Calculate the shift amount into an index register.
int use_index_reg = allocate_word();
assert(use_index_reg >= 0);
draw_eval_expr_into_integer(re, use_index_reg);
// Emit the actual shift instruction. This will pop the top of
// the stack and replace it with the result of the shift.
switch (ivl_expr_opcode(expr)) {
case 'l': /* << */
fprintf(vvp_out, " %%shiftl %d;\n", use_index_reg);
break;
case 'r': /* >> */
fprintf(vvp_out, " %%shiftr %d;\n", use_index_reg);
break;
case 'R': /* >>> */
if (ivl_expr_signed(le))
fprintf(vvp_out, " %%shiftr/s %d;\n", use_index_reg);
else
fprintf(vvp_out, " %%shiftr %d;\n", use_index_reg);
break;
default:
assert(0);
break;
}
clr_word(use_index_reg);
}
static void draw_ternary_vec4(ivl_expr_t expr)
{
ivl_expr_t cond = ivl_expr_oper1(expr);
ivl_expr_t true_ex = ivl_expr_oper2(expr);
ivl_expr_t false_ex = ivl_expr_oper3(expr);
unsigned lab_true = local_count++;
unsigned lab_out = local_count++;
int use_flag = draw_eval_condition(cond);
/* The condition flag is used after possibly other statements,
so we need to put it into a non-common place. Allocate a
safe flag bit and move the condition to the flag position. */
if (use_flag < 8) {
int tmp_flag = allocate_flag();
assert(tmp_flag >= 8);
fprintf(vvp_out, " %%flag_mov %d, %d;\n", tmp_flag, use_flag);
use_flag = tmp_flag;
}
fprintf(vvp_out, " %%jmp/0 T_%u.%u, %d;\n", thread_count, lab_true, use_flag);
/* If the condition is true or xz (not false), we need the true
expression. If the condition is true, then we ONLY need the
true expression. */
draw_eval_vec4(true_ex);
fprintf(vvp_out, " %%jmp/1 T_%u.%u, %d;\n", thread_count, lab_out, use_flag);
fprintf(vvp_out, "T_%u.%u ; End of true expr.\n", thread_count, lab_true);
/* If the condition is false or xz (not true), we need the false
expression. If the condition is false, then we ONLY need
the false expression. */
draw_eval_vec4(false_ex);
fprintf(vvp_out, " %%jmp/0 T_%u.%u, %d;\n", thread_count, lab_out, use_flag);
fprintf(vvp_out, " ; End of false expr.\n");
/* Here, the condition is not true or false, it is xz. Both
the true and false expressions have been pushed onto the
stack, we just need to blend the bits. */
fprintf(vvp_out, " %%blend;\n");
fprintf(vvp_out, "T_%u.%u;\n", thread_count, lab_out);
clr_flag(use_flag);
}
static void draw_binary_vec4_lor(ivl_expr_t expr)
{
ivl_expr_t le = ivl_expr_oper1(expr);
ivl_expr_t re = ivl_expr_oper2(expr);
/* Push the left expression. Reduce it to a single bit if
necessary. */
draw_eval_vec4(le);
if (ivl_expr_width(le) > 1)
fprintf(vvp_out, " %%or/r;\n");
/* Now push the right expression. Again, reduce to a single
bit if necessary. */
draw_eval_vec4(re);
if (ivl_expr_width(re) > 1)
fprintf(vvp_out, " %%or/r;\n");
fprintf(vvp_out, " %%or;\n");
if (ivl_expr_width(expr) > 1)
fprintf(vvp_out, " %%pad/u %u;\n", ivl_expr_width(expr));
}
/*
* This function handles the special case that we assign an array
* pattern to a dynamic array. Handle this by assigning each
* element. The array pattern will have a fixed size.
*/
static int show_stmt_assign_darray_pattern(ivl_statement_t net)
{
int errors = 0;
ivl_lval_t lval = ivl_stmt_lval(net, 0);
ivl_expr_t rval = ivl_stmt_rval(net);
ivl_signal_t var= ivl_lval_sig(lval);
ivl_type_t var_type= ivl_signal_net_type(var);
assert(ivl_type_base(var_type) == IVL_VT_DARRAY);
ivl_type_t element_type = ivl_type_element(var_type);
unsigned idx;
#if 0
unsigned element_width = 1;
if (ivl_type_base(element_type) == IVL_VT_BOOL)
element_width = width_of_packed_type(element_type);
else if (ivl_type_base(element_type) == IVL_VT_LOGIC)
element_width = width_of_packed_type(element_type);
#endif
assert(ivl_expr_type(rval) == IVL_EX_ARRAY_PATTERN);
for (idx = 0 ; idx < ivl_expr_parms(rval) ; idx += 1) {
switch (ivl_type_base(element_type)) {
case IVL_VT_BOOL:
case IVL_VT_LOGIC:
draw_eval_vec4(ivl_expr_parm(rval,idx));
fprintf(vvp_out, " %%ix/load 3, %u, 0;\n", idx);
fprintf(vvp_out, " %%store/dar/vec4 v%p_0;\n", var);
break;
case IVL_VT_REAL:
draw_eval_real(ivl_expr_parm(rval,idx));
fprintf(vvp_out, " %%ix/load 3, %u, 0;\n", idx);
fprintf(vvp_out, " %%store/dar/r v%p_0;\n", var);
break;
case IVL_VT_STRING:
draw_eval_string(ivl_expr_parm(rval,idx));
fprintf(vvp_out, " %%ix/load 3, %u, 0;\n", idx);
fprintf(vvp_out, " %%store/dar/str v%p_0;\n", var);
break;
default:
fprintf(vvp_out, "; ERROR: show_stmt_assign_darray_pattern: type_base=%d not implemented\n", ivl_type_base(element_type));
errors += 1;
break;
}
}
return errors;
}
static int draw_condition_fallback(ivl_expr_t expr)
{
int use_flag = allocate_flag();
/* Evaluate the condition expression, including optionally
reducing it to a single bit. Put the result into a flag bit
for use by all the tests. */
draw_eval_vec4(expr);
if (ivl_expr_width(expr) > 1)
fprintf(vvp_out, " %%or/r;\n");
fprintf(vvp_out, " %%flag_set/vec4 %d;\n", use_flag);
return use_flag;
}
static void function_argument_logic(ivl_signal_t port, ivl_expr_t expr)
{
unsigned ewidth, pwidth;
/* ports cannot be arrays. */
assert(ivl_signal_dimensions(port) == 0);
ewidth = ivl_expr_width(expr);
pwidth = ivl_signal_width(port);
draw_eval_vec4(expr);
if (ewidth < pwidth)
fprintf(vvp_out, " %%pad/u %u;\n", pwidth);
}
static int show_stmt_assign_sig_string(ivl_statement_t net)
{
ivl_lval_t lval = ivl_stmt_lval(net, 0);
ivl_expr_t rval = ivl_stmt_rval(net);
ivl_expr_t part = ivl_lval_part_off(lval);
ivl_expr_t aidx = ivl_lval_idx(lval);
ivl_signal_t var= ivl_lval_sig(lval);
assert(ivl_stmt_lvals(net) == 1);
assert(ivl_stmt_opcode(net) == 0);
/* Simplest case: no mux. Evaluate the r-value as a string and
store the result into the variable. Note that the
%store/str opcode pops the string result. */
if (part == 0 && aidx == 0) {
draw_eval_string(rval);
fprintf(vvp_out, " %%store/str v%p_0;\n", var);
return 0;
}
/* Assign to array. The l-value has an index expression
expression so we are assigning to an array word. */
if (aidx != 0) {
unsigned ix;
assert(part == 0);
draw_eval_string(rval);
draw_eval_expr_into_integer(aidx, (ix = allocate_word()));
fprintf(vvp_out, " %%store/stra v%p, %u;\n", var, ix);
clr_word(ix);
return 0;
}
assert(ivl_expr_width(rval)==8);
draw_eval_vec4(rval);
/* Calculate the character select for the word. */
int mux_word = allocate_word();
draw_eval_expr_into_integer(part, mux_word);
fprintf(vvp_out, " %%putc/str/vec4 v%p_0, %d;\n", var, mux_word);
clr_word(mux_word);
return 0;
}
static void draw_unary_inc_dec(ivl_expr_t sub, bool incr, bool pre)
{
ivl_signal_t sig = 0;
unsigned wid = 0;
switch (ivl_expr_type(sub)) {
case IVL_EX_SELECT: {
ivl_expr_t e1 = ivl_expr_oper1(sub);
sig = ivl_expr_signal(e1);
wid = ivl_expr_width(e1);
break;
}
case IVL_EX_SIGNAL:
sig = ivl_expr_signal(sub);
wid = ivl_expr_width(sub);
break;
default:
assert(0);
break;
}
draw_eval_vec4(sub);
const char*cmd = incr? "%add" : "%sub";
if (pre) {
/* prefix means we add the result first, and store the
result, as well as leaving a copy on the stack. */
fprintf(vvp_out, " %%pushi/vec4 1, 0, %u;\n", wid);
fprintf(vvp_out, " %s;\n", cmd);
fprintf(vvp_out, " %%dup/vec4;\n");
fprintf(vvp_out, " %%store/vec4 v%p_0, 0, %u;\n", sig, wid);
} else {
/* The post-fix decrement returns the non-decremented
version, so there is a slight re-arrange. */
fprintf(vvp_out, " %%dup/vec4;\n");
fprintf(vvp_out, " %%pushi/vec4 1, 0, %u;\n", wid);
fprintf(vvp_out, " %s;\n", cmd);
fprintf(vvp_out, " %%store/vec4 v%p_0, 0, %u;\n", sig, wid);
}
}
static void draw_select_pad_vec4(ivl_expr_t expr)
{
// This is the sub-expression to pad/truncate
ivl_expr_t subexpr = ivl_expr_oper1(expr);
// This is the target width of the expression
unsigned wid = ivl_expr_width(expr);
// Push the sub-expression onto the stack.
draw_eval_vec4(subexpr);
// Special case: The expression is already the correct width,
// so there is nothing to be done.
if (wid == ivl_expr_width(subexpr))
return;
if (ivl_expr_signed(expr))
fprintf(vvp_out, " %%pad/s %u;\n", wid);
else
fprintf(vvp_out, " %%pad/u %u;\n", wid);
}
static int show_stmt_assign_vector(ivl_statement_t net)
{
ivl_expr_t rval = ivl_stmt_rval(net);
//struct vector_info res;
//struct vector_info lres = {0, 0};
struct vec_slice_info*slices = 0;
int idx_reg;
/* If this is a compressed assignment, then get the contents
of the l-value. We need these values as part of the r-value
calculation. */
if (ivl_stmt_opcode(net) != 0) {
slices = calloc(ivl_stmt_lvals(net), sizeof(struct vec_slice_info));
get_vec_from_lval(net, slices);
}
/* Handle the special case that the expression is a real
value. Evaluate the real expression, then convert the
result to a vector. Then store that vector into the
l-value. */
if (ivl_expr_value(rval) == IVL_VT_REAL) {
draw_eval_real(rval);
/* This is the accumulated with of the l-value of the
assignment. */
unsigned wid = ivl_stmt_lwidth(net);
/* Convert a calculated real value to a vec4 value of
the given width. We need to include the width of the
result because real values to not have any inherit
width. The real value will be popped, and a vec4
value pushed. */
fprintf(vvp_out, " %%cvt/vr %u;\n", wid);
} else if (ivl_expr_value(rval) == IVL_VT_STRING) {
/* Special case: vector to string casting */
ivl_lval_t lval = ivl_stmt_lval(net, 0);
fprintf(vvp_out, " %%vpi_call %u %u \"$ivl_string_method$to_vec\", v%p_0, v%p_0 {0 0 0};\n",
ivl_file_table_index(ivl_stmt_file(net)), ivl_stmt_lineno(net),
ivl_expr_signal(rval), ivl_lval_sig(lval));
return 0;
} else {
unsigned wid = ivl_stmt_lwidth(net);
draw_eval_vec4(rval);
resize_vec4_wid(rval, wid);
}
switch (ivl_stmt_opcode(net)) {
case 0:
store_vec4_to_lval(net);
break;
case '+':
fprintf(vvp_out, " %%add;\n");
put_vec_to_lval(net, slices);
break;
case '-':
fprintf(vvp_out, " %%sub;\n");
put_vec_to_lval(net, slices);
break;
case '*':
fprintf(vvp_out, " %%mul;\n");
put_vec_to_lval(net, slices);
break;
case '/':
fprintf(vvp_out, " %%div%s;\n", ivl_expr_signed(rval)? "/s":"");
put_vec_to_lval(net, slices);
break;
case '%':
fprintf(vvp_out, " %%mod%s;\n", ivl_expr_signed(rval)? "/s":"");
put_vec_to_lval(net, slices);
break;
case '&':
fprintf(vvp_out, " %%and;\n");
put_vec_to_lval(net, slices);
break;
case '|':
fprintf(vvp_out, " %%or;\n");
put_vec_to_lval(net, slices);
break;
case '^':
fprintf(vvp_out, " %%xor;\n");
put_vec_to_lval(net, slices);
break;
case 'l': /* lval <<= expr */
idx_reg = allocate_word();
fprintf(vvp_out, " %%ix/vec4 %d;\n", idx_reg);
fprintf(vvp_out, " %%shiftl %d;\n", idx_reg);
clr_word(idx_reg);
put_vec_to_lval(net, slices);
break;
case 'r': /* lval >>= expr */
idx_reg = allocate_word();
fprintf(vvp_out, " %%ix/vec4 %d;\n", idx_reg);
fprintf(vvp_out, " %%shiftr %d;\n", idx_reg);
clr_word(idx_reg);
put_vec_to_lval(net, slices);
break;
case 'R': /* lval >>>= expr */
idx_reg = allocate_word();
fprintf(vvp_out, " %%ix/vec4 %d;\n", idx_reg);
fprintf(vvp_out, " %%shiftr/s %d;\n", idx_reg);
clr_word(idx_reg);
put_vec_to_lval(net, slices);
break;
default:
fprintf(vvp_out, "; UNSUPPORTED ASSIGNMENT OPCODE: %c\n", ivl_stmt_opcode(net));
assert(0);
break;
}
if (slices)
free(slices);
return 0;
}
static int show_stmt_assign_sig_darray(ivl_statement_t net)
{
int errors = 0;
ivl_lval_t lval = ivl_stmt_lval(net, 0);
ivl_expr_t rval = ivl_stmt_rval(net);
ivl_expr_t part = ivl_lval_part_off(lval);
ivl_signal_t var= ivl_lval_sig(lval);
ivl_type_t var_type= ivl_signal_net_type(var);
assert(ivl_type_base(var_type) == IVL_VT_DARRAY);
ivl_type_t element_type = ivl_type_element(var_type);
ivl_expr_t mux = ivl_lval_idx(lval);
assert(ivl_stmt_lvals(net) == 1);
assert(ivl_stmt_opcode(net) == 0);
assert(part == 0);
if (mux && (ivl_type_base(element_type)==IVL_VT_REAL)) {
draw_eval_real(rval);
/* The %set/dar expects the array index to be in index
register 3. Calculate the index in place. */
draw_eval_expr_into_integer(mux, 3);
fprintf(vvp_out, " %%store/dar/r v%p_0;\n", var);
} else if (mux && ivl_type_base(element_type)==IVL_VT_STRING) {
/* Evaluate the rval into the top of the string stack. */
draw_eval_string(rval);
/* The %store/dar/s expects the array index to me in index
register 3. Calculate the index in place. */
draw_eval_expr_into_integer(mux, 3);
fprintf(vvp_out, " %%store/dar/str v%p_0;\n", var);
} else if (mux) {
draw_eval_vec4(rval);
/* The %store/dar/vec4 expects the array index to be in index
register 3. Calculate the index in place. */
draw_eval_expr_into_integer(mux, 3);
fprintf(vvp_out, " %%store/dar/vec4 v%p_0;\n", var);
} else if (ivl_expr_type(rval) == IVL_EX_ARRAY_PATTERN) {
/* There is no l-value mux, but the r-value is an array
pattern. This is a special case of an assignment to
elements of the l-value. */
errors += show_stmt_assign_darray_pattern(net);
} else {
/* There is no l-value mux, so this must be an
assignment to the array as a whole. Evaluate the
"object", and store the evaluated result. */
errors += draw_eval_object(rval);
fprintf(vvp_out, " %%store/obj v%p_0;\n", var);
}
return errors;
}
static void draw_binary_vec4_le(ivl_expr_t expr)
{
ivl_expr_t le = ivl_expr_oper1(expr);
ivl_expr_t re = ivl_expr_oper2(expr);
ivl_expr_t tmp;
if ((ivl_expr_value(le) == IVL_VT_REAL)
|| (ivl_expr_value(re) == IVL_VT_REAL)) {
draw_binary_vec4_le_real(expr);
return;
}
char use_opcode = ivl_expr_opcode(expr);
char s_flag = (ivl_expr_signed(le) && ivl_expr_signed(re)) ? 's' : 'u';
/* If this is a > or >=, then convert it to < or <= by
swapping the operands. Adjust the opcode to match. */
switch (use_opcode) {
case 'G':
tmp = le;
le = re;
re = tmp;
use_opcode = 'L';
break;
case '>':
tmp = le;
le = re;
re = tmp;
use_opcode = '<';
break;
}
if ((ivl_expr_value(le)==IVL_VT_STRING)
&& (ivl_expr_value(re)==IVL_VT_STRING)) {
draw_binary_vec4_le_string(expr);
return;
}
if ((ivl_expr_value(le)==IVL_VT_STRING)
&& (ivl_expr_type(re)==IVL_EX_STRING)) {
draw_binary_vec4_le_string(expr);
return;
}
if ((ivl_expr_type(le)==IVL_EX_STRING)
&& (ivl_expr_value(re)==IVL_VT_STRING)) {
draw_binary_vec4_le_string(expr);
return;
}
/* NOTE: I think I would rather the elaborator handle the
operand widths. When that happens, take this code out. */
unsigned use_wid = ivl_expr_width(le);
if (ivl_expr_width(re) > use_wid)
use_wid = ivl_expr_width(re);
draw_eval_vec4(le);
resize_vec4_wid(le, use_wid);
if (ivl_expr_width(re)==use_wid && test_immediate_vec4_ok(re)) {
/* Special case: If the right operand can be handled as
an immediate operand, then use that instead. */
char opcode[8];
snprintf(opcode, sizeof opcode, "%%cmpi/%c", s_flag);
draw_immediate_vec4(re, opcode);
} else {
draw_eval_vec4(re);
resize_vec4_wid(re, use_wid);
fprintf(vvp_out, " %%cmp/%c;\n", s_flag);
}
switch (use_opcode) {
case 'L':
fprintf(vvp_out, " %%flag_get/vec4 4;\n");
fprintf(vvp_out, " %%flag_get/vec4 5;\n");
fprintf(vvp_out, " %%or;\n");
break;
case '<':
fprintf(vvp_out, " %%flag_get/vec4 5;\n");
break;
default:
assert(0);
break;
}
}
static void draw_binary_vec4_compare(ivl_expr_t expr)
{
ivl_expr_t le = ivl_expr_oper1(expr);
ivl_expr_t re = ivl_expr_oper2(expr);
if ((ivl_expr_value(le) == IVL_VT_REAL)
|| (ivl_expr_value(re) == IVL_VT_REAL)) {
draw_binary_vec4_compare_real(expr);
return;
}
if ((ivl_expr_value(le)==IVL_VT_STRING)
&& (ivl_expr_value(re)==IVL_VT_STRING)) {
draw_binary_vec4_compare_string(expr);
return;
}
if ((ivl_expr_value(le)==IVL_VT_STRING)
&& (ivl_expr_type(re)==IVL_EX_STRING)) {
draw_binary_vec4_compare_string(expr);
return;
}
if ((ivl_expr_type(le)==IVL_EX_STRING)
&& (ivl_expr_value(re)==IVL_VT_STRING)) {
draw_binary_vec4_compare_string(expr);
return;
}
if ((ivl_expr_value(le)==IVL_VT_CLASS)
&& (ivl_expr_value(re)==IVL_VT_CLASS)) {
draw_binary_vec4_compare_class(expr);
return;
}
unsigned use_wid = ivl_expr_width(le);
if (ivl_expr_width(re) > use_wid)
use_wid = ivl_expr_width(re);
draw_eval_vec4(le);
resize_vec4_wid(le, use_wid);
draw_eval_vec4(re);
resize_vec4_wid(re, use_wid);
switch (ivl_expr_opcode(expr)) {
case 'e': /* == */
fprintf(vvp_out, " %%cmp/e;\n");
fprintf(vvp_out, " %%flag_get/vec4 4;\n");
break;
case 'n': /* != */
fprintf(vvp_out, " %%cmp/e;\n");
fprintf(vvp_out, " %%flag_inv 4;\n");
fprintf(vvp_out, " %%flag_get/vec4 4;\n");
break;
case 'E': /* === */
fprintf(vvp_out, " %%cmp/e;\n");
fprintf(vvp_out, " %%flag_get/vec4 6;\n");
break;
case 'N': /* !== */
fprintf(vvp_out, " %%cmp/e;\n");
fprintf(vvp_out, " %%flag_inv 6;\n");
fprintf(vvp_out, " %%flag_get/vec4 6;\n");
break;
default:
assert(0);
}
}
static int show_stmt_assign_sig_cobject(ivl_statement_t net)
{
int errors = 0;
ivl_lval_t lval = ivl_stmt_lval(net, 0);
ivl_expr_t rval = ivl_stmt_rval(net);
ivl_signal_t sig= ivl_lval_sig(lval);
unsigned lwid = ivl_lval_width(lval);
int prop_idx = ivl_lval_property_idx(lval);
if (prop_idx >= 0) {
ivl_type_t sig_type = ivl_signal_net_type(sig);
ivl_type_t prop_type = ivl_type_prop_type(sig_type, prop_idx);
if (ivl_type_base(prop_type) == IVL_VT_BOOL) {
assert(ivl_type_packed_dimensions(prop_type) == 1);
assert(ivl_type_packed_msb(prop_type,0) >= ivl_type_packed_lsb(prop_type, 0));
draw_eval_vec4(rval);
if (ivl_expr_value(rval)!=IVL_VT_BOOL)
fprintf(vvp_out, " %%cast2;\n");
fprintf(vvp_out, " %%load/obj v%p_0;\n", sig);
fprintf(vvp_out, " %%store/prop/v %d, %u; Store in bool property %s\n",
prop_idx, lwid, ivl_type_prop_name(sig_type, prop_idx));
fprintf(vvp_out, " %%pop/obj 1, 0;\n");
} else if (ivl_type_base(prop_type) == IVL_VT_LOGIC) {
assert(ivl_type_packed_dimensions(prop_type) == 1);
assert(ivl_type_packed_msb(prop_type,0) >= ivl_type_packed_lsb(prop_type, 0));
draw_eval_vec4(rval);
fprintf(vvp_out, " %%load/obj v%p_0;\n", sig);
fprintf(vvp_out, " %%store/prop/v %d, %u; Store in logic property %s\n",
prop_idx, lwid, ivl_type_prop_name(sig_type, prop_idx));
fprintf(vvp_out, " %%pop/obj 1, 0;\n");
} else if (ivl_type_base(prop_type) == IVL_VT_REAL) {
/* Calculate the real value into the real value
stack. The %store/prop/r will pop the stack
value. */
draw_eval_real(rval);
fprintf(vvp_out, " %%load/obj v%p_0;\n", sig);
fprintf(vvp_out, " %%store/prop/r %d;\n", prop_idx);
fprintf(vvp_out, " %%pop/obj 1, 0;\n");
} else if (ivl_type_base(prop_type) == IVL_VT_STRING) {
/* Calculate the string value into the string value
stack. The %store/prop/r will pop the stack
value. */
draw_eval_string(rval);
fprintf(vvp_out, " %%load/obj v%p_0;\n", sig);
fprintf(vvp_out, " %%store/prop/str %d;\n", prop_idx);
fprintf(vvp_out, " %%pop/obj 1, 0;\n");
} else if (ivl_type_base(prop_type) == IVL_VT_DARRAY) {
int idx = 0;
/* The property is a darray, and there is no mux
expression to the assignment is of an entire
array object. */
fprintf(vvp_out, " %%load/obj v%p_0;\n", sig);
draw_eval_object(rval);
fprintf(vvp_out, " %%store/prop/obj %d, %d; IVL_VT_DARRAY\n", prop_idx, idx);
fprintf(vvp_out, " %%pop/obj 1, 0;\n");
} else if (ivl_type_base(prop_type) == IVL_VT_CLASS) {
int idx = 0;
ivl_expr_t idx_expr;
if ( (idx_expr = ivl_lval_idx(lval)) ) {
idx = allocate_word();
}
/* The property is a class object. */
fprintf(vvp_out, " %%load/obj v%p_0;\n", sig);
draw_eval_object(rval);
if (idx_expr) draw_eval_expr_into_integer(idx_expr, idx);
fprintf(vvp_out, " %%store/prop/obj %d, %d; IVL_VT_CLASS\n", prop_idx, idx);
fprintf(vvp_out, " %%pop/obj 1, 0;\n");
if (idx_expr) clr_word(idx);
} else {
fprintf(vvp_out, " ; ERROR: ivl_type_base(prop_type) = %d\n",
ivl_type_base(prop_type));
assert(0);
}
} else {
/* There is no property select, so evaluate the r-value
as an object and assign the entire object to the
variable. */
errors += draw_eval_object(rval);
if (ivl_signal_array_count(sig) > 1) {
unsigned ix;
ivl_expr_t aidx = ivl_lval_idx(lval);
draw_eval_expr_into_integer(aidx, (ix = allocate_word()));
fprintf(vvp_out, " %%store/obja v%p, %u;\n", sig, ix);
clr_word(ix);
} else {
/* Not an array, so no index expression */
fprintf(vvp_out, " %%store/obj v%p_0;\n", sig);
}
}
return errors;
}
static void draw_unary_vec4(ivl_expr_t expr)
{
ivl_expr_t sub = ivl_expr_oper1(expr);
if (debug_draw) {
fprintf(vvp_out, " ; %s:%u:draw_unary_vec4: opcode=%c\n",
ivl_expr_file(expr), ivl_expr_lineno(expr),
ivl_expr_opcode(expr));
}
switch (ivl_expr_opcode(expr)) {
case '&':
draw_eval_vec4(sub);
fprintf(vvp_out, " %%and/r;\n");
break;
case '|':
draw_eval_vec4(sub);
fprintf(vvp_out, " %%or/r;\n");
break;
case '^':
draw_eval_vec4(sub);
fprintf(vvp_out, " %%xor/r;\n");
break;
case '~':
draw_eval_vec4(sub);
fprintf(vvp_out, " %%inv;\n");
break;
case '!':
draw_eval_vec4(sub);
fprintf(vvp_out, " %%nor/r;\n");
break;
case '-':
draw_eval_vec4(sub);
fprintf(vvp_out, " %%inv;\n");
fprintf(vvp_out, " %%pushi/vec4 1, 0, %u;\n", ivl_expr_width(sub));
fprintf(vvp_out, " %%add;\n");
break;
case 'A': /* nand (~&) */
draw_eval_vec4(sub);
fprintf(vvp_out, " %%nand/r;\n");
break;
case 'D': /* pre-decrement (--x) */
draw_unary_inc_dec(sub, false, true);
break;
case 'd': /* post_decrement (x--) */
draw_unary_inc_dec(sub, false, false);
break;
case 'I': /* pre-increment (++x) */
draw_unary_inc_dec(sub, true, true);
break;
case 'i': /* post-increment (x++) */
draw_unary_inc_dec(sub, true, false);
break;
case 'N': /* nor (~|) */
draw_eval_vec4(sub);
fprintf(vvp_out, " %%nor/r;\n");
break;
case 'X': /* xnor (~^) */
draw_eval_vec4(sub);
fprintf(vvp_out, " %%xnor/r;\n");
break;
case 'm': /* abs(m) */
draw_eval_vec4(sub);
if (! ivl_expr_signed(sub))
break;
/* Test if (m) < 0 */
fprintf(vvp_out, " %%dup/vec4;\n");
fprintf(vvp_out, " %%pushi/vec4 0, 0, %u;\n", ivl_expr_width(sub));
fprintf(vvp_out, " %%cmp/s;\n");
fprintf(vvp_out, " %%jmp/0xz T_%u.%u, 5;\n", thread_count, local_count);
/* If so, calculate -(m) */
fprintf(vvp_out, " %%inv;\n");
fprintf(vvp_out, " %%pushi/vec4 1, 0, %u;\n", ivl_expr_width(sub));
fprintf(vvp_out, " %%add;\n");
fprintf(vvp_out, "T_%u.%u ;\n", thread_count, local_count);
local_count += 1;
break;
case 'v': /* Cast real to vec4 */
assert(ivl_expr_value(sub) == IVL_VT_REAL);
draw_eval_real(sub);
fprintf(vvp_out, " %%cvt/vr %u;\n", ivl_expr_width(expr));
break;
case '2': /* Cast expression to bool */
switch (ivl_expr_value(sub)) {
case IVL_VT_LOGIC:
draw_eval_vec4(sub);
fprintf(vvp_out, " %%cast2;\n");
resize_vec4_wid(sub, ivl_expr_width(expr));
break;
case IVL_VT_BOOL:
draw_eval_vec4(sub);
resize_vec4_wid(sub, ivl_expr_width(expr));
break;
case IVL_VT_REAL:
draw_eval_real(sub);
fprintf(vvp_out, " %%cvt/vr %u;\n", ivl_expr_width(expr));
break;
default:
assert(0);
break;
}
break;
default:
fprintf(stderr, "XXXX Unary operator %c not implemented\n", ivl_expr_opcode(expr));
break;
}
}
static void draw_binary_vec4_arith(ivl_expr_t expr)
{
ivl_expr_t le = ivl_expr_oper1(expr);
ivl_expr_t re = ivl_expr_oper2(expr);
unsigned lwid = ivl_expr_width(le);
unsigned rwid = ivl_expr_width(re);
unsigned ewid = ivl_expr_width(expr);
int signed_flag = ivl_expr_signed(le) && ivl_expr_signed(re) ? 1 : 0;
const char*signed_string = signed_flag? "/s" : "";
/* All the arithmetic operations handled here require that the
operands (and the result) be the same width. We further
assume that the core has not given us an operand wider then
the expression width. So padd operands as needed. */
draw_eval_vec4(le);
if (lwid != ewid) {
fprintf(vvp_out, " %%pad/%c %u;\n", ivl_expr_signed(le)? 's' : 'u', ewid);
}
/* Special case: If the re expression can be collected into an
immediate operand, and the instruction supports it, then
generate an immediate instruction instead of the generic
version. */
if (rwid==ewid && test_immediate_vec4_ok(re)) {
switch (ivl_expr_opcode(expr)) {
case '+':
draw_immediate_vec4(re, "%addi");
return;
case '-':
draw_immediate_vec4(re, "%subi");
return;
case '*':
draw_immediate_vec4(re, "%muli");
return;
default:
break;
}
}
draw_eval_vec4(re);
if (rwid != ewid) {
fprintf(vvp_out, " %%pad/%c %u;\n", ivl_expr_signed(re)? 's' : 'u', ewid);
}
switch (ivl_expr_opcode(expr)) {
case '+':
fprintf(vvp_out, " %%add;\n");
break;
case '-':
fprintf(vvp_out, " %%sub;\n");
break;
case '*':
fprintf(vvp_out, " %%mul;\n");
break;
case '/':
fprintf(vvp_out, " %%div%s;\n", signed_string);
break;
case '%':
fprintf(vvp_out, " %%mod%s;\n", signed_string);
break;
case 'p':
/* Note that the power operator is signed if EITHER of
the operands is signed. This is different from other
arithmetic operators. */
if (ivl_expr_signed(le) || ivl_expr_signed(re))
signed_string = "/s";
fprintf(vvp_out, " %%pow%s;\n", signed_string);
break;
default:
assert(0);
break;
}
}
static int draw_condition_binary_compare(ivl_expr_t expr)
{
ivl_expr_t le = ivl_expr_oper1(expr);
ivl_expr_t re = ivl_expr_oper2(expr);
if ((ivl_expr_value(le) == IVL_VT_REAL)
|| (ivl_expr_value(re) == IVL_VT_REAL)) {
return draw_condition_fallback(expr);
}
if ((ivl_expr_value(le)==IVL_VT_STRING)
&& (ivl_expr_value(re)==IVL_VT_STRING)) {
return draw_condition_fallback(expr);
}
if ((ivl_expr_value(le)==IVL_VT_STRING)
&& (ivl_expr_type(re)==IVL_EX_STRING)) {
return draw_condition_fallback(expr);
}
if ((ivl_expr_type(le)==IVL_EX_STRING)
&& (ivl_expr_value(re)==IVL_VT_STRING)) {
return draw_condition_fallback(expr);
}
if ((ivl_expr_value(le)==IVL_VT_CLASS)
&& (ivl_expr_value(re)==IVL_VT_CLASS)) {
return draw_condition_fallback(expr);
}
unsigned use_wid = ivl_expr_width(le);
if (ivl_expr_width(re) > use_wid)
use_wid = ivl_expr_width(re);
/* If the le is constant, then swap the operands so that we
can possibly take advantage of the immediate version of the
%cmp instruction. */
if (ivl_expr_width(le)==use_wid && test_immediate_vec4_ok(le)) {
ivl_expr_t tmp = le;
re = le;
le = tmp;
}
draw_eval_vec4(le);
resize_vec4_wid(le, use_wid);
char use_opcode = ivl_expr_opcode(expr);
if (ivl_expr_width(re)==use_wid && test_immediate_vec4_ok(re)) {
/* Special case: If the right operand can be handled as
an immediate operand, then use that instead. */
if (use_opcode=='n' || use_opcode=='N')
draw_immediate_vec4(re, "%cmpi/ne");
else
draw_immediate_vec4(re, "%cmpi/e");
} else {
draw_eval_vec4(re);
resize_vec4_wid(re, use_wid);
if (use_opcode=='n' || use_opcode=='N')
fprintf(vvp_out, " %%cmp/ne;\n");
else
fprintf(vvp_out, " %%cmp/e;\n");
}
switch (ivl_expr_opcode(expr)) {
case 'n': /* != */
case 'e': /* == */
return 4;
break;
case 'N': /* !== */
case 'E': /* === */
return 6;
default:
assert(0);
return -1;
}
}
static int eval_darray_new(ivl_expr_t ex)
{
int errors = 0;
unsigned size_reg = allocate_word();
ivl_expr_t size_expr = ivl_expr_oper1(ex);
ivl_expr_t init_expr = ivl_expr_oper2(ex);
draw_eval_expr_into_integer(size_expr, size_reg);
// The new function has a net_type that contains the details
// of the type.
ivl_type_t net_type = ivl_expr_net_type(ex);
assert(net_type);
ivl_type_t element_type = ivl_type_element(net_type);
assert(element_type);
switch (ivl_type_base(element_type)) {
int msb, lsb, wid;
case IVL_VT_REAL:
// REAL objects are not packable.
assert(ivl_type_packed_dimensions(element_type) == 0);
fprintf(vvp_out, " %%new/darray %u, \"r\";\n", size_reg);
break;
case IVL_VT_STRING:
// STRING objects are not packable.
assert(ivl_type_packed_dimensions(element_type) == 0);
fprintf(vvp_out, " %%new/darray %u, \"S\";\n", size_reg);
break;
case IVL_VT_BOOL:
// bool objects are vectorable, but for now only support
// a single dimensions.
assert(ivl_type_packed_dimensions(element_type) == 1);
msb = ivl_type_packed_msb(element_type, 0);
lsb = ivl_type_packed_lsb(element_type, 0);
wid = msb>=lsb? msb - lsb : lsb - msb;
wid += 1;
fprintf(vvp_out, " %%new/darray %u, \"%sb%d\";\n", size_reg,
ivl_type_signed(element_type) ? "s" : "", wid);
break;
case IVL_VT_LOGIC:
// logic objects are vectorable, but for now only support
// a single dimensions.
assert(ivl_type_packed_dimensions(element_type) == 1);
msb = ivl_type_packed_msb(element_type, 0);
lsb = ivl_type_packed_lsb(element_type, 0);
wid = msb>=lsb? msb - lsb : lsb - msb;
wid += 1;
fprintf(vvp_out, " %%new/darray %u, \"%sv%d\";\n", size_reg,
ivl_type_signed(element_type) ? "s" : "", wid);
break;
default:
assert(0);
break;
}
clr_word(size_reg);
if (init_expr && ivl_expr_type(init_expr)==IVL_EX_ARRAY_PATTERN) {
unsigned idx;
switch (ivl_type_base(element_type)) {
case IVL_VT_BOOL:
case IVL_VT_LOGIC:
for (idx = 0 ; idx < ivl_expr_parms(init_expr) ; idx += 1) {
draw_eval_vec4(ivl_expr_parm(init_expr,idx));
fprintf(vvp_out, " %%ix/load 3, %u, 0;\n", idx);
fprintf(vvp_out, " %%set/dar/obj/vec4 3;\n");
fprintf(vvp_out, " %%pop/vec4 1;\n");
}
break;
case IVL_VT_REAL:
for (idx = 0 ; idx < ivl_expr_parms(init_expr) ; idx += 1) {
draw_eval_real(ivl_expr_parm(init_expr,idx));
fprintf(vvp_out, " %%ix/load 3, %u, 0;\n", idx);
fprintf(vvp_out, " %%set/dar/obj/real 3;\n");
fprintf(vvp_out, " %%pop/real 1;\n");
}
break;
case IVL_VT_STRING:
for (idx = 0 ; idx < ivl_expr_parms(init_expr) ; idx += 1) {
draw_eval_string(ivl_expr_parm(init_expr,idx));
fprintf(vvp_out, " %%ix/load 3, %u, 0;\n", idx);
fprintf(vvp_out, " %%set/dar/obj/str 3;\n");
fprintf(vvp_out, " %%pop/str 1;\n");
}
break;
default:
fprintf(vvp_out, "; ERROR: Sorry, this type not supported here.\n");
errors += 1;
break;
}
} else if (init_expr && (ivl_expr_value(init_expr) == IVL_VT_DARRAY)) {
ivl_signal_t sig = ivl_expr_signal(init_expr);
fprintf(vvp_out, " %%load/obj v%p_0;\n", sig);
fprintf(vvp_out, " %%scopy;\n");
} else if (init_expr && number_is_immediate(size_expr,32,0)) {
/* In this case, there is an init expression, the
expression is NOT an array_pattern, and the size
expression used to calculate the size of the array is
a constant. Generate an unrolled set of assignments. */
long idx;
long cnt = get_number_immediate(size_expr);
unsigned wid;
switch (ivl_type_base(element_type)) {
case IVL_VT_BOOL:
case IVL_VT_LOGIC:
wid = width_of_packed_type(element_type);
for (idx = 0 ; idx < cnt ; idx += 1) {
draw_eval_vec4(init_expr);
fprintf(vvp_out, " %%parti/%c %u, %ld, 6;\n",
ivl_expr_signed(init_expr) ? 's' : 'u', wid, idx * wid);
fprintf(vvp_out, " %%ix/load 3, %ld, 0;\n", cnt - idx - 1);
fprintf(vvp_out, " %%set/dar/obj/vec4 3;\n");
fprintf(vvp_out, " %%pop/vec4 1;\n");
}
break;
case IVL_VT_REAL:
draw_eval_real(init_expr);
for (idx = 0 ; idx < cnt ; idx += 1) {
fprintf(vvp_out, " %%ix/load 3, %ld, 0;\n", idx);
fprintf(vvp_out, " %%set/dar/obj/real 3;\n");
}
fprintf(vvp_out, " %%pop/real 1;\n");
break;
case IVL_VT_STRING:
draw_eval_string(init_expr);
for (idx = 0 ; idx < cnt ; idx += 1) {
fprintf(vvp_out, " %%ix/load 3, %ld, 0;\n", idx);
fprintf(vvp_out, " %%set/dar/obj/str 3;\n");
}
fprintf(vvp_out, " %%pop/str 1;\n");
break;
default:
fprintf(vvp_out, "; ERROR: Sorry, this type not supported here.\n");
errors += 1;
break;
}
} else if (init_expr) {
fprintf(vvp_out, "; ERROR: Sorry, I don't know how to work with this size expr.\n");
errors += 1;
}
return errors;
}
static void get_vec_from_lval_slice(ivl_lval_t lval, struct vec_slice_info*slice,
unsigned wid)
{
ivl_signal_t sig = ivl_lval_sig(lval);
ivl_expr_t part_off_ex = ivl_lval_part_off(lval);
unsigned long part_off = 0;
/* Although Verilog doesn't support it, we'll handle
here the case of an l-value part select of an array
word if the address is constant. */
ivl_expr_t word_ix = ivl_lval_idx(lval);
unsigned long use_word = 0;
if (part_off_ex == 0) {
part_off = 0;
} else if (number_is_immediate(part_off_ex, IMM_WID, 0) &&
!number_is_unknown(part_off_ex)) {
part_off = get_number_immediate(part_off_ex);
part_off_ex = 0;
}
/* If the word index is a constant expression, then evaluate
it to select the word, and pay no further heed to the
expression itself. */
if (word_ix && number_is_immediate(word_ix, IMM_WID, 0)) {
assert(! number_is_unknown(word_ix));
use_word = get_number_immediate(word_ix);
word_ix = 0;
}
if (ivl_signal_dimensions(sig)==0 && part_off_ex==0 && word_ix==0
&& part_off==0 && wid==ivl_signal_width(sig)) {
slice->type = SLICE_SIMPLE_VECTOR;
slice->u_.simple_vector.use_word = use_word;
fprintf(vvp_out, " %%load/vec4 v%p_%lu;\n", sig, use_word);
} else if (ivl_signal_dimensions(sig)==0 && part_off_ex==0 && word_ix==0) {
assert(use_word == 0);
slice->type = SLICE_PART_SELECT_STATIC;
slice->u_.part_select_static.part_off = part_off;
fprintf(vvp_out, " %%load/vec4 v%p_%lu;\n", sig, use_word);
fprintf(vvp_out, " %%pushi/vec4 %lu, 0, 32;\n", part_off);
fprintf(vvp_out, " %%part/u %u;\n", wid);
} else if (ivl_signal_dimensions(sig)==0 && part_off_ex!=0 && word_ix==0) {
assert(use_word == 0);
assert(part_off == 0);
slice->type = SLICE_PART_SELECT_DYNAMIC;
slice->u_.part_select_dynamic.word_idx_reg = allocate_word();
slice->u_.part_select_dynamic.x_flag = allocate_flag();
fprintf(vvp_out, " %%load/vec4 v%p_%lu;\n", sig, use_word);
draw_eval_vec4(part_off_ex);
fprintf(vvp_out, " %%flag_mov %u, 4;\n", slice->u_.part_select_dynamic.x_flag);
fprintf(vvp_out, " %%dup/vec4;\n");
fprintf(vvp_out, " %%ix/vec4 %u;\n", slice->u_.part_select_dynamic.word_idx_reg);
fprintf(vvp_out, " %%part/u %u;\n", wid);
} else if (ivl_signal_dimensions(sig) > 0 && word_ix == 0) {
slice->type = SLICE_MEMORY_WORD_STATIC;
slice->u_.memory_word_static.use_word = use_word;
if (use_word < ivl_signal_array_count(sig)) {
fprintf(vvp_out, " %%ix/load 3, %lu, 0;\n",
use_word);
fprintf(vvp_out, " %%load/vec4a v%p, 3;\n", sig);
} else {
assert(wid <= 32);
fprintf(vvp_out, " %%pushi/vec4 4294967295, 4294967295, %u;\n", wid);
}
} else if (ivl_signal_dimensions(sig) > 0 && word_ix != 0) {
slice->type = SLICE_MEMORY_WORD_DYNAMIC;
slice->u_.memory_word_dynamic.word_idx_reg = allocate_word();
slice->u_.memory_word_dynamic.x_flag = allocate_flag();
draw_eval_expr_into_integer(word_ix, slice->u_.memory_word_dynamic.word_idx_reg);
fprintf(vvp_out, " %%flag_mov %d, 4;\n", slice->u_.memory_word_dynamic.x_flag);
fprintf(vvp_out, " %%load/vec4a v%p, %d;\n", sig, slice->u_.memory_word_dynamic.word_idx_reg);
} else {
assert(0);
}
}