static int graes_start(struct graes_priv *pDev)
{
struct graes_regs *regs = pDev->regs;
int i;
struct graes_ioc_config *cfg = &pDev->config;
volatile unsigned int *txrdy_reg;
unsigned int txrdy_mask, transaddr;
/* Clear Descriptors */
memset(pDev->bds,0,GRAES_BDAR_SIZE);
/* Clear stats */
memset(&pDev->stats,0,sizeof(struct graes_ioc_stats));
/* Init Descriptor Ring */
memset(pDev->_ring,0,sizeof(struct graes_ring)*GRAES_BDAR_ENTRIES);
for(i=0;i<(GRAES_BDAR_ENTRIES-1);i++){
pDev->_ring[i].next = &pDev->_ring[i+1];
pDev->_ring[i].bd = &pDev->bds[i];
pDev->_ring[i].frm = NULL;
}
pDev->_ring[(GRAES_BDAR_ENTRIES-1)].next = &pDev->_ring[0];
pDev->_ring[(GRAES_BDAR_ENTRIES-1)].bd = &pDev->bds[(GRAES_BDAR_ENTRIES-1)];
pDev->_ring[(GRAES_BDAR_ENTRIES-1)].frm = NULL;
pDev->ring = &pDev->_ring[0];
pDev->ring_end = &pDev->_ring[0];
/* Clear Scheduled, Ready and Sent list */
graes_list_clr(&pDev->ready);
graes_list_clr(&pDev->scheduled);
graes_list_clr(&pDev->sent);
/* Software init */
pDev->handling_transmission = 0;
/* Reset the transmitter */
regs->dma_ctrl = 0; /* Leave Reset */
/* Set Descriptor Pointer Base register to point to first descriptor */
drvmgr_translate_check(pDev->dev, CPUMEM_TO_DMA, (void *)pDev->bds,
(void **)&transaddr, GRAES_BDAR_SIZE);
regs->dma_bd = transaddr;
DBG("GRAES: set bd to 0x%08x\n",transaddr);
/*regs->dma_bd = (unsigned int)pDev->bds;*/
/* Set hardware options as defined by config */
if ( graes_hw_set_config(pDev, cfg, &pDev->hw_avail) ) {
return RTEMS_IO_ERROR;
}
DBG("GRAES: reset time %d\n",i);
/* Mark running before enabling the DMA transmitter */
pDev->running = 1;
/* Enable interrupts (Error and DMA TX) */
regs->dma_ctrl = GRAES_DMA_CTRL_IE;
DBG("GRAES: STARTED\n");
return RTEMS_SUCCESSFUL;
}
static int grtm_start(struct grtm_priv *pDev)
{
struct grtm_regs *regs = pDev->regs;
int i;
struct grtm_ioc_config *cfg = &pDev->config;
unsigned int txrdy;
/* Clear Descriptors */
memset(pDev->bds,0,0x400);
/* Clear stats */
memset(&pDev->stats,0,sizeof(struct grtm_ioc_stats));
/* Init Descriptor Ring */
memset(pDev->_ring,0,sizeof(struct grtm_ring)*128);
for(i=0;i<127;i++){
pDev->_ring[i].next = &pDev->_ring[i+1];
pDev->_ring[i].bd = &pDev->bds[i];
pDev->_ring[i].frm = NULL;
}
pDev->_ring[127].next = &pDev->_ring[0];
pDev->_ring[127].bd = &pDev->bds[127];
pDev->_ring[127].frm = NULL;
pDev->ring = &pDev->_ring[0];
pDev->ring_end = &pDev->_ring[0];
/* Clear Scheduled, Ready and Sent list */
grtm_list_clr(&pDev->ready);
grtm_list_clr(&pDev->scheduled);
grtm_list_clr(&pDev->sent);
/* Software init */
pDev->handling_transmission = 0;
/* Reset the transmitter */
regs->dma_ctrl = GRTM_DMA_CTRL_TXRST;
regs->dma_ctrl = 0; /* Leave Reset */
/* Clear old interrupts */
regs->dma_status = GRTM_DMA_STS_ALL;
/* Set Descriptor Pointer Base register to point to first descriptor */
drvmgr_translate_check(pDev->dev, CPUMEM_TO_DMA, (void *)pDev->bds,
(void **)®s->dma_bd, 0x400);
/* Set hardware options as defined by config */
if ( grtm_hw_set_config(pDev, cfg, &pDev->hw_avail) ) {
return RTEMS_IO_ERROR;
}
/* Enable TM Transmitter */
regs->ctrl = GRTM_CTRL_EN;
/* Wait for TXRDY to be cleared */
i=1000;
while( i > 0 ) {
asm volatile ("nop"::);
i--;
}
/* Check transmitter startup OK */
i = 1000000;
do {
/* Location of TXRDY Bit is different for different revisions */
if ( pDev->subrev == 0 ) {
txrdy = READ_REG(®s->dma_ctrl) &
GRTM_REV0_DMA_CTRL_TXRDY;
} else {
txrdy = READ_REG(®s->dma_status) &
GRTM_REV1_DMA_STS_TXRDY;
}
if (txrdy != 0)
break;
asm volatile ("nop"::);
} while ( --i > 0 );
if ( i == 0 ) {
/* Reset Failed */
DBG("GRTM: start: Reseting transmitter failed (%d)\n",i);
return RTEMS_IO_ERROR;
}
DBG("GRTM: reset time %d\n",i);
/* Everything is configured, the TM transmitter is started
* and idle frames has been sent.
*/
/* Mark running before enabling the DMA transmitter */
pDev->running = 1;
/* Enable interrupts (Error and DMA TX) */
regs->dma_ctrl = GRTM_DMA_CTRL_IE;
DBG("GRTM: STARTED\n");
return RTEMS_SUCCESSFUL;
}
