static int dsi_pll_enable_seq_e(void) { int pll_locked = 0; dsi_pll_software_reset(); /* * Add hardware recommended delays between register writes for * the updates to take effect. These delays are necessary for the * PLL to successfully lock */ DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x01); udelay(200); DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x05); udelay(200); DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x0d); DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x0f); udelay(1000); pll_locked = dsi_pll_lock_status(); pr_debug("%s: PLL status = %s\n", __func__, pll_locked ? "Locked" : "Unlocked"); return pll_locked ? 0 : -EINVAL; }
static int dsi_pll_enable_seq_e(struct mdss_pll_resources *dsi_pll_res) { int pll_locked = 0; dsi_pll_software_reset(dsi_pll_res); /* * Add hardware recommended delays between register writes for * the updates to take effect. These delays are necessary for the * PLL to successfully lock */ MDSS_PLL_REG_W(dsi_pll_res->pll_base, DSI_PHY_PLL_UNIPHY_PLL_PWRGEN_CFG, 0x00); udelay(50); MDSS_PLL_REG_W(dsi_pll_res->pll_base, DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x01); udelay(200); MDSS_PLL_REG_W(dsi_pll_res->pll_base, DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x05); udelay(200); MDSS_PLL_REG_W(dsi_pll_res->pll_base, DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x0d); udelay(1); MDSS_PLL_REG_W(dsi_pll_res->pll_base, DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x0f); udelay(600); dsi_pll_toggle_lock_detect(dsi_pll_res); pll_locked = dsi_pll_lock_status(dsi_pll_res); pr_debug("PLL status = %s\n", pll_locked ? "Locked" : "Unlocked"); return pll_locked ? 0 : -EINVAL; }
static int dsi_pll_enable_seq_m(struct mdss_pll_resources *dsi_pll_res) { int i = 0; int pll_locked = 0; dsi_pll_software_reset(dsi_pll_res); /* * Add hardware recommended delays between register writes for * the updates to take effect. These delays are necessary for the * PLL to successfully lock */ MDSS_PLL_REG_W(dsi_pll_res->pll_base, DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG1, 0x34); MDSS_PLL_REG_W(dsi_pll_res->pll_base, DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x01); udelay(200); MDSS_PLL_REG_W(dsi_pll_res->pll_base, DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x05); udelay(200); MDSS_PLL_REG_W(dsi_pll_res->pll_base, DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x0f); udelay(600); dsi_pll_toggle_lock_detect(dsi_pll_res); pll_locked = dsi_pll_lock_status(dsi_pll_res); for (i = 0; (i < DSI_PLL_SEQ_M_MAX_COUNTER) && !pll_locked; i++) { MDSS_PLL_REG_W(dsi_pll_res->pll_base, DSI_PHY_PLL_UNIPHY_PLL_PWRGEN_CFG, 0x00); udelay(50); MDSS_PLL_REG_W(dsi_pll_res->pll_base, DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x05); udelay(100); MDSS_PLL_REG_W(dsi_pll_res->pll_base, DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x0f); udelay(600); dsi_pll_toggle_lock_detect(dsi_pll_res); pll_locked = dsi_pll_lock_status(dsi_pll_res); } if (pll_locked) pr_debug("PLL Locked at attempt #%d\n", i); else pr_debug("PLL failed to lock after %d attempt(s)\n", i); return pll_locked ? 0 : -EINVAL; }
static int vco_set_rate_hpm(struct clk *c, unsigned long rate) { int rc; struct dsi_pll_vco_clk *vco = to_vco_clk(c); struct mdss_pll_resources *dsi_pll_res = vco->priv; rc = mdss_pll_resource_enable(dsi_pll_res, true); if (rc) { pr_err("Failed to enable mdss dsi pll resources\n"); return rc; } dsi_pll_software_reset(dsi_pll_res); rc = vco_set_rate(vco, rate); mdss_pll_resource_enable(dsi_pll_res, false); return rc; }
static int dsi_pll_enable_seq_m(void) { int i = 0; int pll_locked = 0; dsi_pll_software_reset(); /* * Add hardware recommended delays between register writes for * the updates to take effect. These delays are necessary for the * PLL to successfully lock */ DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x01); udelay(200); DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x05); udelay(200); DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x0f); udelay(1000); do { pll_locked = dsi_pll_lock_status(); if (!pll_locked) { DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x07); udelay(1); DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x0f); udelay(1000); i++; } } while ((i < 3) && !pll_locked); if (pll_locked) pr_debug("%s: PLL Locked at attempt #%d\n", __func__, i); else pr_debug("%s: PLL failed to lock after %d attempt(s)\n", __func__, i); return pll_locked ? 0 : -EINVAL; }
static int dsi_pll_enable_seq_8974(void) { int i, rc = 0; u32 status, max_reads, timeout_us; dsi_pll_software_reset(); /* * PLL power up sequence. * Add necessary delays recommeded by hardware. */ DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x01); udelay(1000); DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x05); udelay(1000); DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x07); udelay(1000); DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x0f); udelay(1000); for (i = 0; i < 3; i++) { /* DSI Uniphy lock detect setting */ DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_LKDET_CFG2, 0x04); udelay(100); DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_LKDET_CFG2, 0x05); udelay(500); /* poll for PLL ready status */ max_reads = 5; timeout_us = 100; if (readl_poll_timeout_noirq((mdss_dsi_base + DSI_0_PHY_PLL_UNIPHY_PLL_STATUS), status, ((status & 0x01) == 1), max_reads, timeout_us)) { pr_debug("%s: DSI PLL status=%x failed to Lock\n", __func__, status); pr_debug("%s:Trying to power UP PLL again\n", __func__); } else { break; } dsi_pll_software_reset(); /* * PLL power up sequence. * Add necessary delays recommeded by hardware. */ DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x1); udelay(1000); DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x5); udelay(1000); DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x7); udelay(1000); DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x5); udelay(1000); DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x7); udelay(1000); DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0xf); udelay(2000); } if ((status & 0x01) != 1) { pr_debug("%s: DSI PLL status=%x failed to Lock\n", __func__, status); rc = -EINVAL; goto error; } pr_debug("%s: DSI PLL Lock success\n", __func__); error: return rc; }
static int dsi_pll_enable_seq_8974(struct mdss_pll_resources *dsi_pll_res) { int i, rc = 0; u32 max_reads, timeout_us; int pll_locked; dsi_pll_software_reset(dsi_pll_res); /* * PLL power up sequence. * Add necessary delays recommeded by hardware. */ MDSS_PLL_REG_W(dsi_pll_res->pll_base, DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x01); udelay(1); MDSS_PLL_REG_W(dsi_pll_res->pll_base, DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x05); udelay(200); MDSS_PLL_REG_W(dsi_pll_res->pll_base, DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x07); udelay(500); MDSS_PLL_REG_W(dsi_pll_res->pll_base, DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x0f); udelay(500); for (i = 0; i < 2; i++) { udelay(100); /* DSI Uniphy lock detect setting */ MDSS_PLL_REG_W(dsi_pll_res->pll_base, DSI_PHY_PLL_UNIPHY_PLL_LKDET_CFG2, 0x0c); udelay(100); MDSS_PLL_REG_W(dsi_pll_res->pll_base, DSI_PHY_PLL_UNIPHY_PLL_LKDET_CFG2, 0x0d); /* poll for PLL ready status */ max_reads = 5; timeout_us = 100; pll_locked = dsi_pll_lock_status(dsi_pll_res); if (pll_locked) break; dsi_pll_software_reset(dsi_pll_res); /* * PLL power up sequence. * Add necessary delays recommeded by hardware. */ MDSS_PLL_REG_W(dsi_pll_res->pll_base, DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x1); udelay(1); MDSS_PLL_REG_W(dsi_pll_res->pll_base, DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x5); udelay(200); MDSS_PLL_REG_W(dsi_pll_res->pll_base, DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x7); udelay(250); MDSS_PLL_REG_W(dsi_pll_res->pll_base, DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x5); udelay(200); MDSS_PLL_REG_W(dsi_pll_res->pll_base, DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x7); udelay(500); MDSS_PLL_REG_W(dsi_pll_res->pll_base, DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0xf); udelay(500); } if (!pll_locked) { pr_err("DSI PLL lock failed\n"); rc = -EINVAL; } else { pr_debug("DSI PLL Lock success\n"); } return rc; }