static struct dt_node *get_i2cm_node(struct dt_node *xscom, int engine)
{
uint64_t xscom_base = P9_I2CM_XSCOM_BASE + P9_I2CM_XSCOM_SIZE * (uint64_t)engine;
struct dt_node *i2cm;
uint64_t freq, clock;
i2cm = dt_find_by_name_addr(xscom, "i2cm", xscom_base);
if (!i2cm) {
i2cm = dt_new_addr(xscom, "i2cm", xscom_base);
dt_add_property_cells(i2cm, "reg", xscom_base,
P9_I2CM_XSCOM_SIZE);
dt_add_property_strings(i2cm, "compatible",
"ibm,power8-i2cm", "ibm,power9-i2cm");
dt_add_property_cells(i2cm, "#size-cells", 0);
dt_add_property_cells(i2cm, "#address-cells", 1);
dt_add_property_cells(i2cm, "chip-engine#", engine);
freq = dt_prop_get_u64_def(xscom, "bus-frequency", 0);
clock = (u32)(freq / 4);
if (clock)
dt_add_property_cells(i2cm, "clock-frequency", clock);
else
dt_add_property_cells(i2cm, "clock-frequency", 150000000);
}
return i2cm;
}
static struct dt_node *get_bus_node(struct dt_node *i2cm, int port, int freq)
{
struct dt_node *bus;
bus = dt_find_by_name_addr(i2cm, "i2c-bus", port);
if (!bus) {
bus = dt_new_addr(i2cm, "i2c-bus", port);
dt_add_property_cells(bus, "reg", port);
dt_add_property_cells(bus, "#size-cells", 0);
dt_add_property_cells(bus, "#address-cells", 1);
/* The P9 I2C master is fully compatible with the P8 one */
dt_add_property_strings(bus, "compatible", "ibm,opal-i2c",
"ibm,power8-i2c-port", "ibm,power9-i2c-port");
/*
* use the clock frequency as the bus frequency until we
* have actual devices on the bus. Adding a device will
* reduce the frequency to something that all devices
* can tolerate.
*/
dt_add_property_cells(bus, "bus-frequency", freq * 1000);
}
return bus;
}
/*
* Helper function for adding /ibm,opal/consoles/serial@<xyz> nodes
*/
struct dt_node *add_opal_console_node(int index, const char *type,
uint32_t write_buffer_size)
{
struct dt_node *con, *consoles;
char buffer[32];
consoles = dt_find_by_name(opal_node, "consoles");
if (!consoles) {
consoles = dt_new(opal_node, "consoles");
assert(consoles);
dt_add_property_cells(consoles, "#address-cells", 1);
dt_add_property_cells(consoles, "#size-cells", 0);
}
con = dt_new_addr(consoles, "serial", index);
assert(con);
snprintf(buffer, sizeof(buffer), "ibm,opal-console-%s", type);
dt_add_property_string(con, "compatible", buffer);
dt_add_property_cells(con, "#write-buffer-size", write_buffer_size);
dt_add_property_cells(con, "reg", index);
dt_add_property_string(con, "device_type", "serial");
return con;
}
static struct dt_node *dt_create_i2c_device(struct dt_node *bus, uint8_t addr,
const char *name, const char *compat,
const char *label)
{
struct dt_node *dev;
dev = dt_new_addr(bus, name, addr);
if (!dev)
return NULL;
dt_add_property_string(dev, "compatible", compat);
dt_add_property_string(dev, "label", label);
dt_add_property_cells(dev, "reg", addr);
dt_add_property_string(dev, "status", "reserved");
return dev;
}
static struct dt_node *dt_create_i2c_bus(struct dt_node *i2cm,
const char *port_name, uint32_t port_id)
{
static struct dt_node *port;
port = dt_new_addr(i2cm, "i2c-bus", port_id);
if (!port)
return NULL;
dt_add_property_strings(port, "compatible", "ibm,power8-i2c-port",
"ibm,opal-i2c");
dt_add_property_string(port, "ibm,port-name", port_name);
dt_add_property_cells(port, "reg", port_id);
dt_add_property_cells(port, "bus-frequency", 400000);
dt_add_property_cells(port, "#address-cells", 1);
dt_add_property_cells(port, "#size-cells", 0);
return port;
}
static struct dt_node *dt_create_i2c_master(struct dt_node *n, uint32_t eng_id)
{
struct dt_node *i2cm;
/* Each master registers set is of length 0x20 */
i2cm = dt_new_addr(n, "i2cm", 0xa0000 + eng_id * 0x20);
if (!i2cm)
return NULL;
dt_add_property_string(i2cm, "compatible",
"ibm,power8-i2cm");
dt_add_property_cells(i2cm, "reg", 0xa0000 + eng_id * 0x20,
0x20);
dt_add_property_cells(i2cm, "clock-frequency", 50000000);
dt_add_property_cells(i2cm, "chip-engine#", eng_id);
dt_add_property_cells(i2cm, "#address-cells", 1);
dt_add_property_cells(i2cm, "#size-cells", 0);
return i2cm;
}
static struct dt_node *create_cache_node(struct dt_node *cpus,
const struct sppcia_cpu_cache *cache,
const char *name, uint32_t unit_addr,
int okay)
{
struct dt_node *node;
node = dt_new_addr(cpus, name, unit_addr);
assert(node);
dt_add_property_string(node, "device_type", "cache");
dt_add_property_cells(node, "reg", unit_addr);
dt_add_property_string(node, "status", okay ? "okay" : "bad");
dt_add_property(node, "cache-unified", NULL, 0);
/* Assume cache associavitity sets is same for L2, L3 and L3.5 */
dt_add_property_cells(node, "d-cache-sets",
be32_to_cpu(cache->l2_cache_assoc_sets));
dt_add_property_cells(node, "i-cache-sets",
be32_to_cpu(cache->l2_cache_assoc_sets));
return node;
}
int parse_i2c_devs(const struct HDIF_common_hdr *hdr, int idata_index,
struct dt_node *xscom)
{
struct dt_node *i2cm, *bus, *node;
const struct hdat_i2c_type *type;
const struct hdat_i2c_info *info;
const struct i2c_dev *dev;
const char *name, *compat;
const struct host_i2c_hdr *ahdr;
uint32_t dev_addr;
uint32_t version;
uint32_t size;
uint32_t purpose;
int i, count;
/*
* This code makes a few assumptions about XSCOM addrs, etc
* and will need updating for new processors
*/
assert(proc_gen == proc_gen_p9);
/*
* Emit an error if we get a newer version. This is an interim measure
* until the new version format is finalised.
*/
ahdr = HDIF_get_idata(hdr, idata_index, &size);
if (!ahdr || !size)
return -1;
/*
* Some hostboots don't correctly fill the version field. On these
* the offset from the start of the header to the start of the array
* is 16 bytes.
*/
if (be32_to_cpu(ahdr->hdr.offset) == 16) {
version = 1;
prerror("I2C: HDAT device array has no version! Assuming v1\n");
} else {
version = be32_to_cpu(ahdr->version);
}
if (version == 2) {
prlog(PR_INFO, "I2C: v%d found, but not supported. Parsing as v1\n",
version);
} else if (version > 2) {
prerror("I2C: v%d found, but not supported! THIS IS A BUG\n",
version);
return -1;
}
count = HDIF_get_iarray_size(hdr, idata_index);
for (i = 0; i < count; i++) {
dev = HDIF_get_iarray_item(hdr, idata_index, i, &size);
/*
* XXX: Some broken hostboots populate i2c devs with zeros.
* Workaround them for now.
*/
if (is_zeros(dev, size)) {
prerror("I2C: Ignoring broken i2c dev %d\n", i);
continue;
}
/*
* On some systems the CFAM I2C master is represented in the
* host I2C table as engine 6. There are only 4 (0, 1, 2, 3)
* engines accessible to the host via XSCOM so filter out
* engines outside this range so we don't create bogus
* i2cm@<addr> nodes.
*/
if (dev->i2cm_engine >= 4 && proc_gen == proc_gen_p9)
continue;
i2cm = get_i2cm_node(xscom, dev->i2cm_engine);
bus = get_bus_node(i2cm, dev->i2cm_port,
be16_to_cpu(dev->i2c_bus_freq));
/*
* Looks like hostboot gives the address as an 8 bit, left
* justified quantity (i.e it includes the R/W bit). So we need
* to strip it off to get an address linux can use.
*/
dev_addr = dev->dev_addr >> 1;
purpose = be32_to_cpu(dev->purpose);
type = map_type(dev->type);
info = get_info(purpose);
/* HACK: Hostboot doesn't export the correct type information
* for the DIMM SPD EEPROMs. This is a problem because SPD
* EEPROMs have a different wire protocol to the atmel,24XXXX
* series. The main difference being that SPD EEPROMs have an
* 8bit offset rather than a 16bit offset. This means that the
* driver will send 2 bytes when doing a random read,
* potentially overwriting part of the SPD information.
*
* Just to make things interested the FSP also gets the device
* type wrong. To work around both just set the device-type to
* "spd" for anything in the 0x50 to 0x57 range since that's the
* SPD eeprom range.
*
* XXX: Future chips might not use engine 3 for the DIMM buses.
*/
if (dev->i2cm_engine == 3 && dev_addr >= 0x50
&& dev_addr < 0x58) {
compat = "spd";
name = "eeprom";
} else if (type) {
compat = type->compat;
name = type->name;
} else {
name = "unknown";
compat = NULL;
}
/*
* An i2c device is unknown if either the i2c device list is
* outdated or the device is marked as unknown (0xFF) in the
* hdat. Log both cases to see what/where/why.
*/
if (!type || dev->type == 0xFF) {
prlog(PR_NOTICE, "HDAT I2C: found e%dp%d - %s@%x dp:%02x (%#x:%s)\n",
dev->i2cm_engine, dev->i2cm_port, name, dev_addr,
dev->dev_port, purpose, info->label);
continue;
}
prlog(PR_DEBUG, "HDAT I2C: found e%dp%d - %s@%x dp:%02x (%#x:%s)\n",
dev->i2cm_engine, dev->i2cm_port, name, dev_addr,
dev->dev_port, purpose, info->label);
/*
* Multi-port device require special handling since we need to
* generate the device-specific DT bindings. For now we're just
* going to ignore them since these devices are owned by FW
* any way.
*/
if (dev->dev_port != 0xff)
continue;
node = dt_new_addr(bus, name, dev_addr);
if (!node)
continue;
dt_add_property_cells(node, "reg", dev_addr);
dt_add_property_cells(node, "link-id",
be32_to_cpu(dev->i2c_link));
if (compat)
dt_add_property_string(node, "compatible", compat);
if (info->label)
dt_add_property_string(node, "label", info->label);
if (!info->whitelist)
dt_add_property_string(node, "status", "reserved");
/*
* Set a default timeout of 2s on the ports with a TPM. This is
* to work around a bug with certain TPM firmwares that can
* clock stretch for long periods of time and will lock up
* until they are power cycled if a STOP condition is sent
* during this period.
*/
if (dev->type == 0x3)
dt_add_property_cells(bus, "timeout-ms", 2000);
/* XXX: SLCA index? */
}
return 0;
}
static struct dt_node *flash_add_dt_node(struct flash *flash, int id)
{
int i;
int rc;
const char *name;
bool ecc;
struct ffs_handle *ffs;
int ffs_part_num, ffs_part_start, ffs_part_size;
struct dt_node *flash_node;
struct dt_node *partition_container_node;
struct dt_node *partition_node;
flash_node = dt_new_addr(opal_node, "flash", id);
dt_add_property_strings(flash_node, "compatible", "ibm,opal-flash");
dt_add_property_cells(flash_node, "ibm,opal-id", id);
dt_add_property_u64(flash_node, "reg", flash->size);
dt_add_property_cells(flash_node, "ibm,flash-block-size",
flash->block_size);
if (flash->no_erase)
dt_add_property(flash_node, "no-erase", NULL, 0);
/* we fix to 32-bits */
dt_add_property_cells(flash_node, "#address-cells", 1);
dt_add_property_cells(flash_node, "#size-cells", 1);
/* Add partition container node */
partition_container_node = dt_new(flash_node, "partitions");
dt_add_property_strings(partition_container_node, "compatible", "fixed-partitions");
/* we fix to 32-bits */
dt_add_property_cells(partition_container_node, "#address-cells", 1);
dt_add_property_cells(partition_container_node, "#size-cells", 1);
/* Add partitions */
for (i = 0, name = NULL; i < ARRAY_SIZE(part_name_map); i++) {
name = part_name_map[i].name;
rc = ffs_init(0, flash->size, flash->bl, &ffs, 1);
if (rc) {
prerror("FLASH: Can't open ffs handle\n");
continue;
}
rc = ffs_lookup_part(ffs, name, &ffs_part_num);
if (rc) {
/* This is not an error per-se, some partitions
* are purposefully absent, don't spam the logs
*/
prlog(PR_DEBUG, "FLASH: No %s partition\n", name);
continue;
}
rc = ffs_part_info(ffs, ffs_part_num, NULL,
&ffs_part_start, NULL, &ffs_part_size, &ecc);
if (rc) {
prerror("FLASH: Failed to get %s partition info\n", name);
continue;
}
partition_node = dt_new_addr(partition_container_node, "partition", ffs_part_start);
dt_add_property_strings(partition_node, "label", name);
dt_add_property_cells(partition_node, "reg", ffs_part_start, ffs_part_size);
if (part_name_map[i].id != RESOURCE_ID_KERNEL_FW) {
/* Mark all partitions other than the full PNOR and the boot kernel
* firmware as read only. These two partitions are the only partitions
* that are properly erase block aligned at this time.
*/
dt_add_property(partition_node, "read-only", NULL, 0);
}
}
partition_node = dt_new_addr(partition_container_node, "partition", 0);
dt_add_property_strings(partition_node, "label", "PNOR");
dt_add_property_cells(partition_node, "reg", 0, flash->size);
return flash_node;
}
struct dt_node * add_core_common(struct dt_node *cpus,
const struct sppcia_cpu_cache *cache,
const struct sppaca_cpu_timebase *tb,
uint32_t int_server, bool okay)
{
const char *name;
struct dt_node *cpu;
uint32_t version;
uint64_t freq;
const uint8_t pa_features[] = {
6, 0, 0xf6, 0x3f, 0xc7, 0x00, 0x80, 0xc0 };
printf(" Cache: I=%u D=%u/%u/%u/%u\n",
be32_to_cpu(cache->icache_size_kb),
be32_to_cpu(cache->l1_dcache_size_kb),
be32_to_cpu(cache->l2_dcache_size_kb),
be32_to_cpu(cache->l3_dcache_size_kb),
be32_to_cpu(cache->l35_dcache_size_kb));
/* Use the boot CPU PVR to make up a CPU name in the device-tree
* since the HDAT doesn't seem to tell....
*/
version = mfspr(SPR_PVR);
switch(PVR_TYPE(version)) {
case PVR_TYPE_P7:
name = "PowerPC,POWER7";
break;
case PVR_TYPE_P7P:
name = "PowerPC,POWER7+";
break;
case PVR_TYPE_P8E:
case PVR_TYPE_P8:
name = "PowerPC,POWER8";
break;
default:
name = "PowerPC,Unknown";
}
cpu = dt_new_addr(cpus, name, int_server);
assert(cpu);
dt_add_property_string(cpu, "device_type", "cpu");
dt_add_property_string(cpu, "status", okay ? "okay" : "bad");
dt_add_property_cells(cpu, "reg", int_server);
dt_add_property_cells(cpu, "cpu-version", version);
dt_add_property(cpu, "64-bit", NULL, 0);
dt_add_property(cpu, "32-64-bridge", NULL, 0);
dt_add_property(cpu, "graphics", NULL, 0);
dt_add_property(cpu, "general-purpose", NULL, 0);
dt_add_property_cells(cpu, "ibm,processor-segment-sizes",
0x1c, 0x28, 0xffffffff, 0xffffffff);
dt_add_property_cells(cpu, "ibm,processor-page-sizes",
0xc, 0x10, 0x18, 0x22);
/* Page size encodings appear to be the same for P7 and P8 */
dt_add_property_cells(cpu, "ibm,segment-page-sizes",
0x0c, 0x000, 3, 0x0c, 0x0000, /* 4K seg 4k pages */
0x10, 0x0007, /* 4K seg 64k pages */
0x18, 0x0038, /* 4K seg 16M pages */
0x10, 0x110, 2, 0x10, 0x0001, /* 64K seg 64k pages */
0x18, 0x0008, /* 64K seg 16M pages */
0x18, 0x100, 1, 0x18, 0x0000, /* 16M seg 16M pages */
0x22, 0x120, 1, 0x22, 0x0003); /* 16G seg 16G pages */
dt_add_property(cpu, "ibm,pa-features",
pa_features, sizeof(pa_features));
dt_add_property_cells(cpu, "ibm,slb-size", 0x20);
dt_add_property_cells(cpu, "ibm,vmx", 0x2);
dt_add_property_cells(cpu, "ibm,dfp", 0x2);
dt_add_property_cells(cpu, "ibm,purr", 0x1);
dt_add_property_cells(cpu, "ibm,spurr", 0x1);
/*
* Do not create "clock-frequency" if the frequency doesn't
* fit in a single cell
*/
freq = ((uint64_t)be32_to_cpu(tb->actual_clock_speed)) * 1000000ul;
if (freq <= 0xfffffffful)
dt_add_property_cells(cpu, "clock-frequency", freq);
dt_add_property_cells(cpu, "ibm,extended-clock-frequency",
hi32(freq), lo32(freq));
/* FIXME: Hardcoding is bad. */
dt_add_property_cells(cpu, "timebase-frequency", 512000000);
dt_add_property_cells(cpu, "ibm,extended-timebase-frequency",
0, 512000000);
dt_add_property_cells(cpu, "reservation-granule-size",
be32_to_cpu(cache->reservation_size));
dt_add_property_cells(cpu, "d-tlb-size",
be32_to_cpu(cache->dtlb_entries));
dt_add_property_cells(cpu, "i-tlb-size",
be32_to_cpu(cache->itlb_entries));
/* Assume unified TLB */
dt_add_property_cells(cpu, "tlb-size",
be32_to_cpu(cache->dtlb_entries));
dt_add_property_cells(cpu, "d-tlb-sets",
be32_to_cpu(cache->dtlb_assoc_sets));
dt_add_property_cells(cpu, "i-tlb-sets",
be32_to_cpu(cache->itlb_assoc_sets));
dt_add_property_cells(cpu, "tlb-sets",
be32_to_cpu(cache->dtlb_assoc_sets));
dt_add_property_cells(cpu, "d-cache-block-size",
be32_to_cpu(cache->dcache_block_size));
dt_add_property_cells(cpu, "i-cache-block-size",
be32_to_cpu(cache->icache_block_size));
dt_add_property_cells(cpu, "d-cache-size",
be32_to_cpu(cache->l1_dcache_size_kb)*1024);
dt_add_property_cells(cpu, "i-cache-size",
be32_to_cpu(cache->icache_size_kb)*1024);
dt_add_property_cells(cpu, "i-cache-sets",
be32_to_cpu(cache->icache_assoc_sets));
dt_add_property_cells(cpu, "d-cache-sets",
be32_to_cpu(cache->dcache_assoc_sets));
if (cache->icache_line_size != cache->icache_block_size)
dt_add_property_cells(cpu, "i-cache-line-size",
be32_to_cpu(cache->icache_line_size));
if (cache->l1_dcache_line_size != cache->dcache_block_size)
dt_add_property_cells(cpu, "d-cache-line-size",
be32_to_cpu(cache->l1_dcache_line_size));
return cpu;
}
struct dt_node * add_core_common(struct dt_node *cpus,
const struct sppcia_cpu_cache *cache,
const struct sppaca_cpu_timebase *tb,
uint32_t int_server, bool okay)
{
const char *name;
struct dt_node *cpu;
uint32_t version;
uint64_t freq;
const uint8_t pa_features_p7[] = {
6, 0,
0xf6, 0x3f, 0xc7, 0x00, 0x80, 0xc0 };
const uint8_t pa_features_p7p[] = {
6, 0,
0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xc0 };
const uint8_t pa_features_p8[] = {
24, 0,
0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xd0, 0x80, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00,
};
const uint8_t pa_features_p9n_dd20[] = {
64, 0,
0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xd0, 0x80, 0x00, /* 0 .. 7 */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 8 .. 15 */
0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 16 .. 23 */
0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 24 .. 31 */
0x80, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, /* 32 .. 39 */
0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 40 .. 47 */
0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 .. 55 */
0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 56 .. 63 */
};
const uint8_t pa_features_p9[] = {
64, 0,
0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xd0, 0x80, 0x00, /* 0 .. 7 */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 8 .. 15 */
0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 16 .. 23 */
0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 24 .. 31 */
0x80, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, /* 32 .. 39 */
0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 40 .. 47 */
0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 .. 55 */
0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 56 .. 63 */
};
const uint8_t *pa_features;
size_t pa_features_size;
prlog(PR_INFO, " Cache: I=%u D=%u/%u/%u/%u\n",
be32_to_cpu(cache->icache_size_kb),
be32_to_cpu(cache->l1_dcache_size_kb),
be32_to_cpu(cache->l2_dcache_size_kb),
be32_to_cpu(cache->l3_dcache_size_kb),
be32_to_cpu(cache->l35_dcache_size_kb));
/* Use the boot CPU PVR to make up a CPU name in the device-tree
* since the HDAT doesn't seem to tell....
*/
version = mfspr(SPR_PVR);
switch(PVR_TYPE(version)) {
case PVR_TYPE_P7:
name = "PowerPC,POWER7";
pa_features = pa_features_p7;
pa_features_size = sizeof(pa_features_p7);
break;
case PVR_TYPE_P7P:
name = "PowerPC,POWER7+";
pa_features = pa_features_p7p;
pa_features_size = sizeof(pa_features_p7p);
break;
case PVR_TYPE_P8E:
case PVR_TYPE_P8:
case PVR_TYPE_P8NVL:
name = "PowerPC,POWER8";
pa_features = pa_features_p8;
pa_features_size = sizeof(pa_features_p8);
break;
case PVR_TYPE_P9:
case PVR_TYPE_P9P:
name = "PowerPC,POWER9";
if (is_power9n(version) &&
(PVR_VERS_MAJ(version) == 2) &&
(PVR_VERS_MIN(version) == 0)) {
/* P9N DD2.0 */
pa_features = pa_features_p9n_dd20;
pa_features_size = sizeof(pa_features_p9n_dd20);
} else {
pa_features = pa_features_p9;
pa_features_size = sizeof(pa_features_p9);
}
break;
default:
name = "PowerPC,Unknown";
pa_features = NULL;
}
cpu = dt_new_addr(cpus, name, int_server);
assert(cpu);
dt_add_property_string(cpu, "device_type", "cpu");
dt_add_property_string(cpu, "status", okay ? "okay" : "bad");
dt_add_property_cells(cpu, "reg", int_server);
dt_add_property_cells(cpu, "cpu-version", version);
dt_add_property(cpu, "64-bit", NULL, 0);
dt_add_property(cpu, "32-64-bridge", NULL, 0);
dt_add_property(cpu, "graphics", NULL, 0);
dt_add_property(cpu, "general-purpose", NULL, 0);
dt_add_property_cells(cpu, "ibm,processor-segment-sizes",
0x1c, 0x28, 0xffffffff, 0xffffffff);
dt_add_property_cells(cpu, "ibm,processor-page-sizes",
0xc, 0x10, 0x18, 0x22);
if (proc_gen == proc_gen_p9)
dt_add_property_cells(cpu, "ibm,processor-radix-AP-encodings",
0x0000000c, 0xa0000010, 0x20000015, 0x4000001e);
/* Page size encodings appear to be the same for P7 and P8 */
dt_add_property_cells(cpu, "ibm,segment-page-sizes",
0x0c, 0x000, 3, 0x0c, 0x0000, /* 4K seg 4k pages */
0x10, 0x0007, /* 4K seg 64k pages */
0x18, 0x0038, /* 4K seg 16M pages */
0x10, 0x110, 2, 0x10, 0x0001, /* 64K seg 64k pages */
0x18, 0x0008, /* 64K seg 16M pages */
0x18, 0x100, 1, 0x18, 0x0000, /* 16M seg 16M pages */
0x22, 0x120, 1, 0x22, 0x0003); /* 16G seg 16G pages */
if (pa_features) {
dt_add_property(cpu, "ibm,pa-features",
pa_features, pa_features_size);
}
dt_add_property_cells(cpu, "ibm,slb-size", 0x20);
dt_add_property_cells(cpu, "ibm,vmx", 0x2);
dt_add_property_cells(cpu, "ibm,dfp", 0x2);
dt_add_property_cells(cpu, "ibm,purr", 0x1);
dt_add_property_cells(cpu, "ibm,spurr", 0x1);
/*
* Do not create "clock-frequency" if the frequency doesn't
* fit in a single cell
*/
freq = ((uint64_t)be32_to_cpu(tb->actual_clock_speed)) * 1000000ul;
if (freq <= 0xfffffffful)
dt_add_property_cells(cpu, "clock-frequency", freq);
dt_add_property_u64(cpu, "ibm,extended-clock-frequency", freq);
/* FIXME: Hardcoding is bad. */
dt_add_property_cells(cpu, "timebase-frequency", 512000000);
dt_add_property_cells(cpu, "ibm,extended-timebase-frequency",
0, 512000000);
dt_add_property_cells(cpu, "reservation-granule-size",
be32_to_cpu(cache->reservation_size));
dt_add_property_cells(cpu, "d-tlb-size",
be32_to_cpu(cache->dtlb_entries));
dt_add_property_cells(cpu, "i-tlb-size",
be32_to_cpu(cache->itlb_entries));
/* Assume unified TLB */
dt_add_property_cells(cpu, "tlb-size",
be32_to_cpu(cache->dtlb_entries));
dt_add_property_cells(cpu, "d-tlb-sets",
be32_to_cpu(cache->dtlb_assoc_sets));
dt_add_property_cells(cpu, "i-tlb-sets",
be32_to_cpu(cache->itlb_assoc_sets));
dt_add_property_cells(cpu, "tlb-sets",
be32_to_cpu(cache->dtlb_assoc_sets));
dt_add_property_cells(cpu, "d-cache-block-size",
be32_to_cpu(cache->dcache_block_size));
dt_add_property_cells(cpu, "i-cache-block-size",
be32_to_cpu(cache->icache_block_size));
dt_add_property_cells(cpu, "d-cache-size",
be32_to_cpu(cache->l1_dcache_size_kb)*1024);
dt_add_property_cells(cpu, "i-cache-size",
be32_to_cpu(cache->icache_size_kb)*1024);
dt_add_property_cells(cpu, "i-cache-sets",
be32_to_cpu(cache->icache_assoc_sets));
dt_add_property_cells(cpu, "d-cache-sets",
be32_to_cpu(cache->dcache_assoc_sets));
if (cache->icache_line_size != cache->icache_block_size)
dt_add_property_cells(cpu, "i-cache-line-size",
be32_to_cpu(cache->icache_line_size));
if (cache->l1_dcache_line_size != cache->dcache_block_size)
dt_add_property_cells(cpu, "d-cache-line-size",
be32_to_cpu(cache->l1_dcache_line_size));
return cpu;
}
