static int ramdump_module_redraw(WINDOW *win)
{
print_module_title(win, "RAM Dump");
dump_ram(win, cursor * 256, 2, 2);
return 0;
}
int skge_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs)
{
const u32 *r = (const u32 *) regs->data;
int dual = !(regs->data[0x11a] & 1);
dump_pci(regs->data + 0x380);
dump_control(regs->data);
printf("\nBus Management Unit\n");
printf("-------------------\n");
printf("CSR Receive Queue 1 0x%08X\n", r[24]);
printf("CSR Sync Queue 1 0x%08X\n", r[26]);
printf("CSR Async Queue 1 0x%08X\n", r[27]);
if (dual) {
printf("CSR Receive Queue 2 0x%08X\n", r[25]);
printf("CSR Async Queue 2 0x%08X\n", r[29]);
printf("CSR Sync Queue 2 0x%08X\n", r[28]);
}
dump_mac(regs->data);
dump_gmac("GMAC 1", regs->data + 0x2800);
dump_timer("Timer", regs->data + 0x130);
dump_timer("Blink Source", regs->data +0x170);
dump_queue("Receive Queue 1", regs->data +0x400, 1);
dump_queue("Sync Transmit Queue 1", regs->data +0x600, 0);
dump_queue("Async Transmit Queue 1", regs->data +0x680, 0);
dump_ram("Receive RAMbuffer 1", regs->data+0x800);
dump_ram("Sync Transmit RAMbuffer 1", regs->data+0xa00);
dump_ram("Async Transmit RAMbuffer 1", regs->data+0xa80);
dump_fifo("Receive MAC FIFO 1", regs->data+0xc00);
dump_fifo("Transmit MAC FIFO 1", regs->data+0xd00);
if (dual) {
dump_gmac("GMAC 1", regs->data + 0x2800);
dump_queue("Receive Queue 2", regs->data +0x480, 1);
dump_queue("Async Transmit Queue 2", regs->data +0x780, 0);
dump_queue("Sync Transmit Queue 2", regs->data +0x700, 0);
dump_ram("Receive RAMbuffer 2", regs->data+0x880);
dump_ram("Sync Transmit RAMbuffer 2", regs->data+0xb00);
dump_ram("Async Transmit RAMbuffer 21", regs->data+0xb80);
dump_fifo("Receive MAC FIFO 2", regs->data+0xc80);
dump_fifo("Transmit MAC FIFO 2", regs->data+0xd80);
}
dump_timer("Descriptor Poll", regs->data+0xe00);
return 0;
}
// This function will run in a background thread to handle input.
static void *mntr_input_handler(void *arg)
{
while(1) {
gkey = getch();
// n: next opcode
// p: pause execution
// c: continue execution
// s: start execution
// q: quit
// d: dump the ram
// 0: IE0
// 1, IE1
// 2: Timer0
// 3: Timer1
// i: ports input
switch (gkey) {
case 'n' :
pthread_cond_signal(&gcondition);
break;
case 'p' :
pthread_mutex_lock(&glock);
gpause = 1;
pthread_mutex_unlock(&glock);
break;
case 'c' :
pthread_mutex_lock(&glock);
gpause = 0;
pthread_cond_signal(&gcondition);
pthread_mutex_unlock(&glock);
break;
case 's' :
pthread_mutex_lock(&glock);
gstart = 1;
pthread_cond_signal(&gcondition);
pthread_mutex_unlock(&glock);
break;
case 'q' :
pthread_mutex_lock(&glock);
gexit = 1;
pthread_cond_signal(&gcondition);
pthread_mutex_unlock(&glock);
pthread_exit(0);
break;
case 'd' :
{
time_t t;
struct tm *lt;
char file_name[32] = {'\0'};
char *format = "ram-%y-%m-%d-%H-%M-%S.dump";
time(&t);
lt = localtime(&t);
strftime(file_name, 31, format, lt);
dump_ram(gchip, file_name);
show_message("Ram dumped in %s", file_name);
}
break;
case '0' :
ex_interrupt(gchip, 0);
pthread_mutex_lock(&glock);
gneed_update_ui = 1;
pthread_cond_signal(&gcondition);
pthread_mutex_unlock(&glock);
break;
case '1' :
ex_interrupt(gchip, 1);
pthread_mutex_lock(&glock);
gneed_update_ui = 1;
pthread_cond_signal(&gcondition);
pthread_mutex_unlock(&glock);
break;
case '2' :
signal_counter(gchip, 0);
pthread_mutex_lock(&glock);
gneed_update_ui = 1;
pthread_cond_signal(&gcondition);
pthread_mutex_unlock(&glock);
break;
case '3' :
signal_counter(gchip, 1);
pthread_mutex_lock(&glock);
gneed_update_ui = 1;
pthread_cond_signal(&gcondition);
pthread_mutex_unlock(&glock);
break;
case 'i' :
{
int port, data;
echo();
curs_set(1);
nocbreak();
mvprintw(INPUT_POS, "");
clrtoeol();
scanw("%d, %d", &port, &data);
if ((port < 0) || (port > 3) || (data < 0) || (data > 255)) {
LOGE("Invalid port or value: %d, %d", port, data);
} else {
LOGI("Input for port %d, value: %d", port, data);
write_port(gchip, port, data);
}
noecho();
curs_set(0);
cbreak();
}
break;
default :
;
}
update_status();
}
}
int sky2_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs)
{
const u16 *r16 = (const u16 *) regs->data;
const u32 *r32 = (const u32 *) regs->data;
int dual;
dump_pci(regs->data + 0x1c00);
dump_control(regs->data);
printf("\nBus Management Unit\n");
printf("-------------------\n");
printf("CSR Receive Queue 1 0x%08X\n", r32[24]);
printf("CSR Sync Queue 1 0x%08X\n", r32[26]);
printf("CSR Async Queue 1 0x%08X\n", r32[27]);
dual = (regs->data[0x11e] & 2) != 0;
if (dual) {
printf("CSR Receive Queue 2 0x%08X\n", r32[25]);
printf("CSR Async Queue 2 0x%08X\n", r32[29]);
printf("CSR Sync Queue 2 0x%08X\n", r32[28]);
}
dump_mac(regs->data);
dump_prefetch("Status", regs->data + 0xe80);
dump_prefetch("Receive 1", regs->data + 0x450);
dump_prefetch("Transmit 1", regs->data + 0x450 + 0x280);
if (dual) {
dump_prefetch("Receive 2", regs->data + 0x450 + 0x80);
dump_prefetch("Transmit 2", regs->data + 0x450 + 0x380);
}
printf("\nStatus FIFO\n");
printf("\tWrite Pointer 0x%02X\n", regs->data[0xea0]);
printf("\tRead Pointer 0x%02X\n", regs->data[0xea4]);
printf("\tLevel 0x%02X\n", regs->data[0xea8]);
printf("\tWatermark 0x%02X\n", regs->data[0xeac]);
printf("\tISR Watermark 0x%02X\n", regs->data[0xead]);
dump_timer("Status level", regs->data + 0xeb0);
dump_timer("TX status", regs->data + 0xec0);
dump_timer("ISR", regs->data + 0xed0);
printf("\nGMAC control 0x%04X\n", r32[0xf00 >> 2]);
printf("GPHY control 0x%04X\n", r32[0xf04 >> 2]);
printf("LINK control 0x%02hX\n", r16[0xf10 >> 1]);
dump_gmac("GMAC 1", regs->data + 0x2800);
dump_gmac_fifo("Rx GMAC 1", regs->data + 0xc40);
dump_gmac_fifo("Tx GMAC 1", regs->data + 0xd40);
dump_queue2("Receive Queue 1", regs->data +0x400, 1);
dump_queue("Sync Transmit Queue 1", regs->data +0x600, 0);
dump_queue2("Async Transmit Queue 1", regs->data +0x680, 0);
dump_ram("Receive RAMbuffer 1", regs->data+0x800);
dump_ram("Sync Transmit RAMbuffer 1", regs->data+0xa00);
dump_ram("Async Transmit RAMbuffer 1", regs->data+0xa80);
if (dual) {
dump_ram("Receive RAMbuffer 2", regs->data+0x880);
dump_ram("Sync Transmit RAMbuffer 2", regs->data+0xb00);
dump_ram("Async Transmit RAMbuffer 21", regs->data+0xb80);
dump_gmac("GMAC 2", regs->data + 0x3800);
dump_gmac_fifo("Rx GMAC 2", regs->data + 0xc40 + 128);
dump_gmac_fifo("Tx GMAC 2", regs->data + 0xd40 + 128);
}
return 0;
}
