static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci)
{
int ret = 0;
ret = dwc3_core_init(fsl_xhci->dwc3_reg);
if (ret) {
debug("%s:failed to initialize core\n", __func__);
return ret;
}
/* We are hard-coding DWC3 core to Host Mode */
dwc3_set_mode(fsl_xhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
/* Set GFLADJ_30MHZ as 20h as per XHCI spec default value */
dwc3_set_fladj(fsl_xhci->dwc3_reg, GFLADJ_30MHZ_DEFAULT);
/* Change beat burst and outstanding pipelined transfers requests */
fsl_xhci_set_beat_burst_length(fsl_xhci->dwc3_reg);
/*
* A-010151: The dwc3 phy TSMC 28-nm HPM 0.9/1.8 V does not
* reliably support Rx Detect in P3 mode(P3 is the default
* setting). Therefore, some USB3.0 devices may not be detected
* reliably in Super Speed mode. So, USB controller to configure
* USB in P2 mode whenever the Receive Detect feature is required.
* whenever the Receive Detect feature is required.
*/
if (has_erratum_a010151())
clrsetbits_le32(&fsl_xhci->dwc3_reg->g_usb3pipectl[0],
DWC3_GUSB3PIPECTL_DISRXDETP3,
DWC3_GUSB3PIPECTL_DISRXDETP3);
return ret;
}
static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci)
{
int ret = 0;
ret = dwc3_core_init(fsl_xhci->dwc3_reg);
if (ret) {
debug("%s:failed to initialize core\n", __func__);
return ret;
}
/* We are hard-coding DWC3 core to Host Mode */
dwc3_set_mode(fsl_xhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
/* Set GFLADJ_30MHZ as 20h as per XHCI spec default value */
dwc3_set_fladj(fsl_xhci->dwc3_reg, GFLADJ_30MHZ_DEFAULT);
return ret;
}
