static void __init timer_init(void)
{
unsigned long timer_base = (unsigned long)ioremap(REG_BASE_TIMER0, SZ_4K);
unsigned long ctrl = TIMER_CTRL_32BIT | TIMER_CTRL_IE;
enable_timer_clk();
writel(0, timer_base + TIMER_CTRL);
sp804_clockevents_init((void *) timer_base, IRQ_TIMER0);
writel(0, timer_base + TIMER_CTRL);
writel(ctrl, timer_base + TIMER_CTRL);
writel(TIMER_RELOAD, timer_base + TIMER_LOAD);
ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
writel(ctrl, timer_base + TIMER_CTRL);
/* free run timer in TIMER5 */
free_timer_overflows = 0;
freerun_timer_init((void *) timer_base + 0x20, IRQ_TIMER1);
iomapped = 1;
edb_trace(1);
}
static int __init godnet_clocksource_init(void)
{
unsigned long rate = timer1_clk_khz * 1000;
#ifdef CONFIG_LOCAL_TIMERS
twd_base = (void *)IO_ADDRESS(REG_BASE_A9_PERI) + REG_SC_LOCAL_TIMER;
edb_trace();
edb_putstr("twd_base :\n");
edb_puthex((int)twd_base);
edb_putstr("\n");
#endif
writel(0, CFG_TIMER_VABASE + REG_TIMER1_CONTROL);
writel(0xffffffff, CFG_TIMER_VABASE + REG_TIMER1_RELOAD);
writel(0xffffffff, CFG_TIMER_VABASE + REG_TIMER1_VALUE);
writel(CFG_TIMER_CONTROL, CFG_TIMER_VABASE + REG_TIMER1_CONTROL);
/* caculate the mult/shift by clock rate to gain more accratury */
if (clocksource_register_hz(&godnet_clocksource, rate))
panic("register clocksouce :%s error\n",
godnet_clocksource.name);
/* force check the mult/shift of clocksource */
init_fixed_sched_clock(&cd, godnet_update_sched_clock, 32, rate,
godnet_clocksource.mult, godnet_clocksource.shift);
return 0;
}
static void timer_set_mode(enum clock_event_mode mode,
struct clock_event_device *clk)
{
unsigned long ctrl;
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
writel(0, CFG_TIMER_VABASE + REG_TIMER_CONTROL);
writel(godarm_timer_reload,
CFG_TIMER_VABASE + REG_TIMER_RELOAD);
writel(CFG_TIMER_CONTROL,
CFG_TIMER_VABASE + REG_TIMER_CONTROL);
edb_trace();
break;
case CLOCK_EVT_MODE_ONESHOT:
writel((CFG_TIMER_32BIT | CFG_TIMER_ONESHOT),
CFG_TIMER_VABASE + REG_TIMER_CONTROL);
break;
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
default:
ctrl = readl(CFG_TIMER_VABASE + REG_TIMER_CONTROL);
ctrl &= ~CFG_TIMER_ENABLE;
writel(ctrl, CFG_TIMER_VABASE + REG_TIMER_CONTROL);
}
}
void __init platform_smp_prepare_cpus(unsigned int max_cpus)
{
unsigned int ncores = get_core_count();
unsigned long addr;
int i;
edb_trace(1);
edb_putstr("smp_prepare_cpus\n");
/* sanity check */
if (ncores == 0) {
printk(KERN_ERR
"hisik3: strange CM count of 0? Default to 1\n");
ncores = 1;
}
if (ncores > NR_CPUS) {
printk(KERN_WARNING
"hisik3: no. of cores (%d) greater than configured "
"maximum of %d - clipping\n",
ncores, NR_CPUS);
ncores = NR_CPUS;
}
/*
* are we trying to boot more cores than exist?
*/
if (max_cpus > ncores) {
WARN(1, "hisik3: smp max cpus should NOT more cores than exist\n");
max_cpus = ncores;
}
/*
* Initialise the present map, which describes the set of CPUs
* actually populated at the present time.
*/
for (i = 0; i < max_cpus; i++)
set_cpu_present(i, true);
scu_enable(scu_base_addr());
addr = (unsigned long) IO_ADDRESS(MEMORY_AXI_SECOND_CPU_BOOT_ADDR);
printk("poke_milo addr 0x%lx at 0x%x\n", addr, virt_to_phys(k3v2_secondary_startup));
/*
* Write the address of secondary startup into the system-wide flags
* register. The BootMonitor waits for this register to become
* non-zero.
*/
writel(BSYM(virt_to_phys(k3v2_secondary_startup)), addr);
wmb();
flush_cache_all();
edb_putstr("smp_prepare_cpus out\n");
}
static int __init __system_timer_init(void)
{
clk_register(&timer1_clk);
edb_trace(1);
return 0;
}
void __init godarm_gic_init_irq(void)
{
edb_trace();
godarm_gic_cpu_base_addr = (void __iomem *)CFG_GIC_CPU_BASE;
gic_init(0, GODARM_IRQ_START, (void __iomem *)CFG_GIC_DIST_BASE,
(void __iomem *)CFG_GIC_CPU_BASE);
}
static void __init godarm_timer_init(void){
edb_trace();
setup_irq(TIMER01_IRQ, &godarm_timer_irq);
setup_irq(TIMER01_IRQ, &godarm_freetimer_irq);
godarm_clocksource_init();
timer0_clockevent.mult =
div_sc(timer0_clk_hz, NSEC_PER_SEC, timer0_clockevent.shift);
timer0_clockevent.max_delta_ns =
clockevent_delta2ns(0xffffffff, &timer0_clockevent);
timer0_clockevent.min_delta_ns =
clockevent_delta2ns(0xf, &timer0_clockevent);
timer0_clockevent.cpumask = cpumask_of(0);
clockevents_register_device(&timer0_clockevent);
edb_trace();
}
static int __init amba_gpio_dev_init(void)
{
int i;
int ret = -1;
edb_trace(1);
for (i = 0; i < ARRAY_SIZE(amba_gpio_devs); i++) {
struct amba_device *d = amba_gpio_devs[i];
ret = amba_device_register(d, &iomem_resource);
if (ret != 0) {
break;
}
}
edb_trace(1);
return ret;
}
static void early_init(void)
{
unsigned long busclk;
edb_trace();
busclk = get_bus_clk();
godarm_timer_reload = BUSCLK_TO_TIMER_RELOAD(busclk);
timer0_clk_hz = BUSCLK_TO_TIMER0_CLK_HZ(busclk);
timer0_clk_khz = BUSCLK_TO_TIMER0_CLK_KHZ(busclk);
timer1_clk_hz = BUSCLK_TO_TIMER1_CLK_HZ(busclk);
timer1_clk_khz = BUSCLK_TO_TIMER1_CLK_KHZ(busclk);
}
void __init godarm_init(void)
{
unsigned long i;
unsigned long reg;
unsigned long busclk;
edb_trace();
/* godarm uart use apb bus clk */
reg = readl(IO_ADDRESS(CRG_BASE + 0xe4));
reg &= ~UART_CKSEL_APB;
writel(reg, IO_ADDRESS(CRG_BASE + 0xe4));
busclk = get_bus_clk();
uart_clk_init(busclk);
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
edb_trace();
amba_device_register(amba_devs[i], &iomem_resource);
}
}
static void __init init_machine(void)
{
edb_trace(1);
#warning "add some sys ctrl register operation here, such as enable something .etc"
cache_init();
#warning "don't replace arm_pm_restart funciton if pm.c is built into boot image "
arm_pm_restart = board_arch_reset;
lm_device_register(&usb_sft_otg);
return;
}
static void __init cache_init(void)
{
#ifdef CONFIG_CACHE_L2X0
void __iomem *p = (void *)IO_ADDRESS(REG_BASE_L2CC);
edb_trace(1);
writel_relaxed(L2X0_DYNAMIC_CLK_GATING_EN|L2X0_STNDBY_MODE_EN,
p+L2X0_POWER_CTRL);
/*
* 64K * 16 Way = 1024MB
*/
/*l2x0_init(p, 0x76070000, 0x8B000fff);*/
l2x0_init(p, 0x3cc70000, 0xc0000fff);
#endif
}
void __init godnet_gic_init_irq(void)
{
edb_trace();
godnet_gic_cpu_base_addr = (void __iomem *)CFG_GIC_CPU_BASE;
#ifndef CONFIG_LOCAL_TIMERS
gic_init(0, GODNET_IRQ_START, (void __iomem *)CFG_GIC_DIST_BASE,
(void __iomem *)CFG_GIC_CPU_BASE);
#else
/* git initialed include Local timer.
* IRQ_LOCALTIMER is settled IRQ number for local timer interrupt.
* It is set to 29 by ARM.
*/
gic_init(0, IRQ_LOCALTIMER, (void __iomem *)CFG_GIC_DIST_BASE,
(void __iomem *)CFG_GIC_CPU_BASE);
#endif
}
void __init godarm_map_io(void)
{
int i;
iotable_init(godarm_io_desc, ARRAY_SIZE(godarm_io_desc));
for (i = 0; i < ARRAY_SIZE(godarm_io_desc); i++) {
edb_putstr(" V: "); edb_puthex(godarm_io_desc[i].virtual);
edb_putstr(" P: "); edb_puthex(godarm_io_desc[i].pfn);
edb_putstr(" S: "); edb_puthex(godarm_io_desc[i].length);
edb_putstr(" T: "); edb_putul(godarm_io_desc[i].type);
edb_putstr("\n");
}
early_init();
edb_trace();
}
void __init k3v2_allocate_memory_regions(void)
{
unsigned long reserved_base = HISI_BASE_MEMORY_SIZE;
unsigned long reserved_size;
unsigned long size;
edb_trace(1);
reserved_size = hisi_get_reserve_mem_size();
reserved_base -= (reserved_size - SZ_1M);
/* GPU memory */
size = hisi_media_mem.gpu_size;
hisi_reserved_gpu_phymem = reserved_base;
printk("ion allocating %lu bytes at (%lx physical) for gpu "
"pmem area\n", size, reserved_base);
reserved_base += size;
/* CODEC memory */
size = hisi_media_mem.codec_size;
/*Revived by y44207 ,V200 64 byte align*/
hisi_reserved_codec_phymem = reserved_base;
printk("codec ion allocating %lu bytes at (%lx physical) for codec "
"pcodec area\n", size, reserved_base);
reserved_base += size;
/* VPP memory */
size = hisi_media_mem.vpp_size;
hisi_reserved_vpp_phymem = reserved_base;
printk("vpp ion allocating %lu bytes at (%lx physical) for vpp "
"pmem area\n", size, reserved_base);
reserved_base += size;
/* CAMERA memory pmem */
size = hisi_media_mem.camera_size;
if (size) {
k3v2_ion_data.heaps[0].base = reserved_base;
k3v2_ion_data.heaps[0].size = size;
hisi_reserved_camera_phymem = k3v2_ion_data.heaps[0].base;
printk("camera ion allocating %lu bytes at (%lx physical) for camera pic\n",
size, reserved_base);
}
reserved_base += size;
/* video decoder display && camera preview + Thumbnail */
size = hisi_media_mem.gralloc_size;
if (size) {
k3v2_ion_data.heaps[1].base = reserved_base;
k3v2_ion_data.heaps[1].size = size;
printk("camera ion allocating %lu bytes at (%lx physical) for gralloc "
"pmem area\n", size, reserved_base);
}
reserved_base += size;
#if defined(CONFIG_OVERLAY_COMPOSE)
size = hisi_media_mem.overlay_size;
if (size) {
k3v2_ion_data.heaps[2].base = reserved_base;
k3v2_ion_data.heaps[2].size = size;
printk("overlay ion allocating %lu bytes at (%lx physical) for overlay "
"pmem area\n", size, reserved_base);
}
reserved_base += size;
#endif
/*FB memory*/
size = hisi_media_mem.fb_size;
hisi_reserved_fb_phymem = reserved_base;
printk("fb ion allocating %lu bytes at (%lx physical) for fb "
"pmem area\n",size,reserved_base);
reserved_base += size;
/* dumplog memory */
//size = HISI_PMEM_DUMPLOG_SIZE;
/*Revived by y44207 ,V200 64 byte align*/
//hisi_reserved_dumplog_phymem = reserved_base;
//printk("dumplog ion allocating %lu bytes at (%lx physical) for dumplog"
// "area\n", size, reserved_base);
//reserved_base += size;
}