/***************
* Generate code for vector "store" operations.
* The tree e must look like:
* (op1 OPvecsto (op OPparam op2))
* where op is the store instruction STOxxxx.
*/
code *cdvecsto(elem *e, regm_t *pretregs)
{
//printf("cdvecsto()\n");
//elem_print(e);
elem *op1 = e->E1;
elem *op2 = e->E2->E2;
elem *eop = e->E2->E1;
unsigned op = el_tolong(eop);
#ifdef DEBUG
assert(isXMMstore(op));
#endif
return xmmeq(e, op, op1, op2, pretregs);
}
void WReqn(elem *e)
{ static int nest;
if (!e)
return;
if (OTunary(e->Eoper))
{
WROP(e->Eoper);
if (OTbinary(e->E1->Eoper))
{ nest++;
ferr("(");
WReqn(e->E1);
ferr(")");
nest--;
}
else
WReqn(e->E1);
}
else if (e->Eoper == OPcomma && !nest)
{ WReqn(e->E1);
dbg_printf(";\n\t");
WReqn(e->E2);
}
else if (OTbinary(e->Eoper))
{
if (OTbinary(e->E1->Eoper))
{ nest++;
ferr("(");
WReqn(e->E1);
ferr(")");
nest--;
}
else
WReqn(e->E1);
ferr(" ");
WROP(e->Eoper);
if (e->Eoper == OPstreq)
dbg_printf("%ld",(long)type_size(e->ET));
ferr(" ");
if (OTbinary(e->E2->Eoper))
{ nest++;
ferr("(");
WReqn(e->E2);
ferr(")");
nest--;
}
else
WReqn(e->E2);
}
else
{
switch (e->Eoper)
{ case OPconst:
switch (tybasic(e->Ety))
{
case TYfloat:
dbg_printf("%g <float> ",e->EV.Vfloat);
break;
case TYdouble:
dbg_printf("%g ",e->EV.Vdouble);
break;
case TYldouble:
dbg_printf("%Lg ",e->EV.Vldouble);
break;
case TYcent:
case TYucent:
dbg_printf("%lld+%lld ", e->EV.Vcent.msw, e->EV.Vcent.lsw);
break;
default:
dbg_printf("%lld ",el_tolong(e));
break;
}
break;
case OPrelconst:
ferr("#");
/* FALL-THROUGH */
case OPvar:
dbg_printf("%s",e->EV.sp.Vsym->Sident);
if (e->EV.sp.Vsym->Ssymnum != -1)
dbg_printf("(%d)",e->EV.sp.Vsym->Ssymnum);
if (e->Eoffset != 0)
{
if (sizeof(e->Eoffset) == 8)
dbg_printf(".x%llx", e->Eoffset);
else
dbg_printf(".%ld",(long)e->Eoffset);
}
break;
case OPasm:
case OPstring:
dbg_printf("\"%s\"",e->EV.ss.Vstring);
if (e->EV.ss.Voffset)
dbg_printf("+%ld",(long)e->EV.ss.Voffset);
break;
case OPmark:
case OPgot:
case OPframeptr:
case OPhalt:
WROP(e->Eoper);
break;
case OPstrthis:
break;
default:
WROP(e->Eoper);
assert(0);
}
}
}
code *cdvector(elem *e, regm_t *pretregs)
{
/* e should look like one of:
* vector
* |
* param
* / \
* param op2
* / \
* op op1
*/
if (!config.fpxmmregs)
{ printf("SIMD operations not supported on this platform\n");
exit(1);
}
unsigned n = el_nparams(e->E1);
elem **params = (elem **)malloc(n * sizeof(elem *));
assert(params);
elem **tmp = params;
el_paramArray(&tmp, e->E1);
#if 0
printf("cdvector()\n");
for (int i = 0; i < n; i++)
{
printf("[%d]: ", i);
elem_print(params[i]);
}
#endif
if (*pretregs == 0)
{ /* Evaluate for side effects only
*/
CodeBuilder cdb;
for (int i = 0; i < n; i++)
{
cdb.append(codelem(params[i], pretregs, FALSE));
*pretregs = 0; // in case they got set
}
return cdb.finish();
}
assert(n >= 2 && n <= 4);
elem *eop = params[0];
elem *op1 = params[1];
elem *op2 = NULL;
tym_t ty2 = 0;
if (n >= 3)
{ op2 = params[2];
ty2 = tybasic(op2->Ety);
}
unsigned op = el_tolong(eop);
#ifdef DEBUG
assert(!isXMMstore(op));
#endif
tym_t ty1 = tybasic(op1->Ety);
unsigned sz1 = _tysize[ty1];
// assert(sz1 == 16); // float or double
regm_t retregs;
CodeBuilder cdb;
if (n == 3 && ty2 == TYuchar && op2->Eoper == OPconst)
{ // Handle: op xmm,imm8
retregs = *pretregs & XMMREGS;
if (!retregs)
retregs = XMMREGS;
cdb.append(codelem(op1,&retregs,FALSE)); // eval left leaf
unsigned reg = findreg(retregs);
int r;
switch (op)
{
case PSLLD: r = 6; op = 0x660F72; break;
case PSLLQ: r = 6; op = 0x660F73; break;
case PSLLW: r = 6; op = 0x660F71; break;
case PSRAD: r = 4; op = 0x660F72; break;
case PSRAW: r = 4; op = 0x660F71; break;
case PSRLD: r = 2; op = 0x660F72; break;
case PSRLQ: r = 2; op = 0x660F73; break;
case PSRLW: r = 2; op = 0x660F71; break;
case PSRLDQ: r = 3; op = 0x660F73; break;
case PSLLDQ: r = 7; op = 0x660F73; break;
default:
printf("op = x%x\n", op);
assert(0);
break;
}
cdb.append(getregs(retregs));
cdb.genc2(op,modregrmx(3,r,reg-XMM0), el_tolong(op2));
}
else if (n == 2)
{ /* Handle: op xmm,mem
* where xmm is written only, not read
*/
code cs;
if ((op1->Eoper == OPind && !op1->Ecount) || op1->Eoper == OPvar)
{
cdb.append(getlvalue(&cs, op1, RMload)); // get addressing mode
}
else
{
regm_t rretregs = XMMREGS;
cdb.append(codelem(op1, &rretregs, FALSE));
unsigned rreg = findreg(rretregs) - XMM0;
cs.Irm = modregrm(3,0,rreg & 7);
cs.Iflags = 0;
cs.Irex = 0;
if (rreg & 8)
cs.Irex |= REX_B;
}
retregs = *pretregs & XMMREGS;
if (!retregs)
retregs = XMMREGS;
unsigned reg;
cdb.append(allocreg(&retregs, ®, e->Ety));
code_newreg(&cs, reg - XMM0);
cs.Iop = op;
cdb.gen(&cs);
}
else if (n == 3 || n == 4)
{ /* Handle:
* op xmm,mem // n = 3
* op xmm,mem,imm8 // n = 4
* Both xmm and mem are operands, evaluate xmm first.
*/
code cs;
retregs = *pretregs & XMMREGS;
if (!retregs)
retregs = XMMREGS;
cdb.append(codelem(op1,&retregs,FALSE)); // eval left leaf
unsigned reg = findreg(retregs);
if ((op2->Eoper == OPind && !op2->Ecount) || op2->Eoper == OPvar)
{
cdb.append(getlvalue(&cs, op2, RMload | retregs)); // get addressing mode
}
else
{
unsigned rretregs = XMMREGS & ~retregs;
cdb.append(scodelem(op2, &rretregs, retregs, TRUE));
unsigned rreg = findreg(rretregs) - XMM0;
cs.Irm = modregrm(3,0,rreg & 7);
cs.Iflags = 0;
cs.Irex = 0;
if (rreg & 8)
cs.Irex |= REX_B;
}
cdb.append(getregs(retregs));
if (n == 4)
{
switch (op)
{
case CMPPD: case CMPSS: case CMPSD: case CMPPS:
case PSHUFD: case PSHUFHW: case PSHUFLW:
case BLENDPD: case BLENDPS: case DPPD: case DPPS:
case MPSADBW: case PBLENDW:
case ROUNDPD: case ROUNDPS: case ROUNDSD: case ROUNDSS:
case SHUFPD: case SHUFPS:
break;
default:
printf("op = x%x\n", op);
assert(0);
break;
}
elem *imm8 = params[3];
cs.IFL2 = FLconst;
cs.IEV2.Vsize_t = el_tolong(imm8);
}
code_newreg(&cs, reg - XMM0);
cs.Iop = op;
cdb.gen(&cs);
}
else
assert(0);
cdb.append(fixresult(e,retregs,pretregs));
free(params);
freenode(e);
return cdb.finish();
}
void WReqn(elem *e)
{ static int nest;
if (!e)
return;
if (OTunary(e->Eoper))
{
WROP(e->Eoper);
if (OTbinary(e->E1->Eoper))
{ nest++;
ferr("(");
WReqn(e->E1);
ferr(")");
nest--;
}
else
WReqn(e->E1);
}
else if (e->Eoper == OPcomma && !nest)
{ WReqn(e->E1);
dbg_printf(";\n\t");
WReqn(e->E2);
}
else if (OTbinary(e->Eoper))
{
if (OTbinary(e->E1->Eoper))
{ nest++;
ferr("(");
WReqn(e->E1);
ferr(")");
nest--;
}
else
WReqn(e->E1);
ferr(" ");
WROP(e->Eoper);
if (e->Eoper == OPstreq)
dbg_printf("%ld",e->Enumbytes);
ferr(" ");
if (OTbinary(e->E2->Eoper))
{ nest++;
ferr("(");
WReqn(e->E2);
ferr(")");
nest--;
}
else
WReqn(e->E2);
}
else
{
switch (e->Eoper)
{ case OPconst:
switch (tybasic(e->Ety))
{
case TYfloat:
dbg_printf("%g <float> ",e->EV.Vfloat);
break;
case TYdouble:
dbg_printf("%g ",e->EV.Vdouble);
break;
default:
dbg_printf("%lld ",el_tolong(e));
break;
}
break;
case OPrelconst:
ferr("#");
/* FALL-THROUGH */
case OPvar:
dbg_printf("%s",e->EV.sp.Vsym->Sident);
if (e->EV.sp.Vsym->Ssymnum != -1)
dbg_printf("(%d)",e->EV.sp.Vsym->Ssymnum);
if (e->Eoffset != 0)
dbg_printf(".%ld",e->Eoffset);
break;
case OPasm:
#if TARGET_MAC
if (e->Eflags & EFsmasm)
{
if (e->EV.mac.Vasmdat[1])
dbg_printf("\"%c%c\"",e->EV.mac.Vasmdat[0],e->EV.mac.Vasmdat[1]);
else
dbg_printf("\"%c\"",e->EV.mac.Vasmdat[0]);
break;
};
#endif
case OPstring:
dbg_printf("\"%s\"",e->EV.ss.Vstring);
if (e->EV.ss.Voffset)
dbg_printf("+%ld",e->EV.ss.Voffset);
break;
case OPmark:
case OPgot:
case OPframeptr:
WROP(e->Eoper);
break;
case OPstrthis:
break;
default:
WROP(e->Eoper);
assert(0);
}
}
}