int mtk_xhci_ip_init(struct usb_hcd *hcd, struct xhci_hcd *xhci)
{
mtk_xhci_set(hcd, xhci);
#ifdef CONFIG_MTK_FPGA
u3_base = xhci->base_regs;
u3_sif_base = xhci->sif_regs;
u3_sif2_base = xhci->sif2_regs;
i2c1_base = ioremap(0x11008000, 0x1000);
if (!(i2c1_base)) {
pr_err("Can't remap I2C1 BASE\n");
}
printk("%s(%d): i2c1_base, logic x%x, phys 0x%p\n", __func__, __LINE__, 0x11008000, (void *)i2c1_base);
#endif
#ifdef CONFIG_MTK_LDVT
mt_set_gpio_mode(121, 4);
#endif
/* phy initialization is done by device, if target runs on dual mode */
#ifndef CONFIG_USB_MTK_DUALMODE
mtk_xhci_phy_init(0, NULL);
enableAllClockPower(xhci, 1); /* host do reset ip */
#else
enableAllClockPower(xhci, 1); /* device do reset ip */
#endif
setLatchSel(xhci);
mtk_xhci_ck_timer_init(xhci);
mtk_xhci_scheduler_init();
return 0;
}
int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
{
u3phy_init();
mt7621_phy_init(u3phy);
enableAllClockPower();
u2_slew_rate_calibration(u3phy);
u2_slew_rate_calibration(u3phy_p1);
*hccr = (uint32_t)XHC_IO_START;
*hcor = (struct xhci_hcor *)((uint32_t) *hccr
+ HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
debug("mtk-xhci: init hccr %x and hcor %x hc_length %d\n",
(uint32_t)*hccr, (uint32_t)*hcor,
(uint32_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
return 0;
}
void reinitIP(void)
{
enableAllClockPower();
}
