static ssize_t dpidle_state_store(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, size_t n) { char cmd[32]; int param; if (sscanf(buf, "%s %d", cmd, ¶m) == 2) { if (!strcmp(cmd, "dpidle")) { idle_switch[IDLE_TYPE_DP] = param; } else if (!strcmp(cmd, "enable")) { enable_dpidle_by_bit(param); } else if (!strcmp(cmd, "disable")) { disable_dpidle_by_bit(param); } else if (!strcmp(cmd, "time")) { dpidle_time_critera = param; }else if (!strcmp(cmd, "bypass")) { dpidle_by_pass_cg = param; } return n; } else if (sscanf(buf, "%d", ¶m) == 1) { idle_switch[IDLE_TYPE_DP] = param; return n; } return -EINVAL; }
static ssize_t dpidle_state_store(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, size_t n) { char cmd[32]; int param; if (sscanf(buf, "%s %d", cmd, ¶m) == 2) { if (!strcmp(cmd, "dpidle")) { idle_switch[IDLE_TYPE_DP] = param; } else if (!strcmp(cmd, "enable")) { enable_dpidle_by_bit(param); } else if (!strcmp(cmd, "disable")) { disable_dpidle_by_bit(param); } else if (!strcmp(cmd, "cpupdn")) { dpidle_cpu_pdn = !!param; } else if (!strcmp(cmd, "time")) { dpidle_time_critera = param; } else if (!strcmp(cmd, "block_time")) { dpidle_block_time_critera = param; } else if (!strcmp(cmd, "bypass")) { memset(dpidle_condition_mask, 0, NR_GRPS * sizeof(unsigned int)); } return n; } else if (sscanf(buf, "%d", ¶m) == 1) { idle_switch[IDLE_TYPE_DP] = param; return n; } return -EINVAL; }
static int _mt_combo_plt_do_deep_idle(COMBO_IF src, int enter) { int ret = -1; const char *combo_if_name[] = { "COMBO_IF_UART", "COMBO_IF_MSDC" }; if(src != COMBO_IF_UART && src!= COMBO_IF_MSDC){ CMB_STUB_LOG_WARN("src = %d is error\n", src); return ret; } if(src >= 0 && src < COMBO_IF_MAX){ CMB_STUB_LOG_INFO("src = %s, to enter deep idle? %d \n", combo_if_name[src], enter); } /*TODO: For Common SDIO configuration, we need to do some judgement between STP and WIFI to decide if the msdc will enter deep idle safely*/ switch(src){ case COMBO_IF_UART: if(enter == 0){ //clr_device_working_ability(MT65XX_PDN_PERI_UART3, DEEP_IDLE_STATE); disable_dpidle_by_bit(MT65XX_PDN_PERI_UART2); } else { //set_device_working_ability(MT65XX_PDN_PERI_UART3, DEEP_IDLE_STATE); enable_dpidle_by_bit(MT65XX_PDN_PERI_UART2); } ret = 0; break; case COMBO_IF_MSDC: if(enter == 0){ //clr_device_working_ability(MT65XX_PDN_PERI_MSDC2, DEEP_IDLE_STATE); } else { //set_device_working_ability(MT65XX_PDN_PERI_MSDC2, DEEP_IDLE_STATE); } ret = 0; break; default: ret = -1; break; } return ret; }
void AudDrv_Emi_Clk_Off(void) { mutex_lock(&auddrv_pmic_mutex); Aud_EMI_cntr--; if(Aud_EMI_cntr ==0) { enable_dpidle_by_bit(MT_CG_AUDIO_AFE); enable_soidle_by_bit(MT_CG_AUDIO_AFE); } if(Aud_EMI_cntr <0 ) { Aud_EMI_cntr = 0; printk("Aud_EMI_cntr = %d \n",Aud_EMI_cntr); } mutex_unlock(&auddrv_pmic_mutex); }
//-------------------------------- //- Init Funcs //-------------------------------- //- bit 0: ARMPLL SSC default on //- bit 1: MAINPLL SSC default on INT32 freqhop_init(UINT32 option) { UINT32 id, dds_con1; UINT32 reg_con0,reg_con1; if (freqhop_initiated) return FHCTL_SUCCESS; freqhop_initiated = 1; //fhctl_write_reg(1, DMA_GLOBAL_SEC_EN); fhctl_info ("Initial Frequency Hopping Driver\n"); //- ungate fhctl clock enable_clock (MT_CG_FHCTL_SW_CG, "FHCTL"); enable_dpidle_by_bit(MT_CG_FHCTL_SW_CG); //- must check pllx_con1 dds is equal to fhctl_ seeting for(id=ARMPLL_ID; id<NUM_OF_PLL_ID; id++) { FHCTL_LOCK; dds_con1 = fhctl_read_reg(pll_con1_addr[id]); reg_con0 = fhctl_read_reg(pll_con0[id]); reg_con1 = fhctl_read_reg(pll_con1_addr[id]); //- re-fill setting from PLL_CON1 freqhop_pll_settings[id][0].dds_val = reg_con1 & RG_FHCTLx_DDS_MASK; freqhop_fill_setting_from_dds ((dds_con1 & RG_FHCTLx_DDS_MASK), &(freqhop_pll_settings[id][0])); if (option & (1 << id)) { //- SSC default on ??? freqhop_fhctlx_enable (id, FHCTL_SM | FHCTL_SSC, &(freqhop_pll_settings[id][0])); } FHCTL_UNLOCK; fhctl_info("%s pll_con0 ori = 0x%08X\n", pllid_to_pllname[id], reg_con0); fhctl_info("%s pll_con1 ori = 0x%08X\n", pllid_to_pllname[id], reg_con1); } return FHCTL_SUCCESS; }
void AudDrv_Emi_Clk_Off(void) { mutex_lock(&auddrv_pmic_mutex); Aud_EMI_cntr--; if(Aud_EMI_cntr ==0) { #ifndef CONFIG_FPGA_EARLY_PORTING //george early porting disable enable_dpidle_by_bit(MT_CG_AUDIO_AFE); enable_soidle_by_bit(MT_CG_AUDIO_AFE); #endif } if(Aud_EMI_cntr <0 ) { Aud_EMI_cntr = 0; pr_warn("Aud_EMI_cntr = %d \n",Aud_EMI_cntr); } mutex_unlock(&auddrv_pmic_mutex); }
static ssize_t dpidle_state_write(struct file *filp, const char __user *userbuf, size_t count, loff_t *f_pos) { char cmd[32]; int param; count = min(count, sizeof(cmd_buf) - 1); if (copy_from_user(cmd_buf, userbuf, count)) { return -EFAULT; } cmd_buf[count] = '\0'; if (sscanf(cmd_buf, "%s %d", cmd, ¶m) == 2) { if (!strcmp(cmd, "dpidle")) { idle_switch[IDLE_TYPE_DP] = param; } else if (!strcmp(cmd, "enable")) { enable_dpidle_by_bit(param); } else if (!strcmp(cmd, "disable")) { disable_dpidle_by_bit(param); } else if (!strcmp(cmd, "time")) { dpidle_time_critera = param; }else if (!strcmp(cmd, "bypass")) { dpidle_by_pass_cg = param; printk(KERN_WARNING"bypass = %d\n", dpidle_by_pass_cg); } return count; } else if (sscanf(cmd_buf, "%d", ¶m) == 1) { idle_switch[IDLE_TYPE_DP] = param; return count; } return -EINVAL; }
static ssize_t dpidle_state_store(struct kobject *kobj, struct kobj_attribute *attr,const char *buf, size_t n) { char command[32]; #ifdef PROFILE_IDLE char sec_cmd[32]; int i = 0; #endif int temp; #ifdef PROFILE_IDLE if (sscanf(buf, "%s %s %x", command, sec_cmd, &temp) == 3) { if (!strcmp(command, "profile")) { if (!strcmp(sec_cmd, "on")) { idle_profile_mask |= temp; for (i = 0; i < nr_cpu_ids; i++) { //memset(idle_profile_idx, 0, NR_CPUS * sizeof(int)); if (temp & (0x1 << i)) { idle_profile_idx[i] = 0; } } } else if (!strcmp(sec_cmd, "off")) { idle_profile_mask &= ~temp; } } printk("[test]idle_profile_mask=0x%x\n", idle_profile_mask); } else #endif if (sscanf(buf, "%s %d", command, &temp) == 2) { if (!strcmp(command, "idle")) { idle_switch = temp; } else if (!strcmp(command, "dpidle")) { dpidle_switch = temp; } else if (!strcmp(command, "level")) { if (unlikely(temp < 0 || temp > 2)) { dcm_warn("[%s]invalid dpidle_level %d\n", __func__, temp); } else { dpidle_level = (unsigned int)temp; } } else if (!strcmp(command, "time")) { dpidle_time_critera = temp; } else if (!strcmp(command, "enable")) { enable_dpidle_by_bit(temp); } else if (!strcmp(command, "disable")) { disable_dpidle_by_bit(temp); } else if (!strcmp(command, "enable_hi")) { enable_hispeed_by_bit(temp); } else if (!strcmp(command, "disable_hi")) { disable_hispeed_by_bit(temp); } else if (!strcmp(command, "trace")) { if (temp == 1) { memset(idle_single_count, 0, NR_CPUS * sizeof(unsigned int)); dpidle_single_count = 0; dpidle_cm_block_cnt = 0; dpidle_sc_block_cnt = 0; dpidle_block_interval = 0; memset(dpidle_block_mask, 0, MT65XX_CLOCK_CATEGORY_COUNT * sizeof(unsigned int)); dpidle_debug_mask |= DEBUG_TRACING; } else if (temp == 0) { dpidle_debug_mask &= ~DEBUG_TRACING; } } else if (!strcmp(command, "timer")) { timer_delay = temp; timer_pre = GPT_GetCounter(GPT2); udelay(timer_delay); timer_pos = GPT_GetCounter(GPT2); #ifdef PROFILE_DPIDLE } else if (!strcmp(command, "profile")) { if (temp == 1) { dpidle_debug_mask |= DEBUG_PROFILE; dpidle_profile_idx = 0; } else if (temp == 0) { dpidle_debug_mask &= ~DEBUG_PROFILE; } #endif } return n; } else if (sscanf(buf, "%x", &temp) == 1) { dpidle_switch = temp; return n; } return -EINVAL; }