void disp_set_pll(unsigned int freq)
{
unsigned long reg_va_con0 = 0;
unsigned long reg_va_con1 = 0;
static unsigned int freq_last = 364;
static unsigned int pll_cnt;
if (freq == freq_last)
return;
freq_last = freq;
reg_va_con0 =
(unsigned long)ioremap_nocache(REG_PA_VENC_PLL_CON0,
sizeof(unsigned long));
reg_va_con1 =
(unsigned long)ioremap_nocache(REG_PA_VENC_PLL_CON1,
sizeof(unsigned long));
pr_debug
("disp_set_pll(%d), before set, con0=0x%x, con1=0x%x, 0x%lx, 0x%lx\n",
freq, DISP_REG_GET(reg_va_con0), DISP_REG_GET(reg_va_con1),
reg_va_con0, reg_va_con1);
if (freq == 156) {
enable_pll(VENCPLL, DISP_CLOCK_USER_NAME);
DISP_CPU_REG_SET(reg_va_con0, DISP_MMCLK_156MHZ_CON0);
DISP_CPU_REG_SET(reg_va_con1, DISP_MMCLK_156MHZ_CON1);
clkmux_sel(MT_MUX_MM, 3, DISP_CLOCK_USER_NAME);
pll_cnt++;
} else if (freq == 182) {
enable_pll(VENCPLL, DISP_CLOCK_USER_NAME);
DISP_CPU_REG_SET(reg_va_con0, DISP_MMCLK_182MHZ_CON0);
DISP_CPU_REG_SET(reg_va_con1, DISP_MMCLK_182MHZ_CON1);
clkmux_sel(MT_MUX_MM, 3, DISP_CLOCK_USER_NAME);
pll_cnt++;
} else if (freq == 364) {
clkmux_sel(MT_MUX_MM, 1, DISP_CLOCK_USER_NAME);
if (pll_cnt != 0) {
disable_pll(VENCPLL, DISP_CLOCK_USER_NAME);
pll_cnt--;
}
} else {
pr_debug("disp_set_pll, error, invalid freq=%d\n", freq);
}
pr_debug("disp_set_pll(%d), after set, con0=0x%x, con1=0x%x\n",
freq, DISP_REG_GET(reg_va_con0), DISP_REG_GET(reg_va_con1));
iounmap((void *)reg_va_con0);
iounmap((void *)reg_va_con1);
}
TVE_STATUS TVE_PowerOn()
{
if (!s_isTvePowerOn)
{
BOOL ret;
#if 1
ret = pll_fsel(MT65XX_TVDDS, 0x38E40A8E);
ASSERT(!ret);
ret = enable_pll(MT65XX_TVDDS, "TVE");
ASSERT(!ret);
ret = enable_clock(MT65XX_PDN_MM_TVE, "TVE");
ASSERT(!ret);
#else
ret = enable_clock(MT65XX_PDN_MM_TVE, "TVE");
ASSERT(!ret);
//Enable TVDSS, set it to 27MHZ
OUTREG32(0xf00071A0,0x0A8E);
OUTREG32(0xf00071A4,0x38E4);
OUTREG32(0xf00071A8,0x7C54);
msleep(10); //waiting for PLL stable
#endif
_RestoreTVERegisters();
s_isTvePowerOn = TRUE;
}
return TVE_STATUS_OK;
}
DPI_STATUS DPI_PowerOn()
{
if (!s_isDpiPowerOn)
{
#if 0
int ret = enable_clock(MT_CG_DISP1_DPI0, "DPI");
if(1 == ret)
{
DISP_LOG_PRINT(ANDROID_LOG_ERROR, "DPI", "power manager API return FALSE\n");
}
}
enable_pll(LVDSPLL, "dpi0");
#endif
_RestoreDPIRegisters();
s_isDpiPowerOn = TRUE;
}
void mt65xx_usb11_phy_recover(void)
{
INFO("mt65xx_usb11_phy_recover++\r\n");
enable_pll(MT65XX_UPLL, "USB11");
USB11PHY_SET8(U1PHTCR2+3, force_usb11_avalid | force_usb11_sessend | force_usb11_vbusvalid);
USB11PHY_SET8(U1PHTCR2+2, RG_USB11_AVALID | RG_USB11_VBUSVALID);
USB11PHY_CLR8(U1PHTCR2+2, RG_USB11_SESSEND);
USB11PHY_CLR8(U1PHYCR1+2, force_usb11_en_fs_ls_rcv | force_usb11_en_fs_ls_tx);
USB11PHY_CLR8(U1PHYCR1+3, RG_USB11_EN_FS_LS_RCV | RG_USB11_EN_FS_LS_TX);
USB11PHY_SET8(U1PHYCR0+1, RG_USB11_FSLS_ENBGRI);
udelay(100);
}
void musb_platform_enable(struct musb *musb)
{
unsigned long flags;
printk("%s, %d, %d\n", __func__, mtk_usb_power, musb->power);
if (musb->power == true)
return;
flags = musb_readl(mtk_musb->mregs,USB_L1INTM);
// mask ID pin, so "open clock" and "set flag" won't be interrupted. ISR may call clock_disable.
musb_writel(mtk_musb->mregs,USB_L1INTM,(~IDDIG_INT_STATUS)&flags);
if (platform_init_first) {
DBG(0,"usb init first\n\r");
musb->is_host = true;
}
if (!mtk_usb_power) {
if (down_interruptible(&power_clock_lock))
xlog_printk(ANDROID_LOG_ERROR, "USB20", "%s: busy, Couldn't get power_clock_lock\n" \
, __func__);
#ifndef CONFIG_MT6575T_FPGA
enable_pll(MT65XX_UPLL, "USB_PLL");
hwPowerOn(MT65XX_POWER_LDO_VUSB, VOL_3300, "VUSB_LDO");
printk("%s, enable VUSB and UPLL before connect\n", __func__);
#endif
mdelay(10);
usb_phy_recover();
mtk_usb_power = true;
up(&power_clock_lock);
}
musb->power = true;
musb_writel(mtk_musb->mregs,USB_L1INTM,flags);
}
DPI_STATUS DPI_PowerOn()
{
#ifndef CONFIG_MT6589_FPGA
if (!s_isDpiPowerOn)
{
#if 0 // FIXME
int ret = enable_clock(MT65XX_PDN_MM_DPI, "DPI");
if(1 == ret)
{
DISP_LOG_PRINT(ANDROID_LOG_ERROR, "DPI", "power manager API return FALSE\n");
}
#endif
enable_pll(LVDSPLL, "dpi0");
_RestoreDPIRegisters();
s_isDpiPowerOn = TRUE;
}
#endif
return DPI_STATUS_OK;
}
TVC_STATUS TVC_PowerOn(void)
{
if (!_tvcContext.isTvcPowerOn)
{
BOOL ret;
#if 0 // no need to take care of PLL, because PM will take charge of it
BOOL ret = enable_pll(MT65XX_3G_PLL, "TVC");
ASSERT(!ret);
#endif
ret = enable_clock(MT65XX_PDN_MM_TVC, "TVC");
ASSERT(!ret);
_RestoreTVCRegisters();
_tvcContext.isTvcPowerOn = TRUE;
}
return TVC_STATUS_OK;
}
void mt65xx_usb11_phy_poweron(void)
{
INFO("mt65xx_usb11_phy_poweron++\r\n");
enable_pll(MT65XX_UPLL, "USB11");
udelay(100); // PHY power stable time
/* reverse preloader's sin @mt6575_usbphy.c */
USB11PHY_CLR8(U1PHTCR2+3, force_usb11_avalid | force_usb11_bvalid | force_usb11_sessend | force_usb11_vbusvalid);
USB11PHY_CLR8(U1PHTCR2+2, RG_USB11_AVALID | RG_USB11_BVALID | RG_USB11_SESSEND | RG_USB11_VBUSVALID);
USB11PHY_CLR8(U1PHYCR1+2, force_usb11_en_fs_ls_rcv | force_usb11_en_fs_ls_tx);
/**************************************/
USB11PHY_SET8(U1PHYCR0+1, RG_USB11_FSLS_ENBGRI);
USB11PHY_SET8(U1PHTCR2+3, force_usb11_avalid | force_usb11_sessend | force_usb11_vbusvalid);
USB11PHY_SET8(U1PHTCR2+2, RG_USB11_AVALID | RG_USB11_VBUSVALID);
USB11PHY_CLR8(U1PHTCR2+2, RG_USB11_SESSEND);
udelay(100);
}
/* Will only be used in hdmi_drv_init(), this means that will only be use in ioctl(MTK_HDMI_AUDIO_VIDEO_ENABLE) */
/*static*/ void hdmi_dpi_config_clock(void)
{
int ret = 0;
RET_VOID_IF(p->output_mode == HDMI_OUTPUT_MODE_DPI_BYPASS);
ret = enable_pll(TVDPLL, "HDMI");
if(ret)
{
HDMI_LOG("enable_pll fail!!\n");
}
printk("[hdmi]720p 60Hz\n");
//ret = pll_fsel(TVDPLL, 0x800B6C4E);
OUTREG32(TVDPLL_CON1, 0x800B6C4E); //148.5MHz
OUTREG32(TVDPLL_CON0, 0x80000081);
//OUTREG32(TVDPLL_CON0, 0x80000081);
//OUTREG32(DISPSYS_BASE+0x038, 0x1); // rdma0_out_sel, 2 for DPI0
//OUTREG32(DISPSYS_BASE+0x05c, 0x1); // DPI0_SEL, 0 is from rdma0
ASSERT(!ret);
clk_pol = HDMI_POLARITY_FALLING;
de_pol = HDMI_POLARITY_RISING;
hsync_pol = HDMI_POLARITY_RISING;
vsync_pol = HDMI_POLARITY_RISING;;
hsync_front_porch = 110;
hsync_pulse_width = 40;
hsync_back_porch = 220;
vsync_front_porch = 5;
vsync_pulse_width = 5;
vsync_back_porch = 20;
dpi_clk_div = 2;
dpi_clk_duty = 1;
rgb_order = hdmi_params->rgb_order;
intermediat_buffer_num = 4;
// dpi clock configuration using MIPITX
//if(hdmi_params->dpi_port == HDMI_DPI_OUTPUT_PORT_0)
{
DPI_CHECK_RET(DPI_Init(FALSE));
DPI_CHECK_RET(DPI_ConfigPixelClk(clk_pol, dpi_clk_div, dpi_clk_duty));
DPI_CHECK_RET(DPI_ConfigDataEnable(de_pol));
DPI_CHECK_RET(DPI_ConfigHsync(hsync_pol, hsync_pulse_width, hsync_back_porch, hsync_front_porch));
DPI_CHECK_RET(DPI_ConfigVsync(vsync_pol, vsync_pulse_width, vsync_back_porch, vsync_front_porch));
DPI_CHECK_RET(DPI_FBSetSize(1280, 720));
//if (LCM_COLOR_ORDER_BGR == rgb_order)
if (HDMI_COLOR_ORDER_BGR == rgb_order)
{
DPI_CHECK_RET(DPI_SetRGBOrder(DPI_RGB_ORDER_RGB, DPI_RGB_ORDER_BGR));
}
else
{
DPI_CHECK_RET(DPI_SetRGBOrder(DPI_RGB_ORDER_RGB, DPI_RGB_ORDER_RGB));
}
//DPI_Internal_Pattern(1, 5);
DPI_CHECK_RET(DPI_EnableClk());
p->is_clock_on = true;
}
}
// protected by sem_early_suspend, sem_update_screen
static DISP_STATUS dsi_enable_power(BOOL enable)
{
disp_drv_dsi_init_context();
if(lcm_params->dsi.mode == CMD_MODE) {
if (enable) {
#if 0
// Switch bus to MIPI TX.
DSI_CHECK_RET(DSI_enable_MIPI_txio(TRUE));
DSI_PHY_clk_switch(1);
DSI_PHY_clk_setting(lcm_params->dsi.pll_div1, lcm_params->dsi.pll_div2, lcm_params->dsi.LANE_NUM);
DSI_CHECK_RET(DSI_PowerOn());
DSI_WaitForNotBusy();
DSI_clk_HS_mode(0);
DSI_clk_ULP_mode(0);
DSI_lane0_ULP_mode(0);
DSI_Reset();
LCD_CHECK_RET(LCD_PowerOn());
#else
DSI_PHY_clk_switch(1);
#ifndef MT65XX_NEW_DISP
DSI_CHECK_RET(DSI_PowerOn());
if(Need_Wait_ULPS())
Wait_ULPS_Mode();
DSI_PHY_clk_setting(lcm_params->dsi.pll_div1, lcm_params->dsi.pll_div2, lcm_params->dsi.LANE_NUM);
#else
if(lcm_params->dsi.pll_select == 1)
{
ASSERT(0 == enable_pll(LVDSPLL,"mtk_dsi"));
}
DSI_PHY_clk_setting(lcm_params);
DSI_CHECK_RET(DSI_PowerOn());
DSI_clk_ULP_mode(0);
DSI_lane0_ULP_mode(0);
// DSI_clk_HS_mode(1);
#endif
DSI_CHECK_RET(DSI_enable_MIPI_txio(TRUE));
#ifndef MT65XX_NEW_DISP
Wait_WakeUp();
LCD_CHECK_RET(LCD_PowerOn());
#endif
#endif
} else {
#ifndef MT65XX_NEW_DISP
LCD_CHECK_RET(LCD_PowerOff());
#endif
DSI_clk_HS_mode(0);
DSI_lane0_ULP_mode(1);
DSI_clk_ULP_mode(1);
// DSI_CHECK_RET(DSI_PowerOff());
DSI_PHY_clk_switch(0);
DSI_CHECK_RET(DSI_PowerOff());
// Switch bus to GPIO, then power level will be decided by GPIO setting.
DSI_CHECK_RET(DSI_enable_MIPI_txio(FALSE));
if(lcm_params->dsi.pll_select == 1)
ASSERT(0 == disable_pll(LVDSPLL,"mtk_dsi"));
}
} else {
if (enable) {
#if 0
// Switch bus to MIPI TX.
DSI_CHECK_RET(DSI_enable_MIPI_txio(TRUE));
DSI_PHY_clk_switch(1);
DSI_PHY_clk_setting(lcm_params->dsi.pll_div1, lcm_params->dsi.pll_div2, lcm_params->dsi.LANE_NUM);
DSI_CHECK_RET(DSI_PowerOn());
DSI_clk_ULP_mode(0);
DSI_lane0_ULP_mode(0);
DSI_clk_HS_mode(0);
DSI_Reset();
DPI_CHECK_RET(DPI_PowerOn());
LCD_CHECK_RET(LCD_PowerOn());
#else
DSI_PHY_clk_switch(1);
#ifndef MT65XX_NEW_DISP
DSI_CHECK_RET(DSI_PowerOn());
if(Need_Wait_ULPS())
Wait_ULPS_Mode();
DSI_PHY_clk_setting(lcm_params->dsi.pll_div1, lcm_params->dsi.pll_div2, lcm_params->dsi.LANE_NUM);
#else
needStartDSI = true;
if(lcm_params->dsi.pll_select == 1)
{
ASSERT(0 == enable_pll(LVDSPLL,"mtk_dsi"));
}
DSI_PHY_clk_setting(lcm_params);
DSI_CHECK_RET(DSI_PowerOn());
DSI_clk_ULP_mode(0);
DSI_lane0_ULP_mode(0);
DSI_clk_HS_mode(0);
#endif
DSI_CHECK_RET(DSI_enable_MIPI_txio(TRUE));
#ifndef MT65XX_NEW_DISP
Wait_WakeUp();
DPI_CHECK_RET(DPI_PowerOn());
LCD_CHECK_RET(LCD_PowerOn());
#endif
#endif
} else {
#ifndef BUILD_UBOOT
is_video_mode_running = false;
#ifndef MT65XX_NEW_DISP
if(lcm_params->dsi.noncont_clock)
DSI_set_noncont_clk(false, lcm_params->dsi.noncont_clock_period);
if(lcm_params->dsi.lcm_int_te_monitor)
DSI_set_int_TE(false, lcm_params->dsi.lcm_int_te_period);
#endif
#endif
#ifndef MT65XX_NEW_DISP
LCD_CHECK_RET(LCD_PowerOff());
DPI_CHECK_RET(DPI_PowerOff());
#endif
#if 1
DSI_lane0_ULP_mode(1);
DSI_clk_ULP_mode(1);
DSI_CHECK_RET(DSI_PowerOff());
#endif
DSI_PHY_clk_switch(0);
// Switch bus to GPIO, then power level will be decided by GPIO setting.
DSI_CHECK_RET(DSI_enable_MIPI_txio(FALSE));
if(lcm_params->dsi.pll_select == 1)
ASSERT(0 == disable_pll(LVDSPLL,"mtk_dsi"));
}
}
return DISP_STATUS_OK;
}
unsigned int disp_set_pll_by_cmdq(unsigned int freq, void *cmdq_handle)
{
unsigned long reg_va_con0 = 0;
unsigned long reg_va_con1 = 0;
static unsigned int freq_last = 364;
static unsigned int pll_cnt;
unsigned int i = 0;
if (freq == freq_last)
/* return; */
freq_last = freq;
reg_va_con0 =
(unsigned long)ioremap_nocache(REG_PA_VENC_PLL_CON0,
sizeof(unsigned long));
reg_va_con1 =
(unsigned long)ioremap_nocache(REG_PA_VENC_PLL_CON1,
sizeof(unsigned long));
pr_debug
("disp_set_pll(%d), before set, con0=0x%x, con1=0x%x, 0x%lx, 0x%lx\n",
freq, DISP_REG_GET(reg_va_con0), DISP_REG_GET(reg_va_con1),
reg_va_con0, reg_va_con1);
cmdqRecWaitNoClear(cmdq_handle, CMDQ_EVENT_MUTEX0_STREAM_EOF);
if (freq == 156) {
enable_pll(VENCPLL, DISP_CLOCK_USER_NAME);
DISP_CPU_REG_SET(reg_va_con0, DISP_MMCLK_156MHZ_CON0);
DISP_CPU_REG_SET(reg_va_con1, DISP_MMCLK_156MHZ_CON1);
pll_cnt++;
/* set mux to 3 by CMDQ */
DISP_REG_SET_PA(cmdq_handle, 0x10000048, 0x3000000);
DISP_REG_SET_PA(cmdq_handle, 0x10000044, 0x3000000);
DISP_REG_SET_PA(cmdq_handle, 0x10000004, 8);
} else if (freq == 182) {
/*NOT USE*/
} else if (freq == 364) {
/* set mux to 1 by CMDQ */
DISP_REG_SET_PA(cmdq_handle, 0x10000048, 0x3000000);
DISP_REG_SET_PA(cmdq_handle, 0x10000044, 0x1000000);
DISP_REG_SET_PA(cmdq_handle, 0x10000004, 8);
} else {
pr_debug("disp_set_pll, error, invalid freq=%d\n", freq);
}
/* cmdqRecDumpCommand(cmdq_handle); */
cmdqRecFlush(cmdq_handle);
if (freq == 364) {
if (pll_cnt != 0) {
disable_pll(VENCPLL, DISP_CLOCK_USER_NAME);
pll_cnt--;
}
}
pr_debug("disp_set_pll(%d), after set, con0=0x%x, con1=0x%x\n",
freq, DISP_REG_GET(reg_va_con0), DISP_REG_GET(reg_va_con1));
iounmap((void *)reg_va_con0);
iounmap((void *)reg_va_con1);
return 0; /* cmdqRecEstimateEommandExecTime(cmdq_handle); */
}
void mt65xx_usb11_phy_poweron(void)
{
INFO("mt65xx_usb11_phy_poweron++\r\n");
enable_pll(UNIVPLL, "USB11");
//udelay(100); // PHY power stable time
#if 0
/* reverse preloader's sin @mt6575_usbphy.c */
USB11PHY_CLR8(U1PHTCR2+3, force_usb11_avalid | force_usb11_bvalid | force_usb11_sessend | force_usb11_vbusvalid);
USB11PHY_CLR8(U1PHTCR2+2, RG_USB11_AVALID | RG_USB11_BVALID | RG_USB11_SESSEND | RG_USB11_VBUSVALID);
USB11PHY_CLR8(U1PHYCR1+2, force_usb11_en_fs_ls_rcv | force_usb11_en_fs_ls_tx);
/**************************************/
USB11PHY_SET8(U1PHYCR0+1, RG_USB11_FSLS_ENBGRI);
USB11PHY_SET8(U1PHTCR2+3, force_usb11_avalid | force_usb11_sessend | force_usb11_vbusvalid);
USB11PHY_SET8(U1PHTCR2+2, RG_USB11_AVALID | RG_USB11_VBUSVALID);
USB11PHY_CLR8(U1PHTCR2+2, RG_USB11_SESSEND);
#endif
#if 0
//HQA LOOPBACK TEST. <FS>
USB11PHY_CLR8(0x1a, 0x80);
USB11PHY_CLR8(0x68, 0x08);
USB11PHY_CLR8(0x68, 0x03);
USB11PHY_SET8(0x68, 0x10);
USB11PHY_SET8(0x68, 0x04);
USB11PHY_CLR8(0x69, 0x03);
USB11PHY_CLR8(0x69, 0x3C);
USB11PHY_SET8(0x68, 0x80);
USB11PHY_SET8(0x6a, 0x04);
USB11PHY_SET8(0x6a, 0x01);
USB11PHY_SET8(0x6a, 0x08);
USB11PHY_SET8(0x6a, 0x02);
USB11PHY_SET8(0x6a, 0x40);
USB11PHY_SET8(0x6a, 0x80);
USB11PHY_SET8(0x6a, 0x30);
USB11PHY_SET8(0x68, 0x08);
udelay(50);
USB11PHY_SET8(0x63, 0x02);
udelay(1);
USB11PHY_SET8(0x63, 0x02);
USB11PHY_SET8(0x63, 0x04);
USB11PHY_CLR8(0x63, 0x08);
#endif
#if 0
//HQA LOOPBACK TEST. <HS>
USB11PHY_CLR8(0x1a, 0x80);
USB11PHY_CLR8(0x68, 0x08);
USB11PHY_CLR8(0x68, 0x03);
USB11PHY_CLR8(0x68, 0x30);
USB11PHY_CLR8(0x68, 0x04);
USB11PHY_CLR8(0x69, 0x03);
USB11PHY_CLR8(0x69, 0x3C);
USB11PHY_CLR8(0x68, 0xC0);
USB11PHY_SET8(0x6a, 0x04);
USB11PHY_SET8(0x6a, 0x01);
USB11PHY_SET8(0x6a, 0x08);
USB11PHY_SET8(0x6a, 0x02);
USB11PHY_SET8(0x6a, 0x40);
USB11PHY_SET8(0x6a, 0x80);
USB11PHY_SET8(0x6a, 0x30);
USB11PHY_SET8(0x68, 0x08);
udelay(50);
USB11PHY_SET8(0x63, 0x02);
udelay(1);
USB11PHY_SET8(0x63, 0x02);
USB11PHY_SET8(0x63, 0x04);
USB11PHY_CLR8(0x63, 0x08);
usb11_hs_slew_rate_cal();
#endif
udelay(50);
USB11PHY_CLR8(0x6b, 0x04);
USB11PHY_CLR8(0x6e, 0x01);
USB11PHY_CLR8(0x1a, 0x80);
/* remove in MT6588 ?????
USBPHY_CLR8(0x02, 0x7f);
USBPHY_SET8(0x02, 0x09);
USBPHY_CLR8(0x22, 0x03);
*/
USB11PHY_CLR8(0x6a, 0x04);
//USBPHY_SET8(0x1b, 0x08);
//force VBUS Valid
USB11PHY_SET8(0x6C, 0x2C);
USB11PHY_SET8(0x6D, 0x3C);
udelay(800);
}
void mt65xx_usb11_phy_recover(void)
{
INFO("mt65xx_usb11_phy_recover++\r\n");
//4 1. turn on USB reference clock.
enable_pll(UNIVPLL, "USB11");
#if 0
USB11PHY_SET8(U1PHTCR2+3, force_usb11_avalid | force_usb11_sessend | force_usb11_vbusvalid);
USB11PHY_SET8(U1PHTCR2+2, RG_USB11_AVALID | RG_USB11_VBUSVALID);
USB11PHY_CLR8(U1PHTCR2+2, RG_USB11_SESSEND);
USB11PHY_CLR8(U1PHYCR1+2, force_usb11_en_fs_ls_rcv | force_usb11_en_fs_ls_tx);
USB11PHY_CLR8(U1PHYCR1+3, RG_USB11_EN_FS_LS_RCV | RG_USB11_EN_FS_LS_TX);
USB11PHY_SET8(U1PHYCR0+1, RG_USB11_FSLS_ENBGRI);
udelay(100);
#endif
//4 2. wait 50 usec.
udelay(50);
//4 3. force_uart_en = 1'b0
USB11PHY_CLR8(0x6b, 0x04);
//4 4. RG_UART_EN = 1'b0
USB11PHY_CLR8(0x6e, 0x1);
//4 5. force_uart_en = 1'b0
USB11PHY_CLR8(0x6a, 0x04);
//4 6. RG_DPPULLDOWN = 1'b0
USB11PHY_CLR8(0x68, 0x40);
//4 7. RG_DMPULLDOWN = 1'b0
USB11PHY_CLR8(0x68, 0x80);
//4 8. RG_XCVRSEL = 2'b00
USB11PHY_CLR8(0x68, 0x30);
//4 9. RG_TERMSEL = 1'b0
USB11PHY_CLR8(0x68, 0x04);
//4 10. RG_DATAIN[3:0] = 4'b0000
USB11PHY_CLR8(0x69, 0x3c);
//4 11. force_dp_pulldown = 1b'0
USB11PHY_CLR8(0x6a, 0x10);
//4 12. force_dm_pulldown = 1b'0
USB11PHY_CLR8(0x6a, 0x20);
//4 13. force_xcversel = 1b'0
USB11PHY_CLR8(0x6a, 0x08);
//4 14. force_termsel = 1b'0
USB11PHY_CLR8(0x6a, 0x02);
//4 15. force_datain = 1b'0
USB11PHY_CLR8(0x6a, 0x80);
//4 16. RG_USB20_BC11_SW_EN 1'b0
USB11PHY_CLR8(0x1a, 0x80);
//4 17. RG_USB20_OTG_VBUSSCMP_EN 1'b1
USB11PHY_SET8(0x1a, 0x10);
USB11PHY_SET8(0x6C, 0x2C);
USB11PHY_SET8(0x6D, 0x3C);
//<4> 18. wait 800 usec.
udelay(800);
usb11_hs_slew_rate_cal();
}
