/*
* Receive interrupt task.
*/
static void
slip_receiver (void *arg)
{
slip_t *u = arg;
unsigned short len;
/* Start receiver. */
mutex_lock_irq (&u->netif.lock, RECEIVE_IRQ (u->port),
(handler_t) slip_receive_data, u);
enable_receiver (u->port);
enable_receive_interrupt (u->port);
for (;;) {
if (! u->in_ptr) {
/* Allocate buffer for receive data. */
u->in = buf_alloc (u->pool, u->netif.mtu, 16);
if (u->in) {
u->in_ptr = u->in->payload;
u->in_limit = u->in_ptr + u->netif.mtu;
} else {
/* No buffer - ignore input. */
debug_printf ("slip_receiver: out of memory\n");
++u->netif.in_discards;
}
}
/* Wait for the receive interrupt. */
mutex_wait (&u->netif.lock);
/* Process all available received data. */
if (u->in_ptr && u->in_ptr > u->in->payload) {
len = u->in_ptr - u->in->payload;
debug_printf ("slip_receiver(%ld): received %d bytes\n", u->netif.in_packets, len);
buf_truncate (u->in, len);
++u->netif.in_packets;
if (buf_queue_is_full (&u->inq)) {
debug_printf ("slip_receiver: input overflow\n");
++u->netif.in_discards;
/* Reuse the packet. */
u->in_ptr = u->in->payload;
u->in_limit = u->in_ptr + u->netif.mtu;
} else {
/* Enqueue the received packet. */
buf_queue_put (&u->inq, u->in);
u->in_ptr = 0;
}
}
#ifndef TRANSMIT_IRQ
if (u->out_free)
slip_out_next (u);
#endif
}
}
void __antenna_calibrate(struct agnx_priv *priv)
{
void __iomem *ctl = priv->ctl;
u32 reg;
/* Calibrate the BaseBandFilter */
/* base_band_filter_calibrate(priv); */
spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, 0x1002);
agnx_write32(ctl, AGNX_GCR_GAINSET0, 0x1d);
agnx_write32(ctl, AGNX_GCR_GAINSET1, 0x1d);
agnx_write32(ctl, AGNX_GCR_GAINSET2, 0x1d);
agnx_write32(ctl, AGNX_GCR_GAINSETWRITE, 0x1);
agnx_write32(ctl, AGNX_ACI_MODE, 0x1);
agnx_write32(ctl, AGNX_ACI_LEN, 0x3ff);
agnx_write32(ctl, AGNX_ACI_TIMER1, 0x27);
agnx_write32(ctl, AGNX_ACI_TIMER2, 0x27);
spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, 0x1400);
spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, 0x1500);
/* Measure Calibration */
agnx_write32(ctl, AGNX_ACI_MEASURE, 0x1);
calibra_delay(priv);
do_calibration(priv);
agnx_write32(ctl, AGNX_GCR_RXOVERIDE, 0x0);
agnx_write32(ctl, AGNX_ACI_TIMER1, 0x21);
agnx_write32(ctl, AGNX_ACI_TIMER2, 0x27);
agnx_write32(ctl, AGNX_ACI_LEN, 0xf);
reg = agnx_read32(ctl, AGNX_GCR_GAINSET0);
reg &= 0xf;
agnx_write32(ctl, AGNX_GCR_GAINSET0, reg);
reg = agnx_read32(ctl, AGNX_GCR_GAINSET1);
reg &= 0xf;
agnx_write32(ctl, AGNX_GCR_GAINSET1, reg);
reg = agnx_read32(ctl, AGNX_GCR_GAINSET2);
reg &= 0xf;
agnx_write32(ctl, AGNX_GCR_GAINSET2, reg);
agnx_write32(ctl, AGNX_GCR_GAINSETWRITE, 0x0);
/* Write 0x3 Gain Control Discovery Mode */
enable_receiver(priv);
}
