void __init exynos5_m6x_display_init(void)
{
#if defined(CONFIG_FB_VIDEO_PSR)
// For TE_VSYNC, GPIO initialization will be processed
// in m6x_init_gpio_cfg of gpio-m6x.c after this step
// This interrupt will be chained to 77 (gpio_RT group)
int irq;
irq = s5p_register_gpio_interrupt(MEIZU_LCD_TE);
if (IS_ERR_VALUE(irq)){
pr_err("%s: Failed to configure GPJ1(7) \n", __func__);
return;
}
#endif
#ifdef CONFIG_FB_MIPI_DSIM
#ifdef CONFIG_S5P_DEV_MIPI_DSIM0
s5p_dsim0_set_platdata(&dsim_platform_data);
#else
s5p_dsim1_set_platdata(&dsim_platform_data);
#endif
#endif
#ifdef CONFIG_S5P_DP
s5p_dp_set_platdata(&smdk5410_dp_data);
#endif
#ifdef CONFIG_S5P_DEV_FIMD0
s5p_fimd0_set_platdata(&m6x_lcd0_pdata);
#else
s5p_fimd1_set_platdata(&m6x_lcd1_pdata);
#endif
#if defined(CONFIG_BACKLIGHT_LM3695) || defined(CONFIG_BACKLIGHT_LM3630)
lm3695_rt_init_res();
i2c_register_board_info(9, i2c_bl, ARRAY_SIZE(i2c_bl));
#endif
#ifdef CONFIG_TPS65132
i2c_register_board_info(14, i2c_tps, ARRAY_SIZE(i2c_tps));
#endif
platform_add_devices(m6x_display_devices,
ARRAY_SIZE(m6x_display_devices));
#ifdef CONFIG_S5P_DP
exynos5_fimd1_setup_clock(&s5p_device_fimd1.dev,
"sclk_fimd", "mout_mpll_bpll", 267 * MHZ);
#endif
#ifdef CONFIG_FB_MIPI_DSIM
#if defined(CONFIG_S5P_DEV_FIMD0)
exynos5_fimd0_setup_clock(&s5p_device_fimd0.dev,
"sclk_fimd", "mout_mpll_bpll", 140 * MHZ);
#else
exynos5_fimd1_setup_clock(&s5p_device_fimd1.dev,
"sclk_fimd", "mout_mpll_bpll", 140 * MHZ);
#endif
#endif
}
void __init exynos5_smdk5410_display_init(void)
{
#ifdef CONFIG_FB_MIPI_DSIM
#ifdef CONFIG_S5P_DEV_MIPI_DSIM0
s5p_dsim0_set_platdata(&dsim_platform_data);
#else
s5p_dsim1_set_platdata(&dsim_platform_data);
#endif
#endif
#ifdef CONFIG_S5P_DP
s5p_dp_set_platdata(&smdk5410_dp_data);
#endif
#ifdef CONFIG_S5P_DEV_FIMD0
s5p_fimd0_set_platdata(&smdk5410_lcd0_pdata);
#else
s5p_fimd1_set_platdata(&smdk5410_lcd1_pdata);
#endif
samsung_bl_set(&smdk5410_bl_gpio_info, &smdk5410_bl_data);
platform_add_devices(smdk5410_display_devices,
ARRAY_SIZE(smdk5410_display_devices));
#ifdef CONFIG_S5P_DP
exynos5_fimd1_setup_clock(&s5p_device_fimd1.dev,
"sclk_fimd", "mout_mpll_bpll", 267 * MHZ);
#endif
#ifdef CONFIG_FB_MIPI_DSIM
#if defined(CONFIG_S5P_DEV_FIMD0)
exynos5_fimd0_setup_clock(&s5p_device_fimd0.dev,
"sclk_fimd", "mout_mpll_bpll", 800 * MHZ);
#else
/* 64MHz = 320MHz@CPLL / 6 */
exynos5_fimd1_setup_clock(&s5p_device_fimd1.dev,
"sclk_fimd", "mout_cpll", 64 * MHZ);
#endif
#endif
}
