static void exynos_tmu_work(struct work_struct *work)
{
struct exynos_tmu_data *data = container_of(work,
struct exynos_tmu_data, irq_work);
int i;
mutex_lock(&data->lock);
clk_enable(data->clk);
if (data->soc == SOC_ARCH_EXYNOS5) {
for (i = 0; i < EXYNOS_TMU_COUNT; i++) {
writel(EXYNOS5_TMU_CLEAR_RISE_INT,
data->base[i] + EXYNOS_TMU_REG_INTCLEAR);
}
} else {
writel(EXYNOS4_TMU_INTCLEAR_VAL,
data->base + EXYNOS_TMU_REG_INTCLEAR);
}
clk_disable(data->clk);
mutex_unlock(&data->lock);
exynos_report_trigger();
for (i = 0; i < EXYNOS_TMU_COUNT; i++)
enable_irq(data->irq[i]);
}
static void exynos_tmu_work(struct work_struct *work)
{
struct exynos_tmu_data *data = container_of(work,
struct exynos_tmu_data, irq_work);
exynos_report_trigger();
mutex_lock(&data->lock);
clk_enable(data->clk);
if (data->soc == SOC_ARCH_EXYNOS)
writel(EXYNOS_TMU_CLEAR_RISE_INT |
EXYNOS_TMU_CLEAR_FALL_INT,
data->base + EXYNOS_TMU_REG_INTCLEAR);
else
writel(EXYNOS4210_TMU_INTCLEAR_VAL,
data->base + EXYNOS_TMU_REG_INTCLEAR);
clk_disable(data->clk);
mutex_unlock(&data->lock);
enable_irq(data->irq);
}