int main(int argc, char **argv)
{
int rv;
int width, height;
int width_s, height_s;
int padded_width, padded_height;
int backbuffer = 0;
int supersample_x = 2; // 1 or 2
int supersample_y = 2; // 1 or 2
int extra_ps_inputs = 0;
fb_info fb;
rv = fb_open(0, &fb);
if(rv!=0)
{
exit(1);
}
width = fb.fb_var.xres;
height = fb.fb_var.yres;
width_s = width * supersample_x;
height_s = height * supersample_y;
padded_width = etna_align_up(width_s, 64);
padded_height = etna_align_up(height_s, 64);
extra_ps_inputs = (supersample_x > 1 || supersample_y > 1); // in case of supersample, there is an extra input to PS
printf("padded_width %i padded_height %i\n", padded_width, padded_height);
rv = viv_open();
if(rv!=0)
{
fprintf(stderr, "Error opening device\n");
exit(1);
}
printf("Succesfully opened device\n");
etna_vidmem *rt = 0; /* main render target */
etna_vidmem *rt_ts = 0; /* tile status for main render target */
etna_vidmem *z = 0; /* depth for main render target */
etna_vidmem *z_ts = 0; /* depth ts for main render target */
etna_vidmem *vtx = 0; /* vertex buffer */
etna_vidmem *idx = 0; /* index buffer */
etna_vidmem *aux_rt = 0; /* auxilary render target */
etna_vidmem *aux_rt_ts = 0; /* tile status for auxilary render target */
etna_vidmem *tex = 0; /* texture */
etna_vidmem *bmp = 0; /* bitmap */
/* TODO: anti aliasing (doubles width/height) */
size_t rt_size = padded_width * padded_height * 4;
size_t rt_ts_size = etna_align_up((padded_width * padded_height * 4)/0x100, 0x100);
size_t z_size = padded_width * padded_height * 2;
size_t z_ts_size = etna_align_up((padded_width * padded_height * 2)/0x100, 0x100);
size_t bmp_size = width * height * 4;
if(etna_vidmem_alloc_linear(&rt, rt_size, gcvSURF_RENDER_TARGET, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(&rt_ts, rt_ts_size, gcvSURF_TILE_STATUS, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(&z, z_size, gcvSURF_DEPTH, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(&z_ts, z_ts_size, gcvSURF_TILE_STATUS, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(&vtx, VERTEX_BUFFER_SIZE, gcvSURF_VERTEX, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(&idx, INDEX_BUFFER_SIZE, gcvSURF_INDEX, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(&aux_rt, 0x4000, gcvSURF_RENDER_TARGET, gcvPOOL_SYSTEM, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(&aux_rt_ts, 0x100, gcvSURF_TILE_STATUS, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(&tex, 0x100000, gcvSURF_TEXTURE, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(&bmp, bmp_size, gcvSURF_BITMAP, gcvPOOL_DEFAULT, true)!=ETNA_OK
)
{
fprintf(stderr, "Error allocating video memory\n");
exit(1);
}
/* Phew, now we got all the memory we need.
* Write interleaved attribute vertex stream.
* Unlike the GL example we only do this once, not every time glDrawArrays is called, the same would be accomplished
* from GL by using a vertex buffer object.
*/
memset(vtx->logical, 0, 0x5ef80);
#ifndef INDEXED
printf("Interleaving vertices...\n");
float *vertices_array = companion_vertices_array();
float *texture_coordinates_array =
companion_texture_coordinates_array();
float *normals_array = companion_normals_array();
assert(COMPANION_ARRAY_COUNT*(3+3+2)*sizeof(float) < VERTEX_BUFFER_SIZE);
for(int vert=0; vert<COMPANION_ARRAY_COUNT; ++vert)
{
int dest_idx = vert * (3 + 3 + 2);
for(int comp=0; comp<3; ++comp)
((float*)vtx->logical)[dest_idx+comp+0] = vertices_array[vert*3 + comp]; /* 0 */
for(int comp=0; comp<3; ++comp)
((float*)vtx->logical)[dest_idx+comp+3] = normals_array[vert*3 + comp]; /* 1 */
for(int comp=0; comp<2; ++comp)
((float*)vtx->logical)[dest_idx+comp+6] = texture_coordinates_array[vert*2 + comp]; /* 2 */
}
#else
printf("Interleaving vertices and copying index buffer...\n");
assert(COMPANION_VERTEX_COUNT*(3+3+2)*sizeof(float) < VERTEX_BUFFER_SIZE);
for(int vert=0; vert<COMPANION_VERTEX_COUNT; ++vert)
{
int dest_idx = vert * (3 + 3 + 2);
for(int comp=0; comp<3; ++comp)
((float*)vtx->logical)[dest_idx+comp+0] = companion_vertices[vert][comp]; /* 0 */
for(int comp=0; comp<3; ++comp)
((float*)vtx->logical)[dest_idx+comp+3] = companion_normals[vert][comp]; /* 1 */
for(int comp=0; comp<2; ++comp)
((float*)vtx->logical)[dest_idx+comp+6] = companion_texture_coordinates[vert][comp]; /* 2 */
}
assert(COMPANION_TRIANGLE_COUNT*3*sizeof(unsigned short) < INDEX_BUFFER_SIZE);
memcpy(idx->logical, &companion_triangles[0][0], COMPANION_TRIANGLE_COUNT*3*sizeof(unsigned short));
#endif
/* Fill in texture (convert from RGB linear to tiled) */
#define TILE_WIDTH (4)
#define TILE_HEIGHT (4)
#define TILE_WORDS (TILE_WIDTH*TILE_HEIGHT)
unsigned ytiles = COMPANION_TEXTURE_HEIGHT / TILE_HEIGHT;
unsigned xtiles = COMPANION_TEXTURE_WIDTH / TILE_WIDTH;
unsigned dst_stride = xtiles * TILE_WORDS;
for(unsigned ty=0; ty<ytiles; ++ty)
{
for(unsigned tx=0; tx<xtiles; ++tx)
{
unsigned ofs = ty * dst_stride + tx * TILE_WORDS;
for(unsigned y=0; y<TILE_HEIGHT; ++y)
{
for(unsigned x=0; x<TILE_WIDTH; ++x)
{
unsigned srcy = ty*TILE_HEIGHT + y;
unsigned srcx = tx*TILE_WIDTH + x;
unsigned src_ofs = (srcy*COMPANION_TEXTURE_WIDTH+srcx)*3;
unsigned r,g,b,a;
#ifndef TEST_PATTERN /* actual texture */
r = ((uint8_t*)companion_texture)[src_ofs+0];
g = ((uint8_t*)companion_texture)[src_ofs+1];
b = ((uint8_t*)companion_texture)[src_ofs+2];
#else /* test pattern */
r = srcx; g = srcy; b = 0;
#endif
a = 255;
((uint32_t*)tex->logical)[ofs] = ((a&0xFF) << 24) | ((b&0xFF) << 16) | ((g&0xFF) << 8) | (r&0xFF);
ofs += 1;
}
}
}
}
etna_ctx *ctx = 0;
if(etna_create(&ctx) != ETNA_OK)
{
printf("Unable to create context\n");
exit(1);
}
for(int frame=0; frame<1000; ++frame)
{
printf("*** FRAME %i ****\n", frame);
/* XXX part of this can be put outside the loop, but until we have usable context management
* this is safest.
*/
etna_set_state(ctx, VIVS_GL_VERTEX_ELEMENT_CONFIG, 0x1);
etna_set_state(ctx, VIVS_RA_CONTROL, 0x1);
etna_set_state(ctx, VIVS_PA_W_CLIP_LIMIT, 0x34000001);
etna_set_state(ctx, VIVS_PA_SYSTEM_MODE, 0x11);
etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_BIT(VIVS_PA_CONFIG_UNK22, 0));
etna_set_state(ctx, VIVS_SE_CONFIG, 0x0);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR);
etna_set_state(ctx, VIVS_PE_ALPHA_CONFIG,
ETNA_MASKED_BIT(VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_COLOR, 0) &
ETNA_MASKED_BIT(VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_ALPHA, 0) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR, BLEND_FUNC_ONE) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA, BLEND_FUNC_ONE) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR, BLEND_FUNC_ZERO) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA, BLEND_FUNC_ZERO) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_EQ_COLOR, BLEND_EQ_ADD) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_EQ_ALPHA, BLEND_EQ_ADD));
etna_set_state(ctx, VIVS_PE_ALPHA_BLEND_COLOR,
VIVS_PE_ALPHA_BLEND_COLOR_B(0) |
VIVS_PE_ALPHA_BLEND_COLOR_G(0) |
VIVS_PE_ALPHA_BLEND_COLOR_R(0) |
VIVS_PE_ALPHA_BLEND_COLOR_A(0));
etna_set_state(ctx, VIVS_PE_ALPHA_OP, ETNA_MASKED_BIT(VIVS_PE_ALPHA_OP_ALPHA_TEST, 0));
etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_INL(VIVS_PA_CONFIG_CULL_FACE_MODE, CCW));
etna_set_state(ctx, VIVS_PE_STENCIL_CONFIG, ETNA_MASKED(VIVS_PE_STENCIL_CONFIG_REF_FRONT, 0) &
ETNA_MASKED(VIVS_PE_STENCIL_CONFIG_MASK_FRONT, 0xff) &
ETNA_MASKED(VIVS_PE_STENCIL_CONFIG_WRITE_MASK, 0xff) &
ETNA_MASKED_INL(VIVS_PE_STENCIL_CONFIG_MODE, DISABLED));
etna_set_state(ctx, VIVS_PE_STENCIL_OP, ETNA_MASKED(VIVS_PE_STENCIL_OP_FUNC_FRONT, COMPARE_FUNC_ALWAYS) &
ETNA_MASKED(VIVS_PE_STENCIL_OP_FUNC_BACK, COMPARE_FUNC_ALWAYS) &
ETNA_MASKED(VIVS_PE_STENCIL_OP_FAIL_FRONT, STENCIL_OP_KEEP) &
ETNA_MASKED(VIVS_PE_STENCIL_OP_FAIL_BACK, STENCIL_OP_KEEP) &
ETNA_MASKED(VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT, STENCIL_OP_KEEP) &
ETNA_MASKED(VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK, STENCIL_OP_KEEP) &
ETNA_MASKED(VIVS_PE_STENCIL_OP_PASS_FRONT, STENCIL_OP_KEEP) &
ETNA_MASKED(VIVS_PE_STENCIL_OP_PASS_BACK, STENCIL_OP_KEEP));
etna_set_state(ctx, VIVS_SE_DEPTH_SCALE, 0x0);
etna_set_state(ctx, VIVS_SE_DEPTH_BIAS, 0x0);
etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_INL(VIVS_PA_CONFIG_FILL_MODE, SOLID) &
ETNA_MASKED_INL(VIVS_PA_CONFIG_SHADE_MODEL, SMOOTH));
etna_set_state(ctx, VIVS_PE_COLOR_FORMAT,
ETNA_MASKED_BIT(VIVS_PE_COLOR_FORMAT_PARTIAL, 0) &
ETNA_MASKED(VIVS_PE_COLOR_FORMAT_COMPONENTS, 0xf) &
ETNA_MASKED(VIVS_PE_COLOR_FORMAT_FORMAT, RS_FORMAT_X8R8G8B8) &
ETNA_MASKED_BIT(VIVS_PE_COLOR_FORMAT_SUPER_TILED, 1));
etna_set_state(ctx, VIVS_PE_COLOR_ADDR, rt->address);
etna_set_state(ctx, VIVS_PE_COLOR_STRIDE, padded_width * 4);
uint32_t ts_msaa_config;
if(supersample_x == 2 && supersample_y == 2)
{
// 4X MSAA
etna_set_state(ctx, VIVS_GL_MULTI_SAMPLE_CONFIG,
ETNA_MASKED_INL(VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES, 4X) &
ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES, 0xf) &
ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12, 0x0) &
ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16, 0x0)
);
etna_set_state(ctx, VIVS_RA_MULTISAMPLE_UNK00E04, 0x0);
etna_set_state(ctx, VIVS_RA_MULTISAMPLE_UNK00E10(2), 0xaaa22a22);
etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(8), 0x262a2288);
etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(9), 0x886688a2);
etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(10), 0x888866aa);
etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(11), 0x668888a6);
etna_set_state(ctx, VIVS_RA_MULTISAMPLE_UNK00E10(1), 0xe6ae622a);
etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(4), 0x46622a88);
etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(5), 0x888888ae);
etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(6), 0x888888e6);
etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(7), 0x888888ca);
etna_set_state(ctx, VIVS_RA_MULTISAMPLE_UNK00E10(0), 0xeaa26e26);
etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(0), 0x4a6e2688);
etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(1), 0x888888a2);
etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(2), 0x888888ea);
etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(3), 0x888888c6);
ts_msaa_config = VIVS_TS_MEM_CONFIG_MSAA | VIVS_TS_MEM_CONFIG_MSAA_FORMAT_A8R8G8B8;
} else if(supersample_x == 2 && supersample_y == 1)
{
// 2X MSAA
etna_set_state(ctx, VIVS_GL_MULTI_SAMPLE_CONFIG,
ETNA_MASKED_INL(VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES, 2X) &
ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES, 0xf) &
ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12, 0x0) &
ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16, 0x0)
);
etna_set_state(ctx, VIVS_RA_MULTISAMPLE_UNK00E04, 0x0);
etna_set_state(ctx, VIVS_RA_MULTISAMPLE_UNK00E10(0), 0xaa22);
etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(0), 0x66aa2288);
etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(1), 0x88558800);
etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(2), 0x88881100);
etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(3), 0x33888800);
ts_msaa_config = VIVS_TS_MEM_CONFIG_MSAA | VIVS_TS_MEM_CONFIG_MSAA_FORMAT_A8R8G8B8;
} else { // No multisampling
etna_set_state(ctx, VIVS_GL_MULTI_SAMPLE_CONFIG,
ETNA_MASKED_INL(VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES, NONE) &
ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES, 0xf) &
ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12, 0x0) &
ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16, 0x0)
);
ts_msaa_config = 0;
}
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR);
etna_set_state(ctx, VIVS_TS_COLOR_CLEAR_VALUE, 0);
etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts->address);
etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt->address);
etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG,
ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE, 0) &
ETNA_MASKED_INL(VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT, D16) &
ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_SUPER_TILED, 1) &
ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_EARLY_Z, 1));
etna_set_state(ctx, VIVS_PE_DEPTH_ADDR, z->address);
etna_set_state(ctx, VIVS_PE_DEPTH_STRIDE, padded_width * 2);
etna_set_state(ctx, VIVS_PE_HDEPTH_CONTROL, VIVS_PE_HDEPTH_CONTROL_FORMAT_DISABLED);
etna_set_state_f32(ctx, VIVS_PE_DEPTH_NORMALIZE, 65535.0);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_DEPTH);
etna_set_state(ctx, VIVS_TS_DEPTH_CLEAR_VALUE, 0xffffffff);
etna_set_state(ctx, VIVS_TS_DEPTH_STATUS_BASE, z_ts->address);
etna_set_state(ctx, VIVS_TS_DEPTH_SURFACE_BASE, z->address);
etna_set_state(ctx, VIVS_TS_MEM_CONFIG,
VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR |
VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR |
VIVS_TS_MEM_CONFIG_DEPTH_16BPP |
VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION |
ts_msaa_config);
#ifdef EXTRA_DELAYS
/* Warm up RS on aux render target (is this needed?) */
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_warm_up_rs(ctx, aux_rt->address, aux_rt_ts->address);
etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts_physical);
etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt_physical);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_warm_up_rs(ctx, aux_rt_physical, aux_rt_ts_physical);
etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts_physical);
etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt_physical);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_warm_up_rs(ctx, aux_rt_physical, aux_rt_ts_physical);
etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts_physical);
etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt_physical);
#endif
/* sync rasterizer to pixel engine after changes to PE config */
etna_stall(ctx, SYNC_RECIPIENT_RA, SYNC_RECIPIENT_PE);
/* Set up the resolve to clear tile status for main render target and depth
* Regard the TS as an image of width 16 with 4 bytes per pixel (64 bytes per row)
* */
etna_set_state(ctx, VIVS_RS_CONFIG,
VIVS_RS_CONFIG_SOURCE_FORMAT(RS_FORMAT_A8R8G8B8) |
VIVS_RS_CONFIG_DEST_FORMAT(RS_FORMAT_A8R8G8B8)
);
etna_set_state_multi(ctx, VIVS_RS_DITHER(0), 2, (uint32_t[]){0xffffffff, 0xffffffff});
etna_set_state(ctx, VIVS_RS_FILL_VALUE(0), 0x55555555);
etna_set_state(ctx, VIVS_RS_CLEAR_CONTROL,
VIVS_RS_CLEAR_CONTROL_MODE_ENABLED1 |
(0xffff << VIVS_RS_CLEAR_CONTROL_BITS__SHIFT));
etna_set_state(ctx, VIVS_RS_EXTRA_CONFIG, 0);
/* clear color ts */
etna_set_state(ctx, VIVS_RS_DEST_ADDR, rt_ts->address);
etna_set_state(ctx, VIVS_RS_DEST_STRIDE, 0x40);
etna_set_state(ctx, VIVS_RS_WINDOW_SIZE,
((rt_ts_size/0x40) << VIVS_RS_WINDOW_SIZE_HEIGHT__SHIFT) |
(16 << VIVS_RS_WINDOW_SIZE_WIDTH__SHIFT));
etna_set_state(ctx, VIVS_RS_KICKER, 0xbeebbeeb);
/* clear depth ts */
etna_set_state(ctx, VIVS_RS_DEST_ADDR, z_ts->address);
etna_set_state(ctx, VIVS_RS_DEST_STRIDE, 0x40);
etna_set_state(ctx, VIVS_RS_WINDOW_SIZE,
((z_ts_size/0x40) << VIVS_RS_WINDOW_SIZE_HEIGHT__SHIFT) |
(16 << VIVS_RS_WINDOW_SIZE_WIDTH__SHIFT));
etna_set_state(ctx, VIVS_RS_KICKER, 0xbeebbeeb);
/** Done */
etna_set_state(ctx, VIVS_TS_COLOR_CLEAR_VALUE, 0xff7f7f7f);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR);
etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts->address);
etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt->address);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
/* depth setup */
etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE, 1) &
ETNA_MASKED(VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC, COMPARE_FUNC_LESS) &
ETNA_MASKED_INL(VIVS_PE_DEPTH_CONFIG_DEPTH_MODE, Z) &
ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_ONLY_DEPTH, 0));
etna_set_state_f32(ctx, VIVS_PE_DEPTH_NEAR, 0.0);
etna_set_state_f32(ctx, VIVS_PE_DEPTH_FAR, 1.0);
etna_set_state_f32(ctx, VIVS_PE_DEPTH_NORMALIZE, 65535.0);
/* set up primitive assembly and setup engine */
etna_set_state_f32(ctx, VIVS_PA_VIEWPORT_OFFSET_Z, 0.0);
etna_set_state_f32(ctx, VIVS_PA_VIEWPORT_SCALE_Z, 1.0);
etna_set_state_fixp(ctx, VIVS_PA_VIEWPORT_OFFSET_X, width << 15);
etna_set_state_fixp(ctx, VIVS_PA_VIEWPORT_OFFSET_Y, height << 15);
etna_set_state_fixp(ctx, VIVS_PA_VIEWPORT_SCALE_X, width << 15);
etna_set_state_fixp(ctx, VIVS_PA_VIEWPORT_SCALE_Y, height << 15);
etna_set_state_fixp(ctx, VIVS_SE_SCISSOR_LEFT, 0);
etna_set_state_fixp(ctx, VIVS_SE_SCISSOR_TOP, 0);
etna_set_state_fixp(ctx, VIVS_SE_SCISSOR_RIGHT, (width << 16) | 5);
etna_set_state_fixp(ctx, VIVS_SE_SCISSOR_BOTTOM, (height << 16) | 5);
/* set up texture unit */
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_TEXTURE);
etna_set_state(ctx, VIVS_TE_SAMPLER_SIZE(0),
VIVS_TE_SAMPLER_SIZE_WIDTH(512)|VIVS_TE_SAMPLER_SIZE_HEIGHT(512));
etna_set_state(ctx, VIVS_TE_SAMPLER_LOG_SIZE(0),
VIVS_TE_SAMPLER_LOG_SIZE_WIDTH(9<<5) |
VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT(9<<5));
etna_set_state(ctx, VIVS_TE_SAMPLER_LOD_ADDR(0,0), tex->address);
etna_set_state(ctx, VIVS_TE_SAMPLER_CONFIG0(0),
VIVS_TE_SAMPLER_CONFIG0_TYPE(TEXTURE_TYPE_2D)|
VIVS_TE_SAMPLER_CONFIG0_UWRAP(TEXTURE_WRAPMODE_CLAMP_TO_EDGE)|
VIVS_TE_SAMPLER_CONFIG0_VWRAP(TEXTURE_WRAPMODE_CLAMP_TO_EDGE)|
VIVS_TE_SAMPLER_CONFIG0_MIN(TEXTURE_FILTER_LINEAR)|
VIVS_TE_SAMPLER_CONFIG0_MIP(TEXTURE_FILTER_NONE)|
VIVS_TE_SAMPLER_CONFIG0_MAG(TEXTURE_FILTER_LINEAR)|
VIVS_TE_SAMPLER_CONFIG0_FORMAT(TEXTURE_FORMAT_X8R8G8B8));
etna_set_state(ctx, VIVS_TE_SAMPLER_LOD_CONFIG(0), 0x00000000); /* TE.SAMPLER[0].LOD_CONFIG := 0x0 */
/* shader setup */
etna_set_state(ctx, VIVS_VS_END_PC, vs_size/16);
etna_set_state_multi(ctx, VIVS_VS_INPUT_COUNT, 3, (uint32_t[]){
/* VIVS_VS_INPUT_COUNT */ VIVS_VS_INPUT_COUNT_UNK8(1) | VIVS_VS_INPUT_COUNT_COUNT(3),
/* VIVS_VS_TEMP_REGISTER_CONTROL */ VIVS_VS_TEMP_REGISTER_CONTROL_NUM_TEMPS(6),
/* VIVS_VS_OUTPUT(0) */ 0x10004});
etna_set_state(ctx, VIVS_VS_START_PC, 0x0);
etna_set_state_f32(ctx, VIVS_VS_UNIFORMS(45), 0.5); /* u11.y */
etna_set_state_f32(ctx, VIVS_VS_UNIFORMS(44), 1.0); /* u11.x */
etna_set_state_f32(ctx, VIVS_VS_UNIFORMS(27), 0.0); /* u6.w */
etna_set_state_f32(ctx, VIVS_VS_UNIFORMS(23), 20.0); /* u5.w */
etna_set_state_f32(ctx, VIVS_VS_UNIFORMS(19), 2.0); /* u4.w */
/* Now load the shader itself */
etna_set_state_multi(ctx, VIVS_VS_INST_MEM(0), vs_size/4, vs);
etna_set_state(ctx, VIVS_RA_CONTROL, 0x3);
etna_set_state_f32(ctx, VIVS_PS_UNIFORMS(0), 1.0); /* u0.x */
etna_set_state_multi(ctx, VIVS_PS_END_PC, 2, (uint32_t[]){
/* VIVS_PS_END_PC */ ps_size/16,
/* VIVS_PS_OUTPUT_REG */ 0x1});
etna_set_state(ctx, VIVS_PS_START_PC, 0x0);
etna_set_state(ctx, VIVS_PA_ATTRIBUTE_ELEMENT_COUNT, 0x200);
etna_set_state(ctx, VIVS_PA_SHADER_ATTRIBUTES(0), 0x200);
etna_set_state(ctx, VIVS_PA_SHADER_ATTRIBUTES(1), 0x200);
etna_set_state(ctx, VIVS_GL_VARYING_NUM_COMPONENTS,
VIVS_GL_VARYING_NUM_COMPONENTS_VAR0(4)| /* position */
VIVS_GL_VARYING_NUM_COMPONENTS_VAR1(2) /* texture coordinate */
);
etna_set_state_multi(ctx, VIVS_GL_VARYING_COMPONENT_USE(0), 2, (uint32_t[]){
VIVS_GL_VARYING_COMPONENT_USE_COMP0(VARYING_COMPONENT_USE_USED) |
VIVS_GL_VARYING_COMPONENT_USE_COMP1(VARYING_COMPONENT_USE_USED) |
VIVS_GL_VARYING_COMPONENT_USE_COMP2(VARYING_COMPONENT_USE_USED) |
VIVS_GL_VARYING_COMPONENT_USE_COMP3(VARYING_COMPONENT_USE_USED) |
VIVS_GL_VARYING_COMPONENT_USE_COMP4(VARYING_COMPONENT_USE_USED) |
VIVS_GL_VARYING_COMPONENT_USE_COMP5(VARYING_COMPONENT_USE_USED)
, 0
});
etna_set_state_multi(ctx, VIVS_PS_INST_MEM(0), ps_size/4, ps);
etna_set_state(ctx, VIVS_PS_INPUT_COUNT,
VIVS_PS_INPUT_COUNT_UNK8(31)| VIVS_PS_INPUT_COUNT_COUNT(3 + extra_ps_inputs));
etna_set_state(ctx, VIVS_PS_TEMP_REGISTER_CONTROL,
VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS(3 + extra_ps_inputs));
etna_set_state(ctx, VIVS_PS_CONTROL, VIVS_PS_CONTROL_UNK1);
etna_set_state(ctx, VIVS_GL_VARYING_TOTAL_COMPONENTS,
VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM(6)); /* 4+2=6 total varying components */
etna_set_state(ctx, VIVS_VS_LOAD_BALANCING, 0xf3f0542); /* depends on number of inputs/outputs/varyings? XXX how exactly */
etna_set_state(ctx, VIVS_VS_OUTPUT_COUNT, 3);
etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_BIT(VIVS_PA_CONFIG_POINT_SIZE_ENABLE, 0));
/* Compute transform matrices in the same way as cube egl demo */
ESMatrix modelview;
esMatrixLoadIdentity(&modelview);
esTranslate(&modelview, 0.0f, 0.0f, -9.0f);
esRotate(&modelview, 45.0f, 1.0f, 0.0f, 0.0f);
esRotate(&modelview, 45.0f, 0.0f, 1.0f, 0.0f);
esRotate(&modelview, frame*0.5f, 0.0f, 0.0f, 1.0f);
esScale(&modelview, 0.475f, 0.475f, 0.475f);
GLfloat aspect = (GLfloat)(height) / (GLfloat)(width);
ESMatrix projection;
esMatrixLoadIdentity(&projection);
esFrustum(&projection, -2.8f, +2.8f, -2.8f * aspect, +2.8f * aspect, 6.0f, 10.0f);
ESMatrix modelviewprojection;
esMatrixLoadIdentity(&modelviewprojection);
esMatrixMultiply(&modelviewprojection, &modelview, &projection);
ESMatrix inverse, normal; /* compute inverse transpose normal transformation matrix */
esMatrixInverse3x3(&inverse, &modelview);
esMatrixTranspose(&normal, &inverse);
etna_set_state_multi(ctx, VIVS_VS_UNIFORMS(0), 16, (uint32_t*)&modelviewprojection.m[0][0]);
etna_set_state_multi(ctx, VIVS_VS_UNIFORMS(16), 3, (uint32_t*)&normal.m[0][0]); /* u4.xyz */
etna_set_state_multi(ctx, VIVS_VS_UNIFORMS(20), 3, (uint32_t*)&normal.m[1][0]); /* u5.xyz */
etna_set_state_multi(ctx, VIVS_VS_UNIFORMS(24), 3, (uint32_t*)&normal.m[2][0]); /* u6.xyz */
etna_set_state_multi(ctx, VIVS_VS_UNIFORMS(28), 16, (uint32_t*)&modelview.m[0][0]);
#ifdef INDEXED
etna_set_state(ctx, VIVS_FE_INDEX_STREAM_BASE_ADDR, idx->address);
etna_set_state(ctx, VIVS_FE_INDEX_STREAM_CONTROL, VIVS_FE_INDEX_STREAM_CONTROL_TYPE_UNSIGNED_SHORT);
#endif
etna_set_state(ctx, VIVS_FE_VERTEX_STREAM_BASE_ADDR, vtx->address);
etna_set_state(ctx, VIVS_FE_VERTEX_STREAM_CONTROL,
VIVS_FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE((3 + 3 + 2)*4));
etna_set_state(ctx, VIVS_FE_VERTEX_ELEMENT_CONFIG(0),
VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_FLOAT |
(ENDIAN_MODE_NO_SWAP << VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM(0) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM_3 |
VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_OFF |
VIVS_FE_VERTEX_ELEMENT_CONFIG_START(0x0) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_END(0xc));
etna_set_state(ctx, VIVS_FE_VERTEX_ELEMENT_CONFIG(1),
VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_FLOAT |
(ENDIAN_MODE_NO_SWAP << VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM(0) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM_3 |
VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_OFF |
VIVS_FE_VERTEX_ELEMENT_CONFIG_START(0xc) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_END(0x18));
etna_set_state(ctx, VIVS_FE_VERTEX_ELEMENT_CONFIG(2),
VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_FLOAT |
(ENDIAN_MODE_NO_SWAP << VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_NONCONSECUTIVE |
VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM(0) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM_2 |
VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_OFF |
VIVS_FE_VERTEX_ELEMENT_CONFIG_START(0x18) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_END(0x20));
etna_set_state(ctx, VIVS_VS_INPUT(0), 0x20100);
etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_BIT(VIVS_PA_CONFIG_POINT_SPRITE_ENABLE, 0));
#ifdef INDEXED
etna_draw_indexed_primitives(ctx, PRIMITIVE_TYPE_TRIANGLES, 0, COMPANION_TRIANGLE_COUNT, 0);
#else
etna_draw_primitives(ctx, PRIMITIVE_TYPE_TRIANGLES, 0, COMPANION_TRIANGLE_COUNT);
#endif
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
#ifdef EXTRA_DELAYS
etna_flush(ctx);
#endif
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_set_state(ctx, VIVS_RS_CONFIG,
VIVS_RS_CONFIG_SOURCE_FORMAT(RS_FORMAT_A8R8G8B8) |
VIVS_RS_CONFIG_SOURCE_TILED |
VIVS_RS_CONFIG_DEST_FORMAT(RS_FORMAT_A8R8G8B8) |
VIVS_RS_CONFIG_DEST_TILED);
etna_set_state(ctx, VIVS_RS_SOURCE_STRIDE, (padded_width * 4 * 4) | VIVS_RS_SOURCE_STRIDE_TILING);
etna_set_state(ctx, VIVS_RS_DEST_STRIDE, (padded_width * 4 * 4) | VIVS_RS_DEST_STRIDE_TILING);
etna_set_state(ctx, VIVS_RS_DITHER(0), 0xffffffff);
etna_set_state(ctx, VIVS_RS_DITHER(1), 0xffffffff);
etna_set_state(ctx, VIVS_RS_CLEAR_CONTROL, VIVS_RS_CLEAR_CONTROL_MODE_DISABLED);
etna_set_state(ctx, VIVS_RS_EXTRA_CONFIG, 0);
etna_set_state(ctx, VIVS_RS_SOURCE_ADDR, rt->address);
etna_set_state(ctx, VIVS_RS_DEST_ADDR, rt->address);
etna_set_state(ctx, VIVS_RS_WINDOW_SIZE,
VIVS_RS_WINDOW_SIZE_HEIGHT(padded_height) |
VIVS_RS_WINDOW_SIZE_WIDTH(padded_width));
etna_set_state(ctx, VIVS_RS_KICKER, 0xbeebbeeb);
#ifdef EXTRA_DELAYS
etna_flush(ctx);
etna_warm_up_rs(ctx, aux_rt->address, aux_rt_ts->address);
#endif
etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts->address);
etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt->address);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR);
etna_set_state(ctx, VIVS_TS_MEM_CONFIG,
VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR |
VIVS_TS_MEM_CONFIG_DEPTH_16BPP |
VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR);
/* Wait for pixel engine to finish */
#ifdef EXTRA_DELAYS
etna_finish(ctx);
#else
etna_stall(ctx, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
#endif
/* Copy result to framebuffer */
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_set_state(ctx, VIVS_RS_CONFIG,
VIVS_RS_CONFIG_SOURCE_FORMAT(RS_FORMAT_A8R8G8B8) |
VIVS_RS_CONFIG_SOURCE_TILED |
((supersample_x>1)?VIVS_RS_CONFIG_DOWNSAMPLE_X:0) |
((supersample_y>1)?VIVS_RS_CONFIG_DOWNSAMPLE_Y:0) |
VIVS_RS_CONFIG_DEST_FORMAT(RS_FORMAT_A8R8G8B8) |
VIVS_RS_CONFIG_SWAP_RB);
etna_set_state(ctx, VIVS_RS_SOURCE_STRIDE, (padded_width * 4 * 4) | VIVS_RS_SOURCE_STRIDE_TILING);
etna_set_state(ctx, VIVS_RS_DEST_STRIDE, fb.fb_fix.line_length);
etna_set_state(ctx, VIVS_RS_DITHER(0), 0xffffffff);
etna_set_state(ctx, VIVS_RS_DITHER(1), 0xffffffff);
etna_set_state(ctx, VIVS_RS_CLEAR_CONTROL, VIVS_RS_CLEAR_CONTROL_MODE_DISABLED);
etna_set_state(ctx, VIVS_RS_EXTRA_CONFIG, 0);
etna_set_state(ctx, VIVS_RS_SOURCE_ADDR, rt->address);
etna_set_state(ctx, VIVS_RS_DEST_ADDR, fb.physical[backbuffer]);
etna_set_state(ctx, VIVS_RS_WINDOW_SIZE,
VIVS_RS_WINDOW_SIZE_HEIGHT(height * supersample_y) |
VIVS_RS_WINDOW_SIZE_WIDTH(width * supersample_x));
etna_set_state(ctx, VIVS_RS_KICKER, 0xbeebbeeb);
etna_finish(ctx);
/* switch buffers */
fb_set_buffer(&fb, backbuffer);
backbuffer = 1-backbuffer;
}
etna_free(ctx);
viv_close();
return 0;
}
int main(int argc, char **argv)
{
int rv;
int width = 256;
int height = 256;
int padded_width, padded_height;
int backbuffer = 0;
struct fb_info fb;
rv = fb_open(0, &fb);
if(rv!=0)
{
exit(1);
}
width = fb.fb_var.xres;
height = fb.fb_var.yres;
padded_width = etna_align_up(width, 64);
padded_height = etna_align_up(height, 64);
printf("padded_width %i padded_height %i\n", padded_width, padded_height);
struct viv_conn *conn = 0;
rv = viv_open(VIV_HW_3D, &conn);
if(rv!=0)
{
fprintf(stderr, "Error opening device\n");
exit(1);
}
printf("Succesfully opened device\n");
struct etna_vidmem *rt = 0; /* main render target */
struct etna_vidmem *rt_ts = 0; /* tile status for main render target */
struct etna_vidmem *z = 0; /* depth for main render target */
struct etna_vidmem *z_ts = 0; /* depth ts for main render target */
struct etna_vidmem *vtx = 0; /* vertex buffer */
struct etna_vidmem *aux_rt = 0; /* auxilary render target */
struct etna_vidmem *aux_rt_ts = 0; /* tile status for auxilary render target */
struct etna_vidmem *bmp = 0; /* bitmap */
size_t rt_size = padded_width * padded_height * 4;
size_t rt_ts_size = etna_align_up((padded_width * padded_height * 4)/0x100, 0x100);
size_t z_size = padded_width * padded_height * 2;
size_t z_ts_size = etna_align_up((padded_width * padded_height * 2)/0x100, 0x100);
size_t bmp_size = width * height * 4;
if(etna_vidmem_alloc_linear(conn, &rt, rt_size, gcvSURF_RENDER_TARGET, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(conn, &rt_ts, rt_ts_size, gcvSURF_TILE_STATUS, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(conn, &z, z_size, gcvSURF_DEPTH, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(conn, &z_ts, z_ts_size, gcvSURF_TILE_STATUS, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(conn, &vtx, VERTEX_BUFFER_SIZE, gcvSURF_VERTEX, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(conn, &aux_rt, 0x4000, gcvSURF_RENDER_TARGET, gcvPOOL_SYSTEM, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(conn, &aux_rt_ts, 0x100, gcvSURF_TILE_STATUS, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(conn, &bmp, bmp_size, gcvSURF_BITMAP, gcvPOOL_DEFAULT, true)!=ETNA_OK
)
{
fprintf(stderr, "Error allocating video memory\n");
exit(1);
}
/* Phew, now we got all the memory we need.
* Write interleaved attribute vertex stream.
* Unlike the GL example we only do this once, not every time glDrawArrays is called, the same would be accomplished
* from GL by using a vertex buffer object.
*/
for(int vert=0; vert<NUM_VERTICES; ++vert)
{
int dest_idx = vert * (3 + 2);
for(int comp=0; comp<3; ++comp)
((float*)vtx->logical)[dest_idx+comp+0] = vVertices[vert*3 + comp]; /* 0 */
for(int comp=0; comp<2; ++comp)
((float*)vtx->logical)[dest_idx+comp+3] = vTexCoords[vert*2 + comp]; /* 1 */
}
struct etna_ctx *ctx = 0;
if(etna_create(conn, &ctx) != ETNA_OK)
{
printf("Unable to create context\n");
exit(1);
}
/* Now load the shader itself */
uint32_t vs[] = {
0x02001001, 0x2a800800, 0x00000000, 0x003fc008,
0x02001003, 0x2a800800, 0x00000040, 0x00000002,
};
uint32_t vs_size = sizeof(vs);
uint32_t *ps;
uint32_t ps_size;
if(argc < 2)
{
perror("provide shader on command line");
exit(1);
}
int fd = open(argv[1], O_RDONLY);
if(fd == -1)
{
perror("opening shader");
exit(1);
}
ps_size = lseek(fd, 0, SEEK_END);
ps = malloc(ps_size);
lseek(fd, 0, SEEK_SET);
if(ps_size == 0 || ps_size>8192 || read(fd, ps, ps_size) != ps_size)
{
perror("empty or unreadable shader");
exit(1);
}
close(fd);
for(int frame=0; frame<1000; ++frame)
{
printf("*** FRAME %i ****\n", frame);
/* XXX part of this can be put outside the loop, but until we have usable context management
* this is safest.
*/
etna_set_state(ctx, VIVS_GL_VERTEX_ELEMENT_CONFIG, 0x1);
etna_set_state(ctx, VIVS_RA_CONTROL, 0x1);
etna_set_state(ctx, VIVS_PA_W_CLIP_LIMIT, 0x34000001);
etna_set_state(ctx, VIVS_PA_SYSTEM_MODE, 0x11);
etna_set_state(ctx, VIVS_SE_CONFIG, 0x0);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR);
/* Set up pixel engine */
etna_set_state(ctx, VIVS_PE_ALPHA_CONFIG,
ETNA_MASKED_BIT(VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_COLOR, 0) &
ETNA_MASKED_BIT(VIVS_PE_ALPHA_CONFIG_BLEND_SEPARATE_ALPHA, 0) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR, BLEND_FUNC_ONE) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA, BLEND_FUNC_ONE) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR, BLEND_FUNC_ZERO) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA, BLEND_FUNC_ZERO) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_EQ_COLOR, BLEND_EQ_ADD) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_EQ_ALPHA, BLEND_EQ_ADD));
etna_set_state(ctx, VIVS_PE_ALPHA_BLEND_COLOR,
VIVS_PE_ALPHA_BLEND_COLOR_B(0) |
VIVS_PE_ALPHA_BLEND_COLOR_G(0) |
VIVS_PE_ALPHA_BLEND_COLOR_R(0) |
VIVS_PE_ALPHA_BLEND_COLOR_A(0));
etna_set_state(ctx, VIVS_PE_ALPHA_OP, ETNA_MASKED_BIT(VIVS_PE_ALPHA_OP_ALPHA_TEST, 0));
etna_set_state(ctx, VIVS_PE_STENCIL_CONFIG, ETNA_MASKED(VIVS_PE_STENCIL_CONFIG_REF_FRONT, 0) &
ETNA_MASKED(VIVS_PE_STENCIL_CONFIG_MASK_FRONT, 0xff) &
ETNA_MASKED(VIVS_PE_STENCIL_CONFIG_WRITE_MASK, 0xff));
etna_set_state(ctx, VIVS_PE_STENCIL_OP, ETNA_MASKED(VIVS_PE_STENCIL_OP_FUNC_FRONT, COMPARE_FUNC_ALWAYS) &
ETNA_MASKED(VIVS_PE_STENCIL_OP_FUNC_BACK, COMPARE_FUNC_ALWAYS) &
ETNA_MASKED(VIVS_PE_STENCIL_OP_FAIL_FRONT, STENCIL_OP_KEEP) &
ETNA_MASKED(VIVS_PE_STENCIL_OP_FAIL_BACK, STENCIL_OP_KEEP) &
ETNA_MASKED(VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT, STENCIL_OP_KEEP) &
ETNA_MASKED(VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK, STENCIL_OP_KEEP) &
ETNA_MASKED(VIVS_PE_STENCIL_OP_PASS_FRONT, STENCIL_OP_KEEP) &
ETNA_MASKED(VIVS_PE_STENCIL_OP_PASS_BACK, STENCIL_OP_KEEP));
etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE, 0));
etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_EARLY_Z, 0));
etna_set_state(ctx, VIVS_SE_DEPTH_SCALE, 0x0);
etna_set_state(ctx, VIVS_SE_DEPTH_BIAS, 0x0);
etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_BIT(VIVS_PA_CONFIG_UNK22, 0));
etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_INL(VIVS_PA_CONFIG_CULL_FACE_MODE, OFF));
etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_INL(VIVS_PA_CONFIG_FILL_MODE, SOLID));
etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_INL(VIVS_PA_CONFIG_SHADE_MODEL, SMOOTH));
etna_set_state(ctx, VIVS_PE_COLOR_FORMAT,
ETNA_MASKED_BIT(VIVS_PE_COLOR_FORMAT_OVERWRITE, 0));
etna_set_state(ctx, VIVS_PE_COLOR_FORMAT, ETNA_MASKED(VIVS_PE_COLOR_FORMAT_COMPONENTS, 0xf));
etna_set_state(ctx, VIVS_PE_COLOR_FORMAT,
ETNA_MASKED(VIVS_PE_COLOR_FORMAT_FORMAT, RS_FORMAT_A8R8G8B8) &
ETNA_MASKED_BIT(VIVS_PE_COLOR_FORMAT_SUPER_TILED, 1));
etna_set_state(ctx, VIVS_PE_COLOR_ADDR, rt->address); /* ADDR_A */
etna_set_state(ctx, VIVS_PE_COLOR_STRIDE, padded_width * 4);
etna_set_state(ctx, VIVS_GL_MULTI_SAMPLE_CONFIG,
ETNA_MASKED_INL(VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES, NONE) &
ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES, 0xf) &
ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12, 0x0) &
ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16, 0x0)
);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR);
etna_set_state(ctx, VIVS_PE_COLOR_FORMAT, ETNA_MASKED_BIT(VIVS_PE_COLOR_FORMAT_OVERWRITE, 1));
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR);
etna_set_state(ctx, VIVS_TS_COLOR_CLEAR_VALUE, 0);
etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts->address); /* ADDR_B */
etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt->address); /* ADDR_A */
etna_set_state(ctx, VIVS_TS_MEM_CONFIG, VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR); /* ADDR_A */
etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG,
ETNA_MASKED_INL(VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT, D16) &
ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_SUPER_TILED, 1)
);
etna_set_state(ctx, VIVS_PE_DEPTH_ADDR, z->address); /* ADDR_C */
etna_set_state(ctx, VIVS_PE_DEPTH_STRIDE, padded_width * 2);
etna_set_state(ctx, VIVS_PE_STENCIL_CONFIG, ETNA_MASKED_INL(VIVS_PE_STENCIL_CONFIG_MODE, DISABLED));
etna_set_state(ctx, VIVS_PE_HDEPTH_CONTROL, VIVS_PE_HDEPTH_CONTROL_FORMAT_DISABLED);
etna_set_state_f32(ctx, VIVS_PE_DEPTH_NORMALIZE, 65535.0);
etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_EARLY_Z, 0));
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_DEPTH);
etna_set_state(ctx, VIVS_TS_DEPTH_CLEAR_VALUE, 0xffffffff);
etna_set_state(ctx, VIVS_TS_DEPTH_STATUS_BASE, z_ts->address); /* ADDR_D */
etna_set_state(ctx, VIVS_TS_DEPTH_SURFACE_BASE, z->address); /* ADDR_C */
etna_set_state(ctx, VIVS_TS_MEM_CONFIG,
VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR |
VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR |
VIVS_TS_MEM_CONFIG_DEPTH_16BPP |
VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION);
etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_EARLY_Z, 1)); /* flip-flopping once again */
/* Warm up RS on aux render target */
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_warm_up_rs(ctx, aux_rt->address, aux_rt_ts->address);
/* Phew, now that's one hell of a setup; the serious rendering starts now */
etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts->address); /* ADDR_B */
etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt->address); /* ADDR_A */
/* ... or so we thought */
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_warm_up_rs(ctx, aux_rt->address, aux_rt_ts->address);
/* maybe now? */
etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts->address); /* ADDR_B */
etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt->address); /* ADDR_A */
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
/* nope, not really... */
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_warm_up_rs(ctx, aux_rt->address, aux_rt_ts->address);
etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts->address); /* ADDR_B */
etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt->address); /* ADDR_A */
etna_stall(ctx, SYNC_RECIPIENT_RA, SYNC_RECIPIENT_PE);
/* Set up the resolve to clear tile status for main render target
* What the blob does is regard the TS as an image of width N, height 4, with 4 bytes per pixel
* Looks like the height always stays the same. I don't think it matters as long as the entire memory are is covered.
* XXX need to clear the depth ts too.
* */
etna_set_state(ctx, VIVS_RS_CONFIG,
VIVS_RS_CONFIG_SOURCE_FORMAT(RS_FORMAT_A8R8G8B8) |
VIVS_RS_CONFIG_DEST_FORMAT(RS_FORMAT_A8R8G8B8)
);
etna_set_state_multi(ctx, VIVS_RS_DITHER(0), 2, (uint32_t[]){0xffffffff, 0xffffffff});
etna_set_state(ctx, VIVS_RS_DEST_ADDR, rt_ts->address); /* ADDR_B */
etna_set_state(ctx, VIVS_RS_DEST_STRIDE, 0x100); /* 0x100 iso 0x40! seems it uses a width of 256 if width divisible by 256, XXX need to figure out these rules */
etna_set_state(ctx, VIVS_RS_WINDOW_SIZE,
VIVS_RS_WINDOW_SIZE_HEIGHT(rt_ts_size/0x100) |
VIVS_RS_WINDOW_SIZE_WIDTH(64));
etna_set_state(ctx, VIVS_RS_FILL_VALUE(0), 0x55555555);
etna_set_state(ctx, VIVS_RS_CLEAR_CONTROL,
VIVS_RS_CLEAR_CONTROL_MODE_ENABLED1 |
VIVS_RS_CLEAR_CONTROL_BITS(0xffff));
etna_set_state(ctx, VIVS_RS_EXTRA_CONFIG,
0); /* no AA, no endian switch */
etna_set_state(ctx, VIVS_RS_KICKER,
0xbeebbeeb);
etna_set_state(ctx, VIVS_TS_COLOR_CLEAR_VALUE, 0xff7f7f7f);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR);
etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts->address); /* ADDR_B */
etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt->address); /* ADDR_A */
etna_set_state(ctx, VIVS_TS_MEM_CONFIG,
VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR |
VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR |
VIVS_TS_MEM_CONFIG_DEPTH_16BPP |
VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE, 0));
etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED_INL(VIVS_PE_DEPTH_CONFIG_DEPTH_MODE, NONE));
etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED(VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC, COMPARE_FUNC_ALWAYS));
etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED_INL(VIVS_PE_DEPTH_CONFIG_DEPTH_MODE, Z));
etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_ONLY_DEPTH, 0));
etna_set_state_f32(ctx, VIVS_PE_DEPTH_NEAR, 0.0);
etna_set_state_f32(ctx, VIVS_PE_DEPTH_FAR, 1.0);
etna_set_state_f32(ctx, VIVS_PE_DEPTH_NORMALIZE, 65535.0);
/* set up primitive assembly */
etna_set_state_f32(ctx, VIVS_PA_VIEWPORT_OFFSET_Z, 0.0);
etna_set_state_f32(ctx, VIVS_PA_VIEWPORT_SCALE_Z, 1.0);
etna_set_state_fixp(ctx, VIVS_PA_VIEWPORT_OFFSET_X, width << 15);
etna_set_state_fixp(ctx, VIVS_PA_VIEWPORT_OFFSET_Y, height << 15);
etna_set_state_fixp(ctx, VIVS_PA_VIEWPORT_SCALE_X, width << 15);
etna_set_state_fixp(ctx, VIVS_PA_VIEWPORT_SCALE_Y, height << 15);
etna_set_state_fixp(ctx, VIVS_SE_SCISSOR_LEFT, 0);
etna_set_state_fixp(ctx, VIVS_SE_SCISSOR_TOP, 0);
etna_set_state_fixp(ctx, VIVS_SE_SCISSOR_RIGHT, (width << 16) | 5);
etna_set_state_fixp(ctx, VIVS_SE_SCISSOR_BOTTOM, (height << 16) | 5);
/* shader setup */
etna_set_state(ctx, VIVS_VS_END_PC, vs_size/16);
etna_set_state_multi(ctx, VIVS_VS_INPUT_COUNT, 3, (uint32_t[]){
/* VIVS_VS_INPUT_COUNT */ (1<<8) | 2,
/* VIVS_VS_TEMP_REGISTER_CONTROL */ VIVS_VS_TEMP_REGISTER_CONTROL_NUM_TEMPS(2),
/* VIVS_VS_OUTPUT(0) */ 0x100});
etna_set_state(ctx, VIVS_VS_START_PC, 0x0);
etna_set_state_f32(ctx, VIVS_VS_UNIFORMS(0), 0.5); /* u0.x */
etna_set_state_multi(ctx, VIVS_VS_INST_MEM(0), vs_size/4, vs);
etna_set_state(ctx, VIVS_RA_CONTROL, 0x3); /* huh, this is 1 for the cubes */
etna_set_state_multi(ctx, VIVS_PS_END_PC, 2, (uint32_t[]){
/* VIVS_PS_END_PC */ ps_size/16,
/* VIVS_PS_OUTPUT_REG */ 0x1});
etna_set_state(ctx, VIVS_PS_START_PC, 0x0);
etna_set_state(ctx, VIVS_PA_SHADER_ATTRIBUTES(0), 0x200);
etna_set_state(ctx, VIVS_GL_VARYING_NUM_COMPONENTS, /* one varying, with four components */
VIVS_GL_VARYING_NUM_COMPONENTS_VAR0(2)
);
etna_set_state_multi(ctx, VIVS_GL_VARYING_COMPONENT_USE(0), 2, (uint32_t[]){ /* one varying, with four components */
VIVS_GL_VARYING_COMPONENT_USE_COMP0(VARYING_COMPONENT_USE_USED) |
VIVS_GL_VARYING_COMPONENT_USE_COMP1(VARYING_COMPONENT_USE_USED) |
VIVS_GL_VARYING_COMPONENT_USE_COMP2(VARYING_COMPONENT_USE_UNUSED) |
VIVS_GL_VARYING_COMPONENT_USE_COMP3(VARYING_COMPONENT_USE_UNUSED)
, 0
});
etna_set_state_f32(ctx, VIVS_PS_UNIFORMS(0), 0.0); /* u0.x */
etna_set_state_f32(ctx, VIVS_PS_UNIFORMS(1), 1.0); /* u0.y */
etna_set_state_f32(ctx, VIVS_PS_UNIFORMS(2), 0.5); /* u0.z */
etna_set_state_f32(ctx, VIVS_PS_UNIFORMS(3), 2.0); /* u0.w */
etna_set_state_f32(ctx, VIVS_PS_UNIFORMS(4), 1/256.0); /* u1.x */
etna_set_state_f32(ctx, VIVS_PS_UNIFORMS(5), 16.0); /* u1.y */
etna_set_state_f32(ctx, VIVS_PS_UNIFORMS(6), 10.0); /* u1.z */
etna_set_state_f32(ctx, VIVS_PS_UNIFORMS(8), frame); /* u2.x */
etna_set_state_multi(ctx, VIVS_PS_INST_MEM(0), ps_size/4, ps);
etna_set_state(ctx, VIVS_PS_INPUT_COUNT, (31<<8)|2);
etna_set_state(ctx, VIVS_PS_TEMP_REGISTER_CONTROL,
VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS(4));
etna_set_state(ctx, VIVS_PS_CONTROL,
VIVS_PS_CONTROL_UNK1
);
etna_set_state(ctx, VIVS_PA_ATTRIBUTE_ELEMENT_COUNT, 0x100);
etna_set_state(ctx, VIVS_GL_VARYING_TOTAL_COMPONENTS, /* one varying, with two components, must be
changed together with GL_PS_VARYING_NUM_COMPONENTS */
VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM(2)
);
etna_set_state(ctx, VIVS_VS_LOAD_BALANCING, 0xf3f0582);
etna_set_state(ctx, VIVS_VS_OUTPUT_COUNT, 2);
etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_BIT(VIVS_PA_CONFIG_POINT_SIZE_ENABLE, 0));
etna_set_state(ctx, VIVS_FE_VERTEX_STREAM_BASE_ADDR, vtx->address); /* ADDR_E */
etna_set_state(ctx, VIVS_FE_VERTEX_STREAM_CONTROL,
VIVS_FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE(0x14));
etna_set_state(ctx, VIVS_FE_VERTEX_ELEMENT_CONFIG(0),
VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_FLOAT |
VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN(ENDIAN_MODE_NO_SWAP) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM(0) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM(3) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_OFF |
VIVS_FE_VERTEX_ELEMENT_CONFIG_START(0x0) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_END(0xc));
etna_set_state(ctx, VIVS_FE_VERTEX_ELEMENT_CONFIG(1),
VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_FLOAT |
VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN(ENDIAN_MODE_NO_SWAP) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_NONCONSECUTIVE |
VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM(0) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM(2) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_OFF |
VIVS_FE_VERTEX_ELEMENT_CONFIG_START(0xc) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_END(0x14));
etna_set_state(ctx, VIVS_VS_INPUT(0), 0x00100); /* 0x20000 in etna_cube */
etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_BIT(VIVS_PA_CONFIG_POINT_SPRITE_ENABLE, 0));
etna_draw_primitives(ctx, PRIMITIVE_TYPE_TRIANGLE_STRIP, 0, 2);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
/* Submit first command buffer */
etna_flush(ctx);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_set_state(ctx, VIVS_RS_CONFIG,
VIVS_RS_CONFIG_SOURCE_FORMAT(RS_FORMAT_A8R8G8B8) |
VIVS_RS_CONFIG_SOURCE_TILED |
VIVS_RS_CONFIG_DEST_FORMAT(RS_FORMAT_A8R8G8B8) |
VIVS_RS_CONFIG_DEST_TILED);
etna_set_state(ctx, VIVS_RS_SOURCE_STRIDE, (padded_width * 4 * 4) | VIVS_RS_SOURCE_STRIDE_TILING);
etna_set_state(ctx, VIVS_RS_DEST_STRIDE, (padded_width * 4 * 4) | VIVS_RS_DEST_STRIDE_TILING);
etna_set_state(ctx, VIVS_RS_DITHER(0), 0xffffffff);
etna_set_state(ctx, VIVS_RS_DITHER(1), 0xffffffff);
etna_set_state(ctx, VIVS_RS_CLEAR_CONTROL, VIVS_RS_CLEAR_CONTROL_MODE_DISABLED);
etna_set_state(ctx, VIVS_RS_EXTRA_CONFIG, 0); /* no AA, no endian switch */
etna_set_state(ctx, VIVS_RS_SOURCE_ADDR, rt->address); /* ADDR_A */
etna_set_state(ctx, VIVS_RS_DEST_ADDR, rt->address); /* ADDR_A */
etna_set_state(ctx, VIVS_RS_WINDOW_SIZE,
VIVS_RS_WINDOW_SIZE_HEIGHT(padded_height) |
VIVS_RS_WINDOW_SIZE_WIDTH(padded_width));
etna_set_state(ctx, VIVS_RS_KICKER, 0xbeebbeeb);
/* Submit second command buffer */
etna_flush(ctx);
etna_warm_up_rs(ctx, aux_rt->address, aux_rt_ts->address);
etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts->address); /* ADDR_B */
etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt->address); /* ADDR_A */
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR);
etna_set_state(ctx, VIVS_TS_MEM_CONFIG,
VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR |
VIVS_TS_MEM_CONFIG_DEPTH_16BPP |
VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR);
etna_set_state(ctx, VIVS_PE_COLOR_FORMAT,
ETNA_MASKED_BIT(VIVS_PE_COLOR_FORMAT_OVERWRITE, 0));
/* Submit third command buffer, wait for pixel engine to finish */
etna_finish(ctx);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_set_state(ctx, VIVS_RS_CONFIG,
VIVS_RS_CONFIG_SOURCE_FORMAT(RS_FORMAT_A8R8G8B8) |
VIVS_RS_CONFIG_SOURCE_TILED |
VIVS_RS_CONFIG_DEST_FORMAT(RS_FORMAT_A8R8G8B8) /*|
VIVS_RS_CONFIG_SWAP_RB*/);
etna_set_state(ctx, VIVS_RS_SOURCE_STRIDE, (padded_width * 4 * 4) | VIVS_RS_SOURCE_STRIDE_TILING);
etna_set_state(ctx, VIVS_RS_DEST_STRIDE, fb.fb_fix.line_length);
etna_set_state(ctx, VIVS_RS_DITHER(0), 0xffffffff);
etna_set_state(ctx, VIVS_RS_DITHER(1), 0xffffffff);
etna_set_state(ctx, VIVS_RS_CLEAR_CONTROL, VIVS_RS_CLEAR_CONTROL_MODE_DISABLED);
etna_set_state(ctx, VIVS_RS_EXTRA_CONFIG,
0); /* no AA, no endian switch */
etna_set_state(ctx, VIVS_RS_SOURCE_ADDR, rt->address); /* ADDR_A */
etna_set_state(ctx, VIVS_RS_DEST_ADDR, fb.physical[backbuffer]); /* ADDR_J */
etna_set_state(ctx, VIVS_RS_WINDOW_SIZE,
VIVS_RS_WINDOW_SIZE_HEIGHT(height) |
VIVS_RS_WINDOW_SIZE_WIDTH(width));
etna_set_state(ctx, VIVS_RS_KICKER, 0xbeebbeeb);
etna_finish(ctx);
/* switch buffers */
fb_set_buffer(&fb, backbuffer);
backbuffer = 1-backbuffer;
}
/* Unlock video memory */
if(etna_vidmem_unlock(conn, bmp) != 0)
{
fprintf(stderr, "Cannot unlock vidmem\n");
exit(1);
}
etna_free(ctx);
viv_close(conn);
return 0;
}
int main(int argc, char **argv)
{
int rv;
fb_info fb;
rv = fb_open(0, &fb);
if(rv!=0)
{
exit(1);
}
fb_set_buffer(&fb, 0);
rv = viv_open();
if(rv!=0)
{
fprintf(stderr, "Error opening device\n");
exit(1);
}
printf("Succesfully opened device\n");
/* allocate command buffer (blob uses four command buffers, but we don't even fill one) */
viv_addr_t buf0_physical = 0;
void *buf0_logical = 0;
if(viv_alloc_contiguous(0x8000, &buf0_physical, &buf0_logical, NULL)!=0)
{
fprintf(stderr, "Error allocating host memory\n");
exit(1);
}
printf("Allocated buffer: phys=%08x log=%08x\n", (uint32_t)buf0_physical, (uint32_t)buf0_logical);
/* allocate main render target */
gcuVIDMEM_NODE_PTR rt_node = 0;
if(viv_alloc_linear_vidmem(0x70000, 0x40, gcvSURF_RENDER_TARGET, gcvPOOL_DEFAULT, &rt_node, NULL)!=0)
{
fprintf(stderr, "Error allocating render target buffer memory\n");
exit(1);
}
printf("Allocated render target node: node=%08x\n", (uint32_t)rt_node);
viv_addr_t rt_physical = 0;
void *rt_logical = 0;
if(viv_lock_vidmem(rt_node, &rt_physical, &rt_logical)!=0)
{
fprintf(stderr, "Error locking render target memory\n");
exit(1);
}
printf("Locked render target: phys=%08x log=%08x\n", (uint32_t)rt_physical, (uint32_t)rt_logical);
memset(rt_logical, 0xff, 0x70000); /* clear previous result just in case, test that clearing works */
/* allocate tile status for main render target */
gcuVIDMEM_NODE_PTR rt_ts_node = 0;
if(viv_alloc_linear_vidmem(0x700, 0x40, gcvSURF_TILE_STATUS, gcvPOOL_DEFAULT, &rt_ts_node, NULL)!=0)
{
fprintf(stderr, "Error allocating render target tile status memory\n");
exit(1);
}
printf("Allocated render target tile status node: node=%08x\n", (uint32_t)rt_ts_node);
viv_addr_t rt_ts_physical = 0;
void *rt_ts_logical = 0;
if(viv_lock_vidmem(rt_ts_node, &rt_ts_physical, &rt_ts_logical)!=0)
{
fprintf(stderr, "Error locking render target memory\n");
exit(1);
}
printf("Locked render target ts: phys=%08x log=%08x\n", (uint32_t)rt_ts_physical, (uint32_t)rt_ts_logical);
/* allocate depth for main render target */
gcuVIDMEM_NODE_PTR z_node = 0;
if(viv_alloc_linear_vidmem(0x38000, 0x40, gcvSURF_DEPTH, gcvPOOL_DEFAULT, &z_node, NULL)!=0)
{
fprintf(stderr, "Error allocating depth memory\n");
exit(1);
}
printf("Allocated depth node: node=%08x\n", (uint32_t)z_node);
viv_addr_t z_physical = 0;
void *z_logical = 0;
if(viv_lock_vidmem(z_node, &z_physical, &z_logical)!=0)
{
fprintf(stderr, "Error locking depth target memory\n");
exit(1);
}
printf("Locked depth target: phys=%08x log=%08x\n", (uint32_t)z_physical, (uint32_t)z_logical);
/* allocate depth ts for main render target */
gcuVIDMEM_NODE_PTR z_ts_node = 0;
if(viv_alloc_linear_vidmem(0x400, 0x40, gcvSURF_TILE_STATUS, gcvPOOL_DEFAULT, &z_ts_node, NULL)!=0)
{
fprintf(stderr, "Error allocating depth memory\n");
exit(1);
}
printf("Allocated depth ts node: node=%08x\n", (uint32_t)z_ts_node);
viv_addr_t z_ts_physical = 0;
void *z_ts_logical = 0;
if(viv_lock_vidmem(z_ts_node, &z_ts_physical, &z_ts_logical)!=0)
{
fprintf(stderr, "Error locking depth target ts memory\n");
exit(1);
}
printf("Locked depth ts target: phys=%08x log=%08x\n", (uint32_t)z_ts_physical, (uint32_t)z_ts_logical);
/* allocate vertex buffer */
gcuVIDMEM_NODE_PTR vtx_node = 0;
if(viv_alloc_linear_vidmem(0x60000, 0x40, gcvSURF_VERTEX, gcvPOOL_DEFAULT, &vtx_node, NULL)!=0)
{
fprintf(stderr, "Error allocating vertex memory\n");
exit(1);
}
printf("Allocated vertex node: node=%08x\n", (uint32_t)vtx_node);
viv_addr_t vtx_physical = 0;
void *vtx_logical = 0;
if(viv_lock_vidmem(vtx_node, &vtx_physical, &vtx_logical)!=0)
{
fprintf(stderr, "Error locking vertex memory\n");
exit(1);
}
printf("Locked vertex memory: phys=%08x log=%08x\n", (uint32_t)vtx_physical, (uint32_t)vtx_logical);
/* allocate aux render target */
gcuVIDMEM_NODE_PTR aux_rt_node = 0;
if(viv_alloc_linear_vidmem(0x4000, 0x40, gcvSURF_RENDER_TARGET, gcvPOOL_SYSTEM /*why?*/, &aux_rt_node, NULL)!=0)
{
fprintf(stderr, "Error allocating aux render target buffer memory\n");
exit(1);
}
printf("Allocated aux render target node: node=%08x\n", (uint32_t)aux_rt_node);
viv_addr_t aux_rt_physical = 0;
void *aux_rt_logical = 0;
if(viv_lock_vidmem(aux_rt_node, &aux_rt_physical, &aux_rt_logical)!=0)
{
fprintf(stderr, "Error locking aux render target memory\n");
exit(1);
}
printf("Locked aux render target: phys=%08x log=%08x\n", (uint32_t)aux_rt_physical, (uint32_t)aux_rt_logical);
/* allocate tile status for aux render target */
gcuVIDMEM_NODE_PTR aux_rt_ts_node = 0;
if(viv_alloc_linear_vidmem(0x100, 0x40, gcvSURF_TILE_STATUS, gcvPOOL_DEFAULT, &aux_rt_ts_node, NULL)!=0)
{
fprintf(stderr, "Error allocating aux render target tile status memory\n");
exit(1);
}
printf("Allocated aux render target tile status node: node=%08x\n", (uint32_t)aux_rt_ts_node);
viv_addr_t aux_rt_ts_physical = 0;
void *aux_rt_ts_logical = 0;
if(viv_lock_vidmem(aux_rt_ts_node, &aux_rt_ts_physical, &aux_rt_ts_logical)!=0)
{
fprintf(stderr, "Error locking aux ts render target memory\n");
exit(1);
}
printf("Locked aux render target ts: phys=%08x log=%08x\n", (uint32_t)aux_rt_ts_physical, (uint32_t)aux_rt_ts_logical);
/* Phew, now we got all the memory we need.
* Write interleaved attribute vertex stream.
* Unlike the GL example we only do this once, not every time glDrawArrays is called, the same would be accomplished
* from GL by using a vertex buffer object.
*/
for(int vert=0; vert<NUM_VERTICES; ++vert)
{
int src_idx = vert * COMPONENTS_PER_VERTEX;
int dest_idx = vert * COMPONENTS_PER_VERTEX * 3;
for(int comp=0; comp<COMPONENTS_PER_VERTEX; ++comp)
{
((float*)vtx_logical)[dest_idx+comp+0] = vVertices[src_idx + comp]; /* 0 */
((float*)vtx_logical)[dest_idx+comp+3] = vNormals[src_idx + comp]; /* 1 */
((float*)vtx_logical)[dest_idx+comp+6] = vColors[src_idx + comp]; /* 2 */
}
}
/*
for(int idx=0; idx<NUM_VERTICES*3*3; ++idx)
{
printf("%i %f\n", idx, ((float*)vtx_logical)[idx]);
}*/
/* Load the command buffer and send the commit command. */
/* First build context state map */
size_t stateCount = 0x1d00;
uint32_t *contextMap = malloc(stateCount * 4);
memset(contextMap, 0, stateCount*4);
for(int idx=0; idx<sizeof(contextbuf_addr)/sizeof(address_index_t); ++idx)
{
contextMap[contextbuf_addr[idx].address / 4] = contextbuf_addr[idx].index;
}
struct _gcoCMDBUF commandBuffer = {
.object = {
.type = gcvOBJ_COMMANDBUFFER
},
//.os = (_gcoOS*)0xbf7488,
//.hardware = (_gcoHARDWARE*)0x402694e0,
.physical = (void*)buf0_physical,
.logical = (void*)buf0_logical,
.bytes = 0x8000,
.startOffset = 0x0,
//.offset = 0xac0,
//.free = 0x7520,
//.hintTable = (unsigned int*)0x0, // Used when gcdSECURE
//.hintIndex = (unsigned int*)0x58, // Used when gcdSECURE
//.hintCommit = (unsigned int*)0xffffffff // Used when gcdSECURE
};
struct _gcoCONTEXT contextBuffer = {
.object = {
.type = gcvOBJ_CONTEXT
},
//.os = (_gcoOS*)0xbf7488,
//.hardware = (_gcoHARDWARE*)0x402694e0,
.id = 0x0, // Actual ID will be returned here
.map = contextMap,
.stateCount = stateCount,
//.hint = (unsigned char*)0x0, // Used when gcdSECURE
//.hintValue = 2, // Used when gcdSECURE
//.hintCount = 0xca, // Used when gcdSECURE
.buffer = contextbuf,
.pipe3DIndex = 0x2d6, // XXX should not be hardcoded
.pipe2DIndex = 0x106e,
.linkIndex = 0x1076,
.inUseIndex = 0x1078,
.bufferSize = 0x41e4,
.bytes = 0x0, // Number of bytes at physical, logical
.physical = (void*)0x0,
.logical = (void*)0x0,
.link = (void*)0x0, // Logical address of link
.initialPipe = 0x1,
.entryPipe = 0x0,
.currentPipe = 0x0,
.postCommit = 1,
.inUse = (int*)0x0, // Logical address of inUse
.lastAddress = 0xffffffff, // Not used by kernel
.lastSize = 0x2, // Not used by kernel
.lastIndex = 0x106a, // Not used by kernel
.lastFixed = 0, // Not used by kernel
//.hintArray = (unsigned int*)0x0, // Used when gcdSECURE
//.hintIndex = (unsigned int*)0x0 // Used when gcdSECURE
};
commandBuffer.free = commandBuffer.bytes - 0x8; /* Always keep 0x8 at end of buffer for kernel driver */
/* Set addresses in first command buffer */
cmdbuf1[0x57] = cmdbuf1[0x67] = cmdbuf1[0x9f] = cmdbuf1[0xbb] = cmdbuf1[0xd9] = cmdbuf1[0xfb] = rt_physical;
cmdbuf1[0x65] = cmdbuf1[0x9d] = cmdbuf1[0xb9] = cmdbuf1[0xd7] = cmdbuf1[0xe5] = cmdbuf1[0xf9] = rt_ts_physical;
cmdbuf1[0x6d] = cmdbuf1[0x7f] = z_physical;
cmdbuf1[0x7d] = z_ts_physical;
cmdbuf1[0x87] = cmdbuf1[0xa3] = cmdbuf1[0xc1] = aux_rt_ts_physical;
cmdbuf1[0x89] = cmdbuf1[0x8f] = cmdbuf1[0x93]
= cmdbuf1[0xa5] = cmdbuf1[0xab] = cmdbuf1[0xaf]
= cmdbuf1[0xc3] = cmdbuf1[0xc9] = cmdbuf1[0xcd] = aux_rt_physical;
cmdbuf1[0x1f3] = cmdbuf1[0x215] = cmdbuf1[0x237]
= cmdbuf1[0x259] = cmdbuf1[0x27b] = cmdbuf1[0x29d] = vtx_physical;
/* Submit first command buffer */
commandBuffer.startOffset = 0;
memcpy((void*)((size_t)commandBuffer.logical + commandBuffer.startOffset), cmdbuf1, sizeof(cmdbuf1));
commandBuffer.offset = commandBuffer.startOffset + sizeof(cmdbuf1);
commandBuffer.free -= sizeof(cmdbuf1) + 0x18;
printf("[1] startOffset=%08x, offset=%08x, free=%08x\n", (uint32_t)commandBuffer.startOffset, (uint32_t)commandBuffer.offset, (uint32_t)commandBuffer.free);
if(viv_commit(&commandBuffer, &contextBuffer) != 0)
{
fprintf(stderr, "Error committing first command buffer\n");
exit(1);
}
/* After the first COMMIT, allocate contiguous memory for context and set
* bytes, physical, logical, link, inUse */
printf("Context assigned index: %i\n", (uint32_t)contextBuffer.id);
viv_addr_t cbuf0_physical = 0;
void *cbuf0_logical = 0;
size_t cbuf0_bytes = 0;
if(viv_alloc_contiguous(contextBuffer.bufferSize, &cbuf0_physical, &cbuf0_logical, &cbuf0_bytes)!=0)
{
fprintf(stderr, "Error allocating contiguous host memory for context\n");
exit(1);
}
printf("Allocated buffer (size 0x%x) for context: phys=%08x log=%08x\n", (int)cbuf0_bytes, (int)cbuf0_physical, (int)cbuf0_logical);
contextBuffer.bytes = cbuf0_bytes; /* actual size of buffer */
contextBuffer.physical = (void*)cbuf0_physical;
contextBuffer.logical = cbuf0_logical;
contextBuffer.link = ((uint32_t*)cbuf0_logical) + contextBuffer.linkIndex;
contextBuffer.inUse = (gctBOOL*)(((uint32_t*)cbuf0_logical) + contextBuffer.inUseIndex);
*contextBuffer.inUse = 0;
/* Submit second command buffer, with updated context.
* Second command buffer fills the background.
*/
cmdbuf2[0x1d] = cmdbuf2[0x1f] = rt_physical;
commandBuffer.startOffset = commandBuffer.offset + 0x18; /* Make space for LINK */
memcpy((void*)((size_t)commandBuffer.logical + commandBuffer.startOffset), cmdbuf2, sizeof(cmdbuf2));
commandBuffer.offset = commandBuffer.startOffset + sizeof(cmdbuf2);
commandBuffer.free -= sizeof(cmdbuf2) + 0x18;
printf("[2] startOffset=%08x, offset=%08x, free=%08x\n", (uint32_t)commandBuffer.startOffset, (uint32_t)commandBuffer.offset, (uint32_t)commandBuffer.free);
if(viv_commit(&commandBuffer, &contextBuffer) != 0)
{
fprintf(stderr, "Error committing second command buffer\n");
exit(1);
}
/* Submit third command buffer, with updated context
* Third command buffer does some cache flush trick?
* It can be left out without any visible harm.
**/
cmdbuf3[0x9] = aux_rt_ts_physical;
cmdbuf3[0xb] = cmdbuf3[0x11] = cmdbuf3[0x15] = aux_rt_physical;
cmdbuf3[0x1f] = rt_ts_physical;
cmdbuf3[0x21] = rt_physical;
commandBuffer.startOffset = commandBuffer.offset + 0x18;
memcpy((void*)((size_t)commandBuffer.logical + commandBuffer.startOffset), cmdbuf3, sizeof(cmdbuf3));
commandBuffer.offset = commandBuffer.startOffset + sizeof(cmdbuf3);
commandBuffer.free -= sizeof(cmdbuf3) + 0x18;
printf("[3] startOffset=%08x, offset=%08x, free=%08x\n", (uint32_t)commandBuffer.startOffset, (uint32_t)commandBuffer.offset, (uint32_t)commandBuffer.free);
if(viv_commit(&commandBuffer, &contextBuffer) != 0)
{
fprintf(stderr, "Error committing third command buffer\n");
exit(1);
}
/* Submit event queue with SIGNAL, fromWhere=gcvKERNEL_PIXEL (wait for pixel engine to finish) */
int sig_id = 0;
if(viv_user_signal_create(0, &sig_id) != 0) /* automatic resetting signal */
{
fprintf(stderr, "Cannot create user signal\n");
exit(1);
}
printf("Created user signal %i\n", sig_id);
if(viv_event_queue_signal(sig_id, gcvKERNEL_PIXEL) != 0)
{
fprintf(stderr, "Cannot queue GPU signal\n");
exit(1);
}
/* Wait for signal */
if(viv_user_signal_wait(sig_id, SIG_WAIT_INDEFINITE) != 0)
{
fprintf(stderr, "Cannot wait for signal\n");
exit(1);
}
/* Allocate video memory for BITMAP, lock */
gcuVIDMEM_NODE_PTR bmp_node = 0;
if(viv_alloc_linear_vidmem(0x5dc00, 0x40, gcvSURF_BITMAP, gcvPOOL_DEFAULT, &bmp_node, NULL)!=0)
{
fprintf(stderr, "Error allocating bitmap status memory\n");
exit(1);
}
printf("Allocated bitmap node: node=%08x\n", (uint32_t)bmp_node);
viv_addr_t bmp_physical = 0;
void *bmp_logical = 0;
if(viv_lock_vidmem(bmp_node, &bmp_physical, &bmp_logical)!=0)
{
fprintf(stderr, "Error locking bmp memory\n");
exit(1);
}
memset(bmp_logical, 0xff, 0x5dc00); /* clear previous result */
printf("Locked bmp: phys=%08x log=%08x\n", (uint32_t)bmp_physical, (uint32_t)bmp_logical);
/* Submit fourth command buffer, updating context.
* Fourth command buffer copies render result to bitmap, detiling along the way.
*/
cmdbuf4[0x0f] = fb.fb_fix.line_length;
cmdbuf4[0x19] = rt_physical;
cmdbuf4[0x1b] = fb.physical[0];
fb_set_buffer(&fb, 0);
/* XXX gcvHAL_MAP_USER_MEMORY to get dma-able address, or does this work as-is? */
commandBuffer.startOffset = commandBuffer.offset + 0x18;
memcpy((void*)((size_t)commandBuffer.logical + commandBuffer.startOffset), cmdbuf4, sizeof(cmdbuf4));
commandBuffer.offset = commandBuffer.startOffset + sizeof(cmdbuf4);
commandBuffer.free -= sizeof(cmdbuf4) + 0x18;
printf("[4] startOffset=%08x, offset=%08x, free=%08x\n", (uint32_t)commandBuffer.startOffset, (uint32_t)commandBuffer.offset, (uint32_t)commandBuffer.free);
if(viv_commit(&commandBuffer, &contextBuffer) != 0)
{
fprintf(stderr, "Error committing fourth command buffer\n");
exit(1);
}
/* Submit event queue with SIGNAL, fromWhere=gcvKERNEL_PIXEL */
if(viv_event_queue_signal(sig_id, gcvKERNEL_PIXEL) != 0)
{
fprintf(stderr, "Cannot queue GPU signal\n");
exit(1);
}
/* Wait for signal */
if(viv_user_signal_wait(sig_id, SIG_WAIT_INDEFINITE) != 0)
{
fprintf(stderr, "Cannot wait for signal\n");
exit(1);
}
bmp_dump32(bmp_logical, 400, 240, false, "/mnt/sdcard/replay.bmp");
/* Unlock video memory */
if(viv_unlock_vidmem(bmp_node, gcvSURF_BITMAP, 1) != 0)
{
fprintf(stderr, "Cannot unlock vidmem\n");
exit(1);
}
/*
for(int x=0; x<0x700; ++x)
{
uint32_t value = ((uint32_t*)rt_ts_logical)[x];
printf("Sample ts: %x %08x\n", x*4, value);
}*/
printf("Contextbuffer used %i\n", *contextBuffer.inUse);
viv_close();
return 0;
}
int main(int argc, char **argv)
{
int rv;
int width = 256;
int height = 256;
int padded_width, padded_height;
int backbuffer = 0;
struct fb_info fb;
rv = fb_open(0, &fb);
if(rv!=0)
{
exit(1);
}
width = fb.fb_var.xres;
height = fb.fb_var.yres;
padded_width = etna_align_up(width, 64);
padded_height = etna_align_up(height, 64);
printf("padded_width %i padded_height %i\n", padded_width, padded_height);
struct viv_conn *conn = 0;
rv = viv_open(VIV_HW_3D, &conn);
if(rv!=0)
{
fprintf(stderr, "Error opening device\n");
exit(1);
}
printf("Succesfully opened device\n");
struct etna_vidmem *rt = 0; /* main render target */
struct etna_vidmem *rt_ts = 0; /* tile status for main render target */
struct etna_vidmem *z = 0; /* depth for main render target */
struct etna_vidmem *z_ts = 0; /* depth ts for main render target */
struct etna_vidmem *aux_rt = 0; /* auxilary render target */
struct etna_vidmem *aux_rt_ts = 0; /* tile status for auxilary render target */
size_t rt_size = padded_width * padded_height * 4;
size_t rt_ts_size = etna_align_up((padded_width * padded_height * 4)/0x100, 0x100);
size_t z_size = padded_width * padded_height * 2;
size_t z_ts_size = etna_align_up((padded_width * padded_height * 2)/0x100, 0x100);
if(etna_vidmem_alloc_linear(conn, &rt, rt_size, gcvSURF_RENDER_TARGET, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(conn, &rt_ts, rt_ts_size, gcvSURF_TILE_STATUS, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(conn, &z, z_size, gcvSURF_DEPTH, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(conn, &z_ts, z_ts_size, gcvSURF_TILE_STATUS, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(conn, &aux_rt, 0x4000, gcvSURF_RENDER_TARGET, gcvPOOL_SYSTEM, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(conn, &aux_rt_ts, 0x100, gcvSURF_TILE_STATUS, gcvPOOL_DEFAULT, true)!=ETNA_OK
)
{
fprintf(stderr, "Error allocating video memory\n");
exit(1);
}
struct etna_ctx *ctx = 0;
if(etna_create(conn, &ctx) != ETNA_OK)
{
printf("Unable to create context\n");
exit(1);
}
memset(rt_ts->logical, 0x55, rt_ts->size); // Pattern: cleared
//memset(rt_ts->logical, 0xAA, rt_ts->size); // Pattern: weird pattern fill
//memset(rt_ts->logical, 0x00, rt_ts->size); // Pattern: filled in (nothing to do)
//memset(rt_ts->logical, 0xFF, rt_ts->size); // Pattern: weird pattern fill
uint32_t pixelfmt = RS_FORMAT_X8R8G8B8;
bool supertiled = true;
bool tiled = true;
uint32_t stride = 0;
if(tiled)
{
stride = (padded_width * 4 * 4) | (supertiled?VIVS_RS_DEST_STRIDE_TILING:0);
} else {
stride = (padded_width * 4) | (supertiled?VIVS_RS_DEST_STRIDE_TILING:0);
}
for(int frame=0; frame<1; ++frame)
{
if(frame%50 == 0)
printf("*** FRAME %i ****\n", frame);
/* XXX part of this can be put outside the loop, but until we have usable context management
* this is safest.
*/
etna_set_state(ctx, VIVS_GL_VERTEX_ELEMENT_CONFIG, 0x1);
etna_set_state(ctx, VIVS_RA_CONTROL, 0x1);
etna_set_state(ctx, VIVS_PA_W_CLIP_LIMIT, 0x34000001);
etna_set_state(ctx, VIVS_PA_SYSTEM_MODE, 0x11);
etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_BIT(VIVS_PA_CONFIG_UNK22, 0));
etna_set_state(ctx, VIVS_SE_CONFIG, 0x0);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR);
/* Does this affect the RS? It appears not. */
etna_set_state(ctx, VIVS_GL_MULTI_SAMPLE_CONFIG,
ETNA_MASKED_INL(VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES, 4X) &
ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES, 0xf) &
ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12, 0x0) &
ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16, 0x0)
);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
/* Set up resolve to self */
etna_set_state(ctx, VIVS_TS_COLOR_CLEAR_VALUE, 0xff7f7f7f);
etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts->address); /* ADDR_B */
etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt->address); /* ADDR_A */
#if 0 /* don't care about depth, for now */
etna_set_state(ctx, VIVS_TS_DEPTH_CLEAR_VALUE, 0xffffffff);
etna_set_state(ctx, VIVS_TS_DEPTH_STATUS_BASE, z_ts->address); /* ADDR_D */
etna_set_state(ctx, VIVS_TS_DEPTH_SURFACE_BASE, z->address); /* ADDR_C */
#endif
etna_set_state(ctx, VIVS_TS_MEM_CONFIG,
VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR
/*VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR |
VIVS_TS_MEM_CONFIG_DEPTH_16BPP |
VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION*/);
etna_set_state(ctx, VIVS_RS_CONFIG,
VIVS_RS_CONFIG_SOURCE_FORMAT(pixelfmt) |
(tiled?VIVS_RS_CONFIG_SOURCE_TILED:0) |
VIVS_RS_CONFIG_DEST_FORMAT(pixelfmt) |
(tiled?VIVS_RS_CONFIG_DEST_TILED:0));
etna_set_state(ctx, VIVS_RS_SOURCE_STRIDE, stride);
etna_set_state(ctx, VIVS_RS_DEST_STRIDE, stride);
etna_set_state(ctx, VIVS_RS_DITHER(0), 0xffffffff);
etna_set_state(ctx, VIVS_RS_DITHER(1), 0xffffffff);
etna_set_state(ctx, VIVS_RS_CLEAR_CONTROL, VIVS_RS_CLEAR_CONTROL_MODE_DISABLED);
etna_set_state(ctx, VIVS_RS_EXTRA_CONFIG, 0); /* no AA, no endian switch */
etna_set_state(ctx, VIVS_RS_SOURCE_ADDR, rt->address); /* ADDR_A */
etna_set_state(ctx, VIVS_RS_DEST_ADDR, rt->address); /* ADDR_A */
etna_set_state(ctx, VIVS_RS_WINDOW_SIZE,
VIVS_RS_WINDOW_SIZE_HEIGHT(padded_height) |
VIVS_RS_WINDOW_SIZE_WIDTH(padded_width));
etna_set_state(ctx, VIVS_RS_KICKER, 0xbeebbeeb);
etna_set_state(ctx, VIVS_TS_FLUSH_CACHE, VIVS_TS_FLUSH_CACHE_FLUSH | VIVS_GL_FLUSH_CACHE_COLOR);
/* Clear part using normal (not fast) clear */
etna_set_state(ctx, VIVS_TS_MEM_CONFIG, 0);
etna_set_state_multi(ctx, VIVS_RS_DITHER(0), 2, (uint32_t[]){0xffffffff, 0xffffffff});
etna_set_state(ctx, VIVS_RS_WINDOW_SIZE,
VIVS_RS_WINDOW_SIZE_HEIGHT(0x100) |
VIVS_RS_WINDOW_SIZE_WIDTH(0x100));
etna_set_state(ctx, VIVS_RS_FILL_VALUE(0), 0xffff0000);
etna_set_state(ctx, VIVS_RS_FILL_VALUE(1), 0xff00ff00);
etna_set_state(ctx, VIVS_RS_FILL_VALUE(2), 0xff0000ff);
etna_set_state(ctx, VIVS_RS_FILL_VALUE(3), 0xffff00ff);
etna_set_state(ctx, VIVS_RS_SOURCE_ADDR, 0); /* fill disregards source anyway */
etna_set_state(ctx, VIVS_RS_DEST_ADDR, rt->address + 64*64*4); /* Offset one entire 64*64 tile. Interesting things happen if only a partial tile is offset. */
/* Pure FILL_VALUE(0) */
//etna_set_state(ctx, VIVS_RS_CLEAR_CONTROL, VIVS_RS_CLEAR_CONTROL_MODE_ENABLED1 | VIVS_RS_CLEAR_CONTROL_BITS(0xffff));
/* Vertical line pattern */
etna_set_state(ctx, VIVS_RS_CLEAR_CONTROL, VIVS_RS_CLEAR_CONTROL_MODE_ENABLED4 | VIVS_RS_CLEAR_CONTROL_BITS(0xffff));
/* Same as ENABLED2 */
//etna_set_state(ctx, VIVS_RS_CLEAR_CONTROL, VIVS_RS_CLEAR_CONTROL_MODE_ENABLED4_2 | VIVS_RS_CLEAR_CONTROL_BITS(0xffff));
etna_set_state(ctx, VIVS_RS_EXTRA_CONFIG, 0);
etna_set_state(ctx, VIVS_RS_KICKER,
0xbeebbeeb);
etna_finish(ctx);
#if 0
/* manually fill, to figure out tiling pattern */
for(int x=0; x<16384/4; ++x)
{
int a = (x & 0x3F) << 2;
int b = ((x >> 3) & 0x3F) << 2;
int c = ((x >> 6) & 0x3F) << 2;
((uint32_t*)(rt->logical + 16384*6))[x] = (a & 0xFF) | ((b & 0xFF) << 8) | ((c & 0xFF) << 16);
printf("%08x\n", (a & 0xFF) | ((b & 0xFF) << 8) | ((c & 0xFF) << 16));
}
#endif
/* Copy image to screen */
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_set_state(ctx, VIVS_TS_MEM_CONFIG, 0);
etna_set_state(ctx, VIVS_RS_CONFIG,
VIVS_RS_CONFIG_SOURCE_FORMAT(pixelfmt) |
(tiled?VIVS_RS_CONFIG_SOURCE_TILED:0) |
VIVS_RS_CONFIG_DEST_FORMAT(RS_FORMAT_X8R8G8B8) |
VIVS_RS_CONFIG_SWAP_RB);
etna_set_state(ctx, VIVS_RS_SOURCE_STRIDE, stride);
etna_set_state(ctx, VIVS_RS_DEST_STRIDE, fb.fb_fix.line_length);
etna_set_state(ctx, VIVS_RS_DITHER(0), 0xffffffff);
etna_set_state(ctx, VIVS_RS_DITHER(1), 0xffffffff);
etna_set_state(ctx, VIVS_RS_CLEAR_CONTROL, VIVS_RS_CLEAR_CONTROL_MODE_DISABLED);
etna_set_state(ctx, VIVS_RS_EXTRA_CONFIG,
0); /* no AA, no endian switch */
etna_set_state(ctx, VIVS_RS_SOURCE_ADDR, rt->address); /* ADDR_A */
etna_set_state(ctx, VIVS_RS_DEST_ADDR, fb.physical[backbuffer]); /* ADDR_J */
etna_set_state(ctx, VIVS_RS_WINDOW_SIZE,
VIVS_RS_WINDOW_SIZE_HEIGHT(height) |
VIVS_RS_WINDOW_SIZE_WIDTH(width));
etna_set_state(ctx, VIVS_RS_KICKER, 0xbeebbeeb);
etna_finish(ctx);
/* switch buffers */
fb_set_buffer(&fb, backbuffer);
backbuffer = 1-backbuffer;
}
#ifdef DUMP
bmp_dump32(fb.logical[1-backbuffer], width, height, false, "/mnt/sdcard/fb.bmp");
printf("Dump complete\n");
#endif
etna_free(ctx);
viv_close(conn);
return 0;
}
int main(int argc, char **argv)
{
int rv;
int width = 256;
int height = 256;
int padded_width, padded_height;
int backbuffer = 0;
struct fb_info fb;
rv = fb_open(0, &fb);
if(rv!=0)
{
exit(1);
}
width = fb.fb_var.xres;
height = fb.fb_var.yres;
padded_width = etna_align_up(width, 64);
padded_height = etna_align_up(height, 64);
printf("padded_width %i padded_height %i\n", padded_width, padded_height);
struct viv_conn *conn = 0;
rv = viv_open(VIV_HW_3D, &conn);
if(rv!=0)
{
fprintf(stderr, "Error opening device\n");
exit(1);
}
printf("Succesfully opened device\n");
bool supertiled = VIV_FEATURE(conn, chipMinorFeatures0,SUPER_TILED);
unsigned bits_per_tile = VIV_FEATURE(conn, chipMinorFeatures0,2BITPERTILE)?2:4;
printf("supertiled: %i bits per tile: %i\n", supertiled, bits_per_tile);
struct etna_vidmem *rt = 0; /* main render target */
struct etna_vidmem *rt_ts = 0; /* tile status for main render target */
struct etna_vidmem *z = 0; /* depth for main render target */
struct etna_vidmem *z_ts = 0; /* depth ts for main render target */
struct etna_vidmem *vtx = 0; /* vertex buffer */
struct etna_vidmem *aux_rt = 0; /* auxilary render target */
struct etna_vidmem *aux_rt_ts = 0; /* tile status for auxilary render target */
struct etna_vidmem *bmp = 0; /* bitmap */
size_t rt_size = padded_width * padded_height * 4;
size_t rt_ts_size = etna_align_up((padded_width * padded_height * 4)*bits_per_tile/0x80, 0x100);
size_t z_size = padded_width * padded_height * 2;
size_t z_ts_size = etna_align_up((padded_width * padded_height * 2)*bits_per_tile/0x80, 0x100);
size_t bmp_size = width * height * 4;
if(etna_vidmem_alloc_linear(conn, &rt, rt_size, gcvSURF_RENDER_TARGET, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(conn, &rt_ts, rt_ts_size, gcvSURF_TILE_STATUS, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(conn, &z, z_size, gcvSURF_DEPTH, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(conn, &z_ts, z_ts_size, gcvSURF_TILE_STATUS, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(conn, &vtx, VERTEX_BUFFER_SIZE, gcvSURF_VERTEX, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(conn, &aux_rt, 0x4000, gcvSURF_RENDER_TARGET, gcvPOOL_SYSTEM, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(conn, &aux_rt_ts, 0x80*bits_per_tile, gcvSURF_TILE_STATUS, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(conn, &bmp, bmp_size, gcvSURF_BITMAP, gcvPOOL_DEFAULT, true)!=ETNA_OK
)
{
fprintf(stderr, "Error allocating video memory\n");
exit(1);
}
/* Phew, now we got all the memory we need.
* Write interleaved attribute vertex stream.
* Unlike the GL example we only do this once, not every time glDrawArrays is called, the same would be accomplished
* from GL by using a vertex buffer object.
*/
for(int vert=0; vert<NUM_VERTICES; ++vert)
{
int src_idx = vert * COMPONENTS_PER_VERTEX;
int dest_idx = vert * COMPONENTS_PER_VERTEX * 3;
for(int comp=0; comp<COMPONENTS_PER_VERTEX; ++comp)
{
((float*)vtx->logical)[dest_idx+comp+0] = vVertices[src_idx + comp]; /* 0 */
((float*)vtx->logical)[dest_idx+comp+3] = vNormals[src_idx + comp]; /* 1 */
((float*)vtx->logical)[dest_idx+comp+6] = vColors[src_idx + comp]; /* 2 */
}
}
struct etna_ctx *ctx = 0;
if(etna_create(conn, &ctx) != ETNA_OK)
{
printf("Unable to create context\n");
exit(1);
}
/* XXX how important is the ordering? I suppose we could group states (except the flushes, kickers, semaphores etc)
* and simply submit them at once. Especially for consecutive states and masked stated this could be a big win
* in DMA command buffer size. */
for(int frame=0; frame<1000; ++frame)
{
if(frame % 50 == 0)
printf("*** FRAME %i ****\n", frame);
/* XXX part of this can be put outside the loop, but until we have usable context management
* this is safest.
*/
etna_set_state(ctx, VIVS_GL_VERTEX_ELEMENT_CONFIG, 0x1);
etna_set_state(ctx, VIVS_RA_CONTROL, 0x1);
etna_set_state(ctx, VIVS_PA_W_CLIP_LIMIT, 0x34000001);
etna_set_state(ctx, VIVS_PA_SYSTEM_MODE, 0x11);
etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_BIT(VIVS_PA_CONFIG_UNK22, 0));
etna_set_state(ctx, VIVS_SE_CONFIG, 0x0);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR);
etna_set_state(ctx, VIVS_PE_COLOR_FORMAT,
ETNA_MASKED_BIT(VIVS_PE_COLOR_FORMAT_OVERWRITE, 0));
etna_set_state(ctx, VIVS_PE_ALPHA_CONFIG,
ETNA_MASKED_BIT(VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_COLOR, 0) &
ETNA_MASKED_BIT(VIVS_PE_ALPHA_CONFIG_BLEND_SEPARATE_ALPHA, 0) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR, BLEND_FUNC_ONE) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA, BLEND_FUNC_ONE) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR, BLEND_FUNC_ZERO) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA, BLEND_FUNC_ZERO) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_EQ_COLOR, BLEND_EQ_ADD) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_EQ_ALPHA, BLEND_EQ_ADD));
etna_set_state(ctx, VIVS_PE_ALPHA_BLEND_COLOR,
VIVS_PE_ALPHA_BLEND_COLOR_B(0) |
VIVS_PE_ALPHA_BLEND_COLOR_G(0) |
VIVS_PE_ALPHA_BLEND_COLOR_R(0) |
VIVS_PE_ALPHA_BLEND_COLOR_A(0));
etna_set_state(ctx, VIVS_PE_ALPHA_OP, ETNA_MASKED_BIT(VIVS_PE_ALPHA_OP_ALPHA_TEST, 0));
etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_INL(VIVS_PA_CONFIG_CULL_FACE_MODE, OFF));
etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE, 0));
etna_set_state(ctx, VIVS_PE_STENCIL_CONFIG, ETNA_MASKED(VIVS_PE_STENCIL_CONFIG_REF_FRONT, 0) &
ETNA_MASKED(VIVS_PE_STENCIL_CONFIG_MASK_FRONT, 0xff) &
ETNA_MASKED(VIVS_PE_STENCIL_CONFIG_WRITE_MASK, 0xff) &
ETNA_MASKED_INL(VIVS_PE_STENCIL_CONFIG_MODE, DISABLED));
etna_set_state(ctx, VIVS_PE_STENCIL_OP, ETNA_MASKED(VIVS_PE_STENCIL_OP_FUNC_FRONT, COMPARE_FUNC_ALWAYS) &
ETNA_MASKED(VIVS_PE_STENCIL_OP_FUNC_BACK, COMPARE_FUNC_ALWAYS) &
ETNA_MASKED(VIVS_PE_STENCIL_OP_FAIL_FRONT, STENCIL_OP_KEEP) &
ETNA_MASKED(VIVS_PE_STENCIL_OP_FAIL_BACK, STENCIL_OP_KEEP) &
ETNA_MASKED(VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT, STENCIL_OP_KEEP) &
ETNA_MASKED(VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK, STENCIL_OP_KEEP) &
ETNA_MASKED(VIVS_PE_STENCIL_OP_PASS_FRONT, STENCIL_OP_KEEP) &
ETNA_MASKED(VIVS_PE_STENCIL_OP_PASS_BACK, STENCIL_OP_KEEP));
etna_set_state(ctx, VIVS_PE_COLOR_FORMAT, ETNA_MASKED(VIVS_PE_COLOR_FORMAT_COMPONENTS, 0xf));
etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_EARLY_Z, 0));
etna_set_state(ctx, VIVS_SE_DEPTH_SCALE, 0x0);
etna_set_state(ctx, VIVS_SE_DEPTH_BIAS, 0x0);
etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_INL(VIVS_PA_CONFIG_FILL_MODE, SOLID));
etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_INL(VIVS_PA_CONFIG_SHADE_MODEL, SMOOTH));
etna_set_state(ctx, VIVS_PE_COLOR_FORMAT,
ETNA_MASKED(VIVS_PE_COLOR_FORMAT_FORMAT, RS_FORMAT_X8R8G8B8) &
ETNA_MASKED_BIT(VIVS_PE_COLOR_FORMAT_SUPER_TILED, supertiled));
etna_set_state(ctx, VIVS_PE_COLOR_ADDR, rt->address); /* ADDR_A */
etna_set_state(ctx, VIVS_PE_COLOR_STRIDE, padded_width * 4);
etna_set_state(ctx, VIVS_GL_MULTI_SAMPLE_CONFIG,
ETNA_MASKED_INL(VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES, NONE) &
ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES, 0xf) &
ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12, 0x0) &
ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16, 0x0)
);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR);
etna_set_state(ctx, VIVS_PE_COLOR_FORMAT, ETNA_MASKED_BIT(VIVS_PE_COLOR_FORMAT_OVERWRITE, 1));
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR);
etna_set_state(ctx, VIVS_TS_COLOR_CLEAR_VALUE, 0);
etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts->address); /* ADDR_B */
etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt->address); /* ADDR_A */
etna_set_state(ctx, VIVS_TS_MEM_CONFIG, VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR);
etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG,
ETNA_MASKED_INL(VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT, D16) &
ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_SUPER_TILED, supertiled)
);
etna_set_state(ctx, VIVS_PE_DEPTH_ADDR, z->address); /* ADDR_C */
etna_set_state(ctx, VIVS_PE_DEPTH_STRIDE, padded_width * 2);
etna_set_state(ctx, VIVS_PE_HDEPTH_CONTROL, VIVS_PE_HDEPTH_CONTROL_FORMAT_DISABLED);
etna_set_state_f32(ctx, VIVS_PE_DEPTH_NORMALIZE, 65535.0);
etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_EARLY_Z, 0));
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_DEPTH);
etna_set_state(ctx, VIVS_TS_DEPTH_CLEAR_VALUE, 0xffffffff);
etna_set_state(ctx, VIVS_TS_DEPTH_STATUS_BASE, z_ts->address); /* ADDR_D */
etna_set_state(ctx, VIVS_TS_DEPTH_SURFACE_BASE, z->address); /* ADDR_C */
etna_set_state(ctx, VIVS_TS_MEM_CONFIG,
VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR |
VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR |
VIVS_TS_MEM_CONFIG_DEPTH_16BPP |
VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION);
etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_EARLY_Z, 1)); /* flip-flopping once again */
/* Warm up RS on aux render target */
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_warm_up_rs(ctx, aux_rt->address, aux_rt_ts->address);
etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts->address); /* ADDR_B */
etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt->address); /* ADDR_A */
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_warm_up_rs(ctx, aux_rt->address, aux_rt_ts->address);
etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts->address); /* ADDR_B */
etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt->address); /* ADDR_A */
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_warm_up_rs(ctx, aux_rt->address, aux_rt_ts->address);
etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts->address); /* ADDR_B */
etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt->address); /* ADDR_A */
etna_stall(ctx, SYNC_RECIPIENT_RA, SYNC_RECIPIENT_PE);
/* Set up the resolve to clear tile status for main render target
* Regard the TS as an image of width 16 with 4 bytes per pixel (64 bytes per row)
* XXX need to clear the depth ts too.
* */
etna_set_state(ctx, VIVS_RS_CONFIG,
(RS_FORMAT_A8R8G8B8 << VIVS_RS_CONFIG_SOURCE_FORMAT__SHIFT) |
(RS_FORMAT_A8R8G8B8 << VIVS_RS_CONFIG_DEST_FORMAT__SHIFT)
);
etna_set_state_multi(ctx, VIVS_RS_DITHER(0), 2, (uint32_t[]){0xffffffff, 0xffffffff});
etna_set_state(ctx, VIVS_RS_DEST_ADDR, rt_ts->address); /* ADDR_B */
etna_set_state(ctx, VIVS_RS_DEST_STRIDE, 0x40);
etna_set_state(ctx, VIVS_RS_WINDOW_SIZE,
((rt_ts_size/0x40) << VIVS_RS_WINDOW_SIZE_HEIGHT__SHIFT) |
(16 << VIVS_RS_WINDOW_SIZE_WIDTH__SHIFT));
etna_set_state(ctx, VIVS_RS_FILL_VALUE(0), (bits_per_tile==4)?0x11111111:0x55555555);
etna_set_state(ctx, VIVS_RS_CLEAR_CONTROL,
VIVS_RS_CLEAR_CONTROL_MODE_ENABLED1 |
(0xffff << VIVS_RS_CLEAR_CONTROL_BITS__SHIFT));
etna_set_state(ctx, VIVS_RS_EXTRA_CONFIG,
0); /* no AA, no endian switch */
etna_set_state(ctx, VIVS_RS_KICKER,
0xbeebbeeb);
/** Done */
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR);
etna_set_state(ctx, VIVS_TS_COLOR_CLEAR_VALUE, 0xff7f7f7f);
etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts->address); /* ADDR_B */
etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt->address); /* ADDR_A */
etna_set_state(ctx, VIVS_TS_MEM_CONFIG,
VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR |
VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR |
VIVS_TS_MEM_CONFIG_DEPTH_16BPP |
VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION);
etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_INL(VIVS_PA_CONFIG_CULL_FACE_MODE, CCW));
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE, 0));
etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED_INL(VIVS_PE_DEPTH_CONFIG_DEPTH_MODE, NONE));
etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE, 0));
etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED(VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC, COMPARE_FUNC_ALWAYS));
etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED_INL(VIVS_PE_DEPTH_CONFIG_DEPTH_MODE, Z));
etna_set_state_f32(ctx, VIVS_PE_DEPTH_NEAR, 0.0);
etna_set_state_f32(ctx, VIVS_PE_DEPTH_FAR, 1.0);
etna_set_state_f32(ctx, VIVS_PE_DEPTH_NORMALIZE, 65535.0);
/* set up primitive assembly */
etna_set_state_f32(ctx, VIVS_PA_VIEWPORT_OFFSET_Z, 0.0);
etna_set_state_f32(ctx, VIVS_PA_VIEWPORT_SCALE_Z, 1.0);
etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_ONLY_DEPTH, 0));
etna_set_state_fixp(ctx, VIVS_PA_VIEWPORT_OFFSET_X, width << 15);
etna_set_state_fixp(ctx, VIVS_PA_VIEWPORT_OFFSET_Y, height << 15);
etna_set_state_fixp(ctx, VIVS_PA_VIEWPORT_SCALE_X, width << 15);
etna_set_state_fixp(ctx, VIVS_PA_VIEWPORT_SCALE_Y, height << 15);
etna_set_state_fixp(ctx, VIVS_SE_SCISSOR_LEFT, 0);
etna_set_state_fixp(ctx, VIVS_SE_SCISSOR_TOP, 0);
//etna_set_state_fixp(ctx, VIVS_SE_SCISSOR_RIGHT, (width << 16) | 5);
//etna_set_state_fixp(ctx, VIVS_SE_SCISSOR_BOTTOM, (height << 16) | 5);
/// XXX really important; setting SCISSOR to |5 as above causes crashes for higher resolutions such as
/// 1920x1080. I don't know why.
etna_set_state_fixp(ctx, VIVS_SE_SCISSOR_RIGHT, (width << 16)-1);
etna_set_state_fixp(ctx, VIVS_SE_SCISSOR_BOTTOM, (height << 16)-1);
/* shader setup */
etna_set_state(ctx, VIVS_VS_END_PC, vs_size/16);
etna_set_state_multi(ctx, VIVS_VS_INPUT_COUNT, 3, (uint32_t[]){
/* VIVS_VS_INPUT_COUNT */ (1<<8) | 3,
/* VIVS_VS_TEMP_REGISTER_CONTROL */ 6 << VIVS_VS_TEMP_REGISTER_CONTROL_NUM_TEMPS__SHIFT,
/* VIVS_VS_OUTPUT(0) */ 4});
etna_set_state(ctx, VIVS_VS_START_PC, 0x0);
etna_set_state_f32(ctx, VIVS_VS_UNIFORMS(45), 0.5); /* u11.y */
etna_set_state_f32(ctx, VIVS_VS_UNIFORMS(44), 1.0); /* u11.x */
etna_set_state_f32(ctx, VIVS_VS_UNIFORMS(27), 0.0); /* u6.w */
etna_set_state_f32(ctx, VIVS_VS_UNIFORMS(23), 20.0); /* u5.w */
etna_set_state_f32(ctx, VIVS_VS_UNIFORMS(19), 2.0); /* u4.w */
/* Now load the shader itself */
etna_set_state_multi(ctx, VIVS_VS_INST_MEM(0), vs_size/4, vs);
etna_set_state(ctx, VIVS_RA_CONTROL, 0x1);
etna_set_state_multi(ctx, VIVS_PS_END_PC, 2, (uint32_t[]){
/* VIVS_PS_END_PC */ ps_size/16,
/* VIVS_PS_OUTPUT_REG */ 0x1});
etna_set_state(ctx, VIVS_PS_START_PC, 0x0);
etna_set_state(ctx, VIVS_PA_SHADER_ATTRIBUTES(0), 0x200);
etna_set_state(ctx, VIVS_GL_VARYING_NUM_COMPONENTS, /* one varying, with four components */
(4 << VIVS_GL_VARYING_NUM_COMPONENTS_VAR0__SHIFT)
);
etna_set_state_multi(ctx, VIVS_GL_VARYING_COMPONENT_USE(0), 2, (uint32_t[]){ /* one varying, with four components */
(VARYING_COMPONENT_USE_USED << VIVS_GL_VARYING_COMPONENT_USE_COMP0__SHIFT) |
(VARYING_COMPONENT_USE_USED << VIVS_GL_VARYING_COMPONENT_USE_COMP1__SHIFT) |
(VARYING_COMPONENT_USE_USED << VIVS_GL_VARYING_COMPONENT_USE_COMP2__SHIFT) |
(VARYING_COMPONENT_USE_USED << VIVS_GL_VARYING_COMPONENT_USE_COMP3__SHIFT)
, 0
});
etna_set_state_multi(ctx, VIVS_PS_INST_MEM(0), ps_size/4, ps);
etna_set_state(ctx, VIVS_PS_INPUT_COUNT, (31<<8)|2);
etna_set_state(ctx, VIVS_PS_TEMP_REGISTER_CONTROL,
(2 << VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS__SHIFT));
etna_set_state(ctx, VIVS_PS_CONTROL,
VIVS_PS_CONTROL_UNK1
);
etna_set_state(ctx, VIVS_PA_ATTRIBUTE_ELEMENT_COUNT, 0x100);
etna_set_state(ctx, VIVS_GL_VARYING_TOTAL_COMPONENTS, /* one varying, with four components */
VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM(4)
);
etna_set_state(ctx, VIVS_VS_LOAD_BALANCING, 0xf3f0582);
etna_set_state(ctx, VIVS_VS_OUTPUT_COUNT, 2);
etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_BIT(VIVS_PA_CONFIG_POINT_SIZE_ENABLE, 0));
/* Compute transform matrices in the same way as cube egl demo */
ESMatrix modelview;
esMatrixLoadIdentity(&modelview);
esTranslate(&modelview, 0.0f, 0.0f, -8.0f);
esRotate(&modelview, 45.0f, 1.0f, 0.0f, 0.0f);
esRotate(&modelview, 45.0f, 0.0f, 1.0f, 0.0f);
esRotate(&modelview, frame*0.5f, 0.0f, 0.0f, 1.0f);
GLfloat aspect = (GLfloat)(height) / (GLfloat)(width);
ESMatrix projection;
esMatrixLoadIdentity(&projection);
esFrustum(&projection, -2.8f, +2.8f, -2.8f * aspect, +2.8f * aspect, 6.0f, 10.0f);
ESMatrix modelviewprojection;
esMatrixLoadIdentity(&modelviewprojection);
esMatrixMultiply(&modelviewprojection, &modelview, &projection);
ESMatrix inverse, normal; /* compute inverse transpose normal transformation matrix */
esMatrixInverse3x3(&inverse, &modelview);
esMatrixTranspose(&normal, &inverse);
etna_set_state_multi(ctx, VIVS_VS_UNIFORMS(0), 16, (uint32_t*)&modelviewprojection.m[0][0]);
etna_set_state_multi(ctx, VIVS_VS_UNIFORMS(16), 3, (uint32_t*)&normal.m[0][0]); /* u4.xyz */
etna_set_state_multi(ctx, VIVS_VS_UNIFORMS(20), 3, (uint32_t*)&normal.m[1][0]); /* u5.xyz */
etna_set_state_multi(ctx, VIVS_VS_UNIFORMS(24), 3, (uint32_t*)&normal.m[2][0]); /* u6.xyz */
etna_set_state_multi(ctx, VIVS_VS_UNIFORMS(28), 16, (uint32_t*)&modelview.m[0][0]);
etna_set_state(ctx, VIVS_FE_VERTEX_STREAM_BASE_ADDR, vtx->address); /* ADDR_E */
etna_set_state(ctx, VIVS_FE_VERTEX_STREAM_CONTROL,
0x24 << VIVS_FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__SHIFT);
etna_set_state(ctx, VIVS_FE_VERTEX_ELEMENT_CONFIG(0),
VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_FLOAT |
(ENDIAN_MODE_NO_SWAP << VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT) |
(0 << VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM__SHIFT) |
(3 <<VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM__SHIFT) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_OFF |
(0x0 << VIVS_FE_VERTEX_ELEMENT_CONFIG_START__SHIFT) |
(0xc << VIVS_FE_VERTEX_ELEMENT_CONFIG_END__SHIFT));
etna_set_state(ctx, VIVS_FE_VERTEX_ELEMENT_CONFIG(1),
VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_FLOAT |
(ENDIAN_MODE_NO_SWAP << VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT) |
(0 << VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM__SHIFT) |
(3 <<VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM__SHIFT) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_OFF |
(0xc << VIVS_FE_VERTEX_ELEMENT_CONFIG_START__SHIFT) |
(0x18 << VIVS_FE_VERTEX_ELEMENT_CONFIG_END__SHIFT));
etna_set_state(ctx, VIVS_FE_VERTEX_ELEMENT_CONFIG(2),
VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_FLOAT |
(ENDIAN_MODE_NO_SWAP << VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_NONCONSECUTIVE |
(0 << VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM__SHIFT) |
(3 <<VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM__SHIFT) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_OFF |
(0x18 << VIVS_FE_VERTEX_ELEMENT_CONFIG_START__SHIFT) |
(0x24 << VIVS_FE_VERTEX_ELEMENT_CONFIG_END__SHIFT));
etna_set_state(ctx, VIVS_VS_INPUT(0), 0x20100);
etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_BIT(VIVS_PA_CONFIG_POINT_SPRITE_ENABLE, 0));
for(int prim=0; prim<6; ++prim)
{
etna_draw_primitives(ctx, PRIMITIVE_TYPE_TRIANGLE_STRIP, prim*4, 2);
}
//etna_finish(ctx);
//exit(1);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_flush(ctx);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_set_state(ctx, VIVS_RS_CONFIG,
VIVS_RS_CONFIG_SOURCE_FORMAT(RS_FORMAT_X8R8G8B8) |
VIVS_RS_CONFIG_SOURCE_TILED |
VIVS_RS_CONFIG_DEST_FORMAT(RS_FORMAT_X8R8G8B8) |
VIVS_RS_CONFIG_DEST_TILED);
etna_set_state(ctx, VIVS_RS_SOURCE_STRIDE, (padded_width * 4 * 4) | (supertiled?VIVS_RS_SOURCE_STRIDE_TILING:0));
etna_set_state(ctx, VIVS_RS_DEST_STRIDE, (padded_width * 4 * 4) | (supertiled?VIVS_RS_DEST_STRIDE_TILING:0));
etna_set_state(ctx, VIVS_RS_DITHER(0), 0xffffffff);
etna_set_state(ctx, VIVS_RS_DITHER(1), 0xffffffff);
etna_set_state(ctx, VIVS_RS_CLEAR_CONTROL, VIVS_RS_CLEAR_CONTROL_MODE_DISABLED);
etna_set_state(ctx, VIVS_RS_EXTRA_CONFIG, 0); /* no AA, no endian switch */
etna_set_state(ctx, VIVS_RS_SOURCE_ADDR, rt->address); /* ADDR_A */
etna_set_state(ctx, VIVS_RS_DEST_ADDR, rt->address); /* ADDR_A */
etna_set_state(ctx, VIVS_RS_WINDOW_SIZE,
VIVS_RS_WINDOW_SIZE_HEIGHT(padded_height) |
VIVS_RS_WINDOW_SIZE_WIDTH(padded_width));
etna_set_state(ctx, VIVS_RS_KICKER, 0xbeebbeeb);
/* Submit second command buffer */
etna_flush(ctx);
etna_warm_up_rs(ctx, aux_rt->address, aux_rt_ts->address);
etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts->address); /* ADDR_B */
etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt->address); /* ADDR_A */
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR);
etna_set_state(ctx, VIVS_TS_MEM_CONFIG,
VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR |
VIVS_TS_MEM_CONFIG_DEPTH_16BPP |
VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR);
etna_set_state(ctx, VIVS_PE_COLOR_FORMAT,
ETNA_MASKED_BIT(VIVS_PE_COLOR_FORMAT_OVERWRITE, 0));
/* Submit third command buffer, wait for pixel engine to finish */
etna_finish(ctx);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_set_state(ctx, VIVS_RS_CONFIG,
VIVS_RS_CONFIG_SOURCE_FORMAT(RS_FORMAT_X8R8G8B8) |
VIVS_RS_CONFIG_SOURCE_TILED |
VIVS_RS_CONFIG_DEST_FORMAT(RS_FORMAT_X8R8G8B8) /*|
VIVS_RS_CONFIG_SWAP_RB*/);
etna_set_state(ctx, VIVS_RS_SOURCE_STRIDE, (padded_width * 4 * 4) | (supertiled?VIVS_RS_SOURCE_STRIDE_TILING:0));
etna_set_state(ctx, VIVS_RS_DEST_STRIDE, fb.fb_fix.line_length);
etna_set_state(ctx, VIVS_RS_DITHER(0), 0xffffffff);
etna_set_state(ctx, VIVS_RS_DITHER(1), 0xffffffff);
etna_set_state(ctx, VIVS_RS_CLEAR_CONTROL, VIVS_RS_CLEAR_CONTROL_MODE_DISABLED);
etna_set_state(ctx, VIVS_RS_EXTRA_CONFIG,
0); /* no AA, no endian switch */
etna_set_state(ctx, VIVS_RS_SOURCE_ADDR, rt->address); /* ADDR_A */
etna_set_state(ctx, VIVS_RS_DEST_ADDR, fb.physical[backbuffer]); /* ADDR_J */
etna_set_state(ctx, VIVS_RS_WINDOW_SIZE,
VIVS_RS_WINDOW_SIZE_HEIGHT(height) |
VIVS_RS_WINDOW_SIZE_WIDTH(width));
etna_set_state(ctx, VIVS_RS_KICKER, 0xbeebbeeb);
etna_finish(ctx);
/* switch buffers */
fb_set_buffer(&fb, backbuffer);
backbuffer = 1-backbuffer;
}
/* Unlock video memory */
if(etna_vidmem_unlock(conn, bmp) != 0)
{
fprintf(stderr, "Cannot unlock vidmem\n");
exit(1);
}
etna_free(ctx);
viv_close(conn);
return 0;
}