static int
alpine_get_serdes_base(u_long *pbase, u_long *psize)
{
phandle_t node;
u_long base = 0;
u_long size = 0;
if (pbase == NULL || psize == NULL)
return (EINVAL);
if ((node = OF_finddevice("/")) == -1)
return (EFAULT);
if ((node =
ofw_bus_find_compatible(node, "annapurna-labs,al-serdes")) == 0)
return (EFAULT);
if (fdt_regsize(node, &base, &size))
return (EFAULT);
*pbase = base;
*psize = size;
return (0);
}
static void
pci_from_fdt_node(device_t dev_par, phandle_t dt_node, char *name,
char *type, char *compat)
{
u_long reg_base, reg_size;
phandle_t dt_child;
/*
* Retrieve 'reg' property.
*/
if (fdt_regsize(dt_node, ®_base, ®_size) != 0) {
device_printf(dev_par, "could not retrieve 'reg' prop\n");
return;
}
/*
* Walk the PCI node and instantiate newbus devices representing
* logical resources (bridges / ports).
*/
for (dt_child = OF_child(dt_node); dt_child != 0;
dt_child = OF_peer(dt_child)) {
if (!(fdt_is_enabled(dt_child)))
continue;
newbus_pci_create(dev_par, dt_child, reg_base, reg_size);
}
}
int
mv_msi_data(int irq, uint64_t *addr, uint32_t *data)
{
u_long phys, base, size;
phandle_t node;
int error;
node = ofw_bus_get_node(mv_mpic_sc->sc_dev);
/* Get physical addres of register space */
error = fdt_get_range(OF_parent(node), 0, &phys, &size);
if (error) {
printf("%s: Cannot get register physical address, err:%d",
__func__, error);
return (error);
}
/* Get offset of MPIC register space */
error = fdt_regsize(node, &base, &size);
if (error) {
printf("%s: Cannot get MPIC register offset, err:%d",
__func__, error);
return (error);
}
*addr = phys + base + MPIC_SOFT_INT;
*data = MPIC_SOFT_INT_DRBL1 | irq;
return (0);
}
int
rk30_gpios_prop_handle(phandle_t ctrl, pcell_t *gpios, int len)
{
struct rk30_gpio_softc *sc;
pcell_t gpio_cells;
int inc, t, tuples, tuple_size;
int dir, flags, pin, i;
u_long gpio_ctrl, size;
sc = rk30_gpio_sc;
if (sc == NULL)
return ENXIO;
if (OF_getprop(ctrl, "#gpio-cells", &gpio_cells, sizeof(pcell_t)) < 0)
return (ENXIO);
gpio_cells = fdt32_to_cpu(gpio_cells);
if (gpio_cells != 2)
return (ENXIO);
tuple_size = gpio_cells * sizeof(pcell_t) + sizeof(phandle_t);
tuples = len / tuple_size;
if (fdt_regsize(ctrl, &gpio_ctrl, &size))
return (ENXIO);
/*
* Skip controller reference, since controller's phandle is given
* explicitly (in a function argument).
*/
inc = sizeof(ihandle_t) / sizeof(pcell_t);
gpios += inc;
for (t = 0; t < tuples; t++) {
pin = fdt32_to_cpu(gpios[0]);
dir = fdt32_to_cpu(gpios[1]);
flags = fdt32_to_cpu(gpios[2]);
for (i = 0; i < sc->sc_gpio_npins; i++) {
if (sc->sc_gpio_pins[i].gp_pin == pin)
break;
}
if (i >= sc->sc_gpio_npins)
return (EINVAL);
rk30_gpio_pin_configure(sc, &sc->sc_gpio_pins[i], flags);
if (dir == 1) {
/* Input. */
rk30_gpio_pin_set(sc->sc_dev, pin, RK30_GPIO_INPUT);
} else {
/* Output. */
rk30_gpio_pin_set(sc->sc_dev, pin, RK30_GPIO_OUTPUT);
}
gpios += gpio_cells + inc;
}
return (0);
}
static int
alloc_resource_for_node(phandle_t node, struct resource *res, u_long *size)
{
int err;
u_long pbase, psize;
u_long start;
if ((err = fdt_get_range(OF_parent(node), 0, &pbase, &psize)) != 0 ||
(err = fdt_regsize(node, &start, size)) != 0)
return (err);
start += pbase;
memset(res, 0, sizeof(*res));
res->r_bustag = fdtbus_bs_tag;
err = bus_space_map(res->r_bustag, start, *size, 0, &res->r_bushandle);
return (err);
}
static void
fsl_ocotp_devmap(void)
{
phandle_t child, root;
u_long base, size;
if ((root = OF_finddevice("/")) == 0)
goto fatal;
if ((child = fdt_depth_search_compatible(root, "fsl,imx6q-ocotp", 0)) == 0)
goto fatal;
if (fdt_regsize(child, &base, &size) != 0)
goto fatal;
ocotp_size = (vm_size_t)size;
if ((ocotp_regs = pmap_mapdev((vm_offset_t)base, ocotp_size)) == NULL)
goto fatal;
return;
fatal:
panic("cannot find/map the ocotp registers");
}
int
flash_fill_slices(device_t dev, struct flash_slice *slices, int *slices_num)
{
char *slice_name;
phandle_t dt_node, dt_child;
u_long base, size;
int i;
ssize_t name_len;
/*
* We assume the caller provides buffer for FLASH_SLICES_MAX_NUM
* flash_slice structures.
*/
if (slices == NULL) {
*slices_num = 0;
return (ENOMEM);
}
dt_node = ofw_bus_get_node(dev);
for (dt_child = OF_child(dt_node), i = 0; dt_child != 0;
dt_child = OF_peer(dt_child)) {
if (i == FLASH_SLICES_MAX_NUM) {
debugf("not enough buffer for slice i=%d\n", i);
break;
}
/*
* Retrieve start and size of the slice.
*/
if (fdt_regsize(dt_child, &base, &size) != 0) {
debugf("error during processing reg property, i=%d\n",
i);
continue;
}
if (size == 0) {
debugf("slice i=%d with no size\n", i);
continue;
}
/*
* Retrieve label.
*/
name_len = OF_getprop_alloc(dt_child, "label", sizeof(char),
(void **)&slice_name);
if (name_len <= 0) {
/* Use node name if no label defined */
name_len = OF_getprop_alloc(dt_child, "name", sizeof(char),
(void **)&slice_name);
if (name_len <= 0) {
debugf("slice i=%d with no name\n", i);
slice_name = NULL;
}
}
/*
* Fill slice entry data.
*/
slices[i].base = base;
slices[i].size = size;
slices[i].label = slice_name;
i++;
}
*slices_num = i;
return (0);
}
int
uart_cpu_getdev(int devtype, struct uart_devinfo *di)
{
char buf[64];
struct uart_class *class;
phandle_t node, chosen;
pcell_t shift, br, rclk;
u_long start, size;
int err;
uart_bus_space_mem = fdtbus_bs_tag;
uart_bus_space_io = NULL;
/* Allow overriding the FDT uning the environment. */
class = &uart_ns8250_class;
err = uart_getenv(devtype, di, class);
if (!err)
return (0);
if (devtype != UART_DEV_CONSOLE)
return (ENXIO);
/*
* Retrieve /chosen/std{in,out}.
*/
if ((chosen = OF_finddevice("/chosen")) == 0)
return (ENXIO);
if (OF_getprop(chosen, "stdin", buf, sizeof(buf)) <= 0)
return (ENXIO);
if ((node = OF_finddevice(buf)) == 0)
return (ENXIO);
if (OF_getprop(chosen, "stdout", buf, sizeof(buf)) <= 0)
return (ENXIO);
if (OF_finddevice(buf) != node)
/* Only stdin == stdout is supported. */
return (ENXIO);
/*
* Retrieve serial attributes.
*/
uart_fdt_get_shift(node, &shift);
if (OF_getprop(node, "current-speed", &br, sizeof(br)) <= 0)
br = 0;
br = fdt32_to_cpu(br);
if ((err = uart_fdt_get_clock(node, &rclk)) != 0)
return (err);
/*
* Finalize configuration.
*/
class = &uart_quicc_class;
if (fdt_is_compatible(node, "ns16550"))
class = &uart_ns8250_class;
di->bas.chan = 0;
di->bas.regshft = (u_int)shift;
di->baudrate = 0;
di->bas.rclk = (u_int)rclk;
di->ops = uart_getops(class);
di->databits = 8;
di->stopbits = 1;
di->parity = UART_PARITY_NONE;
di->bas.bst = uart_bus_space_mem;
err = fdt_regsize(node, &start, &size);
if (err)
return (ENXIO);
start += fdt_immr_va;
return (bus_space_map(di->bas.bst, start, size, 0, &di->bas.bsh));
}
