static void powernv_populate_ipmi_bt(ISADevice *d, void *fdt, int lpc_off)
{
const char compatible[] = "bt\0ipmi-bt";
uint32_t io_base;
uint32_t io_regs[] = {
cpu_to_be32(1),
0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */
cpu_to_be32(3)
};
uint32_t irq;
char *name;
int node;
io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal);
io_regs[1] = cpu_to_be32(io_base);
irq = object_property_get_int(OBJECT(d), "irq", &error_fatal);
name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
node = fdt_add_subnode(fdt, lpc_off, name);
_FDT(node);
g_free(name);
_FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
_FDT((fdt_setprop(fdt, node, "compatible", compatible,
sizeof(compatible))));
/* Mark it as reserved to avoid Linux trying to claim it */
_FDT((fdt_setprop_string(fdt, node, "status", "reserved")));
_FDT((fdt_setprop_cell(fdt, node, "interrupts", irq)));
_FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
fdt_get_phandle(fdt, lpc_off))));
}
static void powernv_populate_serial(ISADevice *d, void *fdt, int lpc_off)
{
const char compatible[] = "ns16550\0pnpPNP,501";
uint32_t io_base = d->ioport_id;
uint32_t io_regs[] = {
cpu_to_be32(1),
cpu_to_be32(io_base),
cpu_to_be32(8)
};
char *name;
int node;
name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
node = fdt_add_subnode(fdt, lpc_off, name);
_FDT(node);
g_free(name);
_FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
_FDT((fdt_setprop(fdt, node, "compatible", compatible,
sizeof(compatible))));
_FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200)));
_FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200)));
_FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0])));
_FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
fdt_get_phandle(fdt, lpc_off))));
/* This is needed by Linux */
_FDT((fdt_setprop_string(fdt, node, "device_type", "serial")));
}
static int get_cpus_node(void *fdt)
{
int cpus_offset = fdt_path_offset(fdt, "/cpus");
if (cpus_offset < 0) {
cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
if (cpus_offset) {
_FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
_FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
}
}
_FDT(cpus_offset);
return cpus_offset;
}
static int spapr_vlan_devnode(VIOsPAPRDevice *dev, void *fdt, int node_off)
{
VIOsPAPRVLANDevice *vdev = (VIOsPAPRVLANDevice *)dev;
uint8_t padded_mac[8] = {0, 0};
int ret;
/* Some old phyp versions give the mac address in an 8-byte
* property. The kernel driver has an insane workaround for this;
* rather than doing the obvious thing and checking the property
* length, it checks whether the first byte has 0b10 in the low
* bits. If a correct 6-byte property has a different first byte
* the kernel will get the wrong mac address, overrunning its
* buffer in the process (read only, thank goodness).
*
* Here we workaround the kernel workaround by always supplying an
* 8-byte property, with the mac address in the last six bytes */
memcpy(&padded_mac[2], &vdev->nicconf.macaddr, ETH_ALEN);
ret = fdt_setprop(fdt, node_off, "local-mac-address",
padded_mac, sizeof(padded_mac));
if (ret < 0) {
return ret;
}
ret = fdt_setprop_cell(fdt, node_off, "ibm,mac-address-filters", 0);
if (ret < 0) {
return ret;
}
return 0;
}
void fsl_sgmii_riser_fdt_fixup(void *fdt)
{
struct eth_device *dev;
int node;
int i = -1;
int etsec_num = 0;
node = fdt_path_offset(fdt, "/aliases");
if (node < 0)
return;
while ((dev = eth_get_dev_by_index(++i)) != NULL) {
struct tsec_private *priv;
int enet_node;
char enet[16];
const u32 *phyh;
int phynode;
const char *model;
const char *path;
if (!strstr(dev->name, "eTSEC"))
continue;
sprintf(enet, "ethernet%d", etsec_num++);
path = fdt_getprop(fdt, node, enet, NULL);
if (!path) {
debug("No alias for %s\n", enet);
continue;
}
enet_node = fdt_path_offset(fdt, path);
if (enet_node < 0)
continue;
model = fdt_getprop(fdt, enet_node, "model", NULL);
/*
* We only want to do this to eTSECs. On some platforms
* there are more than one type of gianfar-style ethernet
* controller, and as we are creating an implicit connection
* between ethernet nodes and eTSEC devices, it is best to
* make the connection use as much explicit information
* as exists.
*/
if (!strstr(model, "TSEC"))
continue;
phyh = fdt_getprop(fdt, enet_node, "phy-handle", NULL);
if (!phyh)
continue;
phynode = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*phyh));
priv = dev->priv;
if (priv->flags & TSEC_SGMII)
fdt_setprop_cell(fdt, phynode, "reg", priv->phyaddr);
}
}
static int setprop_cell(void *fdt, const char *node_path,
const char *property, uint32_t val)
{
int offset = node_offset(fdt, node_path);
if (offset < 0)
return offset;
return fdt_setprop_cell(fdt, offset, property, val);
}
void fdt_fixup_dmamem(void *fdt)
{
/*
* By default assume param values specified in U-Boot config
*/
u32 mem_adr = CONFIG_DMAMEM_BASE;
u32 mem_sz = CONFIG_DMAMEM_SZ_ALL;
u32 fb_sz = CONFIG_DMAMEM_SZ_FB;
const u32 *val;
int node;
node = fdt_path_offset(fdt, "/dmamem");
if (node < 0) {
/*
* The device-tree file does not include 'dmamem' node.
* Create it, and fill with U-Boot params
*/
node = fdt_add_subnode(fdt, 0, "dmamem");
if (node < 0)
goto out;
fdt_setprop_string(fdt, node, "compatible", "dmamem");
fdt_setprop_cell(fdt, node, "base-addr", mem_adr);
fdt_setprop_cell(fdt, node, "full-size", mem_sz);
fdt_setprop_cell(fdt, node, "fb-size", fb_sz);
goto out;
}
/*
* Get params from device-tree
*/
val = fdt_getprop(fdt, node, "base-addr", NULL);
if (val)
mem_adr = fdt32_to_cpu(*val);
val = fdt_getprop(fdt, node, "full-size", NULL);
if (val)
mem_sz = fdt32_to_cpu(*val);
out:
/*
* Configure the dmamem area if it's not empty
*/
if (mem_sz)
dmamem_init(mem_adr, mem_sz);
}
int main(int argc, char *argv[])
{
void *fdt;
int err;
int offset, s1, s2;
test_init(argc, argv);
fdt = xmalloc(SPACE);
/* First create empty tree with SW */
CHECK(fdt_create(fdt, SPACE));
CHECK(fdt_finish_reservemap(fdt));
CHECK(fdt_begin_node(fdt, ""));
CHECK(fdt_end_node(fdt));
CHECK(fdt_finish(fdt));
verbose_printf("Built empty tree, totalsize = %d\n",
fdt_totalsize(fdt));
CHECK(fdt_open_into(fdt, fdt, SPACE));
CHECK(fdt_add_mem_rsv(fdt, TEST_ADDR_1, TEST_SIZE_1));
CHECK(fdt_add_mem_rsv(fdt, TEST_ADDR_2, TEST_SIZE_2));
CHECK(fdt_setprop_string(fdt, 0, "compatible", "test_tree1"));
CHECK(fdt_setprop_cell(fdt, 0, "prop-int", TEST_VALUE_1));
CHECK(fdt_setprop_string(fdt, 0, "prop-str", TEST_STRING_1));
OFF_CHECK(offset, fdt_add_subnode(fdt, 0, "subnode@1"));
s1 = offset;
CHECK(fdt_setprop_string(fdt, s1, "compatible", "subnode1"));
CHECK(fdt_setprop_cell(fdt, s1, "prop-int", TEST_VALUE_1));
OFF_CHECK(offset, fdt_add_subnode(fdt, s1, "subsubnode"));
CHECK(fdt_setprop(fdt, offset, "compatible",
"subsubnode1\0subsubnode", 23));
CHECK(fdt_setprop_cell(fdt, offset, "prop-int", TEST_VALUE_1));
OFF_CHECK(offset, fdt_add_subnode(fdt, s1, "ss1"));
OFF_CHECK(offset, fdt_add_subnode(fdt, 0, "subnode@2"));
s2 = offset;
CHECK(fdt_setprop_cell(fdt, s2, "linux,phandle", PHANDLE_1));
CHECK(fdt_setprop_cell(fdt, s2, "prop-int", TEST_VALUE_2));
OFF_CHECK(offset, fdt_add_subnode(fdt, s2, "subsubnode@0"));
CHECK(fdt_setprop_cell(fdt, offset, "linux,phandle", PHANDLE_2));
CHECK(fdt_setprop(fdt, offset, "compatible",
"subsubnode2\0subsubnode", 23));
CHECK(fdt_setprop_cell(fdt, offset, "prop-int", TEST_VALUE_2));
OFF_CHECK(offset, fdt_add_subnode(fdt, s2, "ss2"));
CHECK(fdt_pack(fdt));
save_blob("rw_tree1.test.dtb", fdt);
PASS();
}
void spapr_dt_xics(int nr_servers, void *fdt, uint32_t phandle)
{
uint32_t interrupt_server_ranges_prop[] = {
0, cpu_to_be32(nr_servers),
};
int node;
_FDT(node = fdt_add_subnode(fdt, 0, "interrupt-controller"));
_FDT(fdt_setprop_string(fdt, node, "device_type",
"PowerPC-External-Interrupt-Presentation"));
_FDT(fdt_setprop_string(fdt, node, "compatible", "IBM,ppc-xicp"));
_FDT(fdt_setprop(fdt, node, "interrupt-controller", NULL, 0));
_FDT(fdt_setprop(fdt, node, "ibm,interrupt-server-ranges",
interrupt_server_ranges_prop,
sizeof(interrupt_server_ranges_prop)));
_FDT(fdt_setprop_cell(fdt, node, "#interrupt-cells", 2));
_FDT(fdt_setprop_cell(fdt, node, "linux,phandle", phandle));
_FDT(fdt_setprop_cell(fdt, node, "phandle", phandle));
}
int qemu_devtree_setprop_cell(void *fdt, const char *node_path,
const char *property, uint32_t val)
{
int offset;
offset = fdt_path_offset(fdt, node_path);
if (offset < 0)
return offset;
return fdt_setprop_cell(fdt, offset, property, val);
}
void spapr_load_rtas(sPAPRMachineState *spapr, void *fdt, hwaddr addr)
{
int rtas_node;
int ret;
/* Copy RTAS blob into guest RAM */
cpu_physical_memory_write(addr, spapr->rtas_blob, spapr->rtas_size);
ret = fdt_add_mem_rsv(fdt, addr, spapr->rtas_size);
if (ret < 0) {
error_report("Couldn't add RTAS reserve entry: %s",
fdt_strerror(ret));
exit(1);
}
/* Update the device tree with the blob's location */
rtas_node = fdt_path_offset(fdt, "/rtas");
assert(rtas_node >= 0);
ret = fdt_setprop_cell(fdt, rtas_node, "linux,rtas-base", addr);
if (ret < 0) {
error_report("Couldn't add linux,rtas-base property: %s",
fdt_strerror(ret));
exit(1);
}
ret = fdt_setprop_cell(fdt, rtas_node, "linux,rtas-entry", addr);
if (ret < 0) {
error_report("Couldn't add linux,rtas-entry property: %s",
fdt_strerror(ret));
exit(1);
}
ret = fdt_setprop_cell(fdt, rtas_node, "rtas-size", spapr->rtas_size);
if (ret < 0) {
error_report("Couldn't add rtas-size property: %s",
fdt_strerror(ret));
exit(1);
}
}
static int pnv_lpc_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset)
{
const char compat[] = "ibm,power8-lpc\0ibm,lpc";
char *name;
int offset;
uint32_t lpc_pcba = PNV_XSCOM_LPC_BASE;
uint32_t reg[] = {
cpu_to_be32(lpc_pcba),
cpu_to_be32(PNV_XSCOM_LPC_SIZE)
};
name = g_strdup_printf("isa@%x", lpc_pcba);
offset = fdt_add_subnode(fdt, xscom_offset, name);
_FDT(offset);
g_free(name);
_FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))));
_FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 2)));
_FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 1)));
_FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat))));
return 0;
}
int qemu_fdt_setprop_cell(void *fdt, const char *node_path,
const char *property, uint32_t val)
{
int r;
r = fdt_setprop_cell(fdt, findnode_nofail(fdt, node_path), property, val);
if (r < 0) {
error_report("%s: Couldn't set %s/%s = %#08x: %s", __func__,
node_path, property, val, fdt_strerror(r));
exit(1);
}
return r;
}
void spapr_dt_rtas_tokens(void *fdt, int rtas)
{
int i;
for (i = 0; i < RTAS_TOKEN_MAX - RTAS_TOKEN_BASE; i++) {
struct rtas_call *call = &rtas_table[i];
if (!call->name) {
continue;
}
_FDT(fdt_setprop_cell(fdt, rtas, call->name, i + RTAS_TOKEN_BASE));
}
}
static void powernv_populate_icp(PnvChip *chip, void *fdt, uint32_t pir,
uint32_t nr_threads)
{
uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12);
char *name;
const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp";
uint32_t irange[2], i, rsize;
uint64_t *reg;
int offset;
irange[0] = cpu_to_be32(pir);
irange[1] = cpu_to_be32(nr_threads);
rsize = sizeof(uint64_t) * 2 * nr_threads;
reg = g_malloc(rsize);
for (i = 0; i < nr_threads; i++) {
reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000));
reg[i * 2 + 1] = cpu_to_be64(0x1000);
}
name = g_strdup_printf("interrupt-controller@%"PRIX64, addr);
offset = fdt_add_subnode(fdt, 0, name);
_FDT(offset);
g_free(name);
_FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat))));
_FDT((fdt_setprop(fdt, offset, "reg", reg, rsize)));
_FDT((fdt_setprop_string(fdt, offset, "device_type",
"PowerPC-External-Interrupt-Presentation")));
_FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0)));
_FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges",
irange, sizeof(irange))));
_FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1)));
_FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0)));
g_free(reg);
}
/**
* Add all bootstage timings to a device tree.
*
* @param blob Device tree blob
* @return 0 on success, != 0 on failure.
*/
static int add_bootstages_devicetree(struct fdt_header *blob)
{
struct bootstage_data *data = gd->bootstage;
int bootstage;
char buf[20];
int recnum;
int i;
if (!blob)
return 0;
/*
* Create the node for bootstage.
* The address of flat device tree is set up by the command bootm.
*/
bootstage = fdt_add_subnode(blob, 0, "bootstage");
if (bootstage < 0)
return -EINVAL;
/*
* Insert the timings to the device tree in the reverse order so
* that they can be printed in the Linux kernel in the right order.
*/
for (recnum = data->rec_count - 1, i = 0; recnum >= 0; recnum--, i++) {
struct bootstage_record *rec = &data->record[recnum];
int node;
if (rec->id != BOOTSTAGE_ID_AWAKE && rec->time_us == 0)
continue;
node = fdt_add_subnode(blob, bootstage, simple_itoa(i));
if (node < 0)
break;
/* add properties to the node. */
if (fdt_setprop_string(blob, node, "name",
get_record_name(buf, sizeof(buf), rec)))
return -EINVAL;
/* Check if this is a 'mark' or 'accum' record */
if (fdt_setprop_cell(blob, node,
rec->start_us ? "accum" : "mark",
rec->time_us))
return -EINVAL;
}
return 0;
}
/*
* Memory nodes are created by hostboot, one for each range of memory
* that has a different "affinity". In practice, it means one range
* per chip.
*/
static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size)
{
char *mem_name;
uint64_t mem_reg_property[2];
int off;
mem_reg_property[0] = cpu_to_be64(start);
mem_reg_property[1] = cpu_to_be64(size);
mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start);
off = fdt_add_subnode(fdt, 0, mem_name);
g_free(mem_name);
_FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
_FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
sizeof(mem_reg_property))));
_FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id)));
}
/*
* The PowerNV cores (and threads) need to use real HW ids and not an
* incremental index like it has been done on other platforms. This HW
* id is stored in the CPU PIR, it is used to create cpu nodes in the
* device tree, used in XSCOM to address cores and in interrupt
* servers.
*/
static void powernv_create_core_node(PnvChip *chip, PnvCore *pc, void *fdt)
{
CPUState *cs = CPU(DEVICE(pc->threads));
DeviceClass *dc = DEVICE_GET_CLASS(cs);
PowerPCCPU *cpu = POWERPC_CPU(cs);
int smt_threads = CPU_CORE(pc)->nr_threads;
CPUPPCState *env = &cpu->env;
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
uint32_t servers_prop[smt_threads];
int i;
uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
0xffffffff, 0xffffffff};
uint32_t tbfreq = PNV_TIMEBASE_FREQ;
uint32_t cpufreq = 1000000000;
uint32_t page_sizes_prop[64];
size_t page_sizes_prop_size;
const uint8_t pa_features[] = { 24, 0,
0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0,
0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
int offset;
char *nodename;
int cpus_offset = get_cpus_node(fdt);
nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir);
offset = fdt_add_subnode(fdt, cpus_offset, nodename);
_FDT(offset);
g_free(nodename);
_FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id)));
_FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir)));
_FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir)));
_FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
_FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
_FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
env->dcache_line_size)));
_FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
env->dcache_line_size)));
_FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
env->icache_line_size)));
_FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
env->icache_line_size)));
if (pcc->l1_dcache_size) {
_FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
pcc->l1_dcache_size)));
} else {
warn_report("Unknown L1 dcache size for cpu");
}
if (pcc->l1_icache_size) {
_FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
pcc->l1_icache_size)));
} else {
warn_report("Unknown L1 icache size for cpu");
}
_FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
_FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
_FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr)));
_FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
_FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
if (env->spr_cb[SPR_PURR].oea_read) {
_FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
}
if (env->mmu_model & POWERPC_MMU_1TSEG) {
_FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
segs, sizeof(segs))));
}
/* Advertise VMX/VSX (vector extensions) if available
* 0 / no property == no vector extensions
* 1 == VMX / Altivec available
* 2 == VSX available */
if (env->insns_flags & PPC_ALTIVEC) {
uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
_FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
}
/* Advertise DFP (Decimal Floating Point) if available
* 0 / no property == no DFP
* 1 == DFP available */
if (env->insns_flags2 & PPC2_DFP) {
_FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
}
page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop,
sizeof(page_sizes_prop));
if (page_sizes_prop_size) {
_FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
page_sizes_prop, page_sizes_prop_size)));
}
_FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
pa_features, sizeof(pa_features))));
/* Build interrupt servers properties */
for (i = 0; i < smt_threads; i++) {
servers_prop[i] = cpu_to_be32(pc->pir + i);
}
_FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
servers_prop, sizeof(servers_prop))));
}
static int spapr_nvram_devnode(VIOsPAPRDevice *dev, void *fdt, int node_off)
{
sPAPRNVRAM *nvram = VIO_SPAPR_NVRAM(dev);
return fdt_setprop_cell(fdt, node_off, "#bytes", nvram->size);
}
STATIC
EFI_STATUS
PrepareFdt (
IN OUT VOID *Fdt,
IN UINTN FdtSize
)
{
EFI_STATUS Status;
INT32 Node;
INT32 CpuNode;
UINTN Index;
ARM_CORE_INFO *ArmCoreInfoTable;
UINTN ArmCoreCount;
INT32 MapNode;
INT32 ClusterNode;
INT32 PmuNode;
PMU_INTERRUPT PmuInt;
INT32 Phandle[NUM_CORES];
UINT32 ClusterIndex;
UINT32 CoreIndex;
UINT32 ClusterCount;
UINT32 CoresInCluster;
UINT32 ClusterId;
UINTN MpId;
CHAR8 Name[10];
AMD_MP_CORE_INFO_PROTOCOL *AmdMpCoreInfoProtocol;
//
// Setup Arm Mpcore Info if it is a multi-core or multi-cluster platforms.
//
// For 'cpus' and 'cpu' device tree nodes bindings, refer to this file
// in the kernel documentation:
// Documentation/devicetree/bindings/arm/cpus.txt
//
Status = gBS->LocateProtocol (
&gAmdMpCoreInfoProtocolGuid,
NULL,
(VOID **)&AmdMpCoreInfoProtocol
);
ASSERT_EFI_ERROR (Status);
// Get pointer to ARM core info table
ArmCoreInfoTable = AmdMpCoreInfoProtocol->GetArmCoreInfoTable (&ArmCoreCount);
ASSERT (ArmCoreInfoTable != NULL);
ASSERT (ArmCoreCount <= NUM_CORES);
// Get Id from primary CPU
MpId = (UINTN)ArmReadMpidr ();
// Create /pmu node
PmuNode = fdt_add_subnode(Fdt, 0, "pmu");
if (PmuNode >= 0) {
fdt_setprop_string (Fdt, PmuNode, "compatible", "arm,armv8-pmuv3");
// append PMU interrupts
for (Index = 0; Index < ArmCoreCount; Index++) {
MpId = (UINTN)GET_MPID (ArmCoreInfoTable[Index].ClusterId,
ArmCoreInfoTable[Index].CoreId);
Status = AmdMpCoreInfoProtocol->GetPmuSpiFromMpId (MpId, &PmuInt.IntId);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR,
"FDT: Error getting PMU interrupt for MpId '0x%x'\n", MpId));
return Status;
}
PmuInt.Flag = cpu_to_fdt32 (PMU_INT_FLAG_SPI);
PmuInt.IntId = cpu_to_fdt32 (PmuInt.IntId);
PmuInt.Type = cpu_to_fdt32 (PMU_INT_TYPE_HIGH_LEVEL);
fdt_appendprop (Fdt, PmuNode, "interrupts", &PmuInt, sizeof(PmuInt));
}
} else {
DEBUG ((DEBUG_ERROR, "FDT: Error creating 'pmu' node\n"));
return EFI_INVALID_PARAMETER;
}
// Create /cpus noide
Node = fdt_add_subnode (Fdt, 0, "cpus");
if (Node >= 0) {
// Configure the 'cpus' node
fdt_setprop_string (Fdt, Node, "name", "cpus");
fdt_setprop_cell (Fdt, Node, "#address-cells", sizeof (UINTN) / 4);
fdt_setprop_cell (Fdt, Node, "#size-cells", 0);
} else {
DEBUG ((DEBUG_ERROR, "FDT: Error creating 'cpus' node\n"));
return EFI_INVALID_PARAMETER;
}
//
// Walk the processor table in reverse order for proper listing in FDT
//
Index = ArmCoreCount;
while (Index--) {
// Create 'cpu' node
AsciiSPrint (Name, sizeof (Name), "CPU%d", Index);
CpuNode = fdt_add_subnode (Fdt, Node, Name);
if (CpuNode < 0) {
DEBUG ((DEBUG_ERROR, "FDT: Error on creating '%a' node\n", Name));
return EFI_INVALID_PARAMETER;
}
Phandle[Index] = fdt_alloc_phandle (Fdt);
fdt_setprop_cell (Fdt, CpuNode, "phandle", Phandle[Index]);
fdt_setprop_cell (Fdt, CpuNode, "linux,phandle", Phandle[Index]);
fdt_setprop_string (Fdt, CpuNode, "enable-method", "psci");
MpId = (UINTN)GET_MPID (ArmCoreInfoTable[Index].ClusterId,
ArmCoreInfoTable[Index].CoreId);
MpId = cpu_to_fdt64 (MpId);
fdt_setprop (Fdt, CpuNode, "reg", &MpId, sizeof (MpId));
fdt_setprop_string (Fdt, CpuNode, "compatible", "arm,armv8");
fdt_setprop_string (Fdt, CpuNode, "device_type", "cpu");
}
// Create /cpu-map node
MapNode = fdt_add_subnode (Fdt, Node, "cpu-map");
if (MapNode >= 0) {
ClusterIndex = ArmCoreCount - 1;
ClusterCount = NumberOfClustersInTable (ArmCoreInfoTable,
ArmCoreCount);
while (ClusterCount--) {
// Create 'cluster' node
AsciiSPrint (Name, sizeof (Name), "cluster%d", ClusterCount);
ClusterNode = fdt_add_subnode (Fdt, MapNode, Name);
if (ClusterNode < 0) {
DEBUG ((DEBUG_ERROR, "FDT: Error creating '%a' node\n", Name));
return EFI_INVALID_PARAMETER;
}
ClusterId = ArmCoreInfoTable[ClusterIndex].ClusterId;
CoreIndex = ClusterIndex;
CoresInCluster = NumberOfCoresInCluster (ArmCoreInfoTable,
ArmCoreCount,
ClusterId);
while (CoresInCluster--) {
// Create 'core' node
AsciiSPrint (Name, sizeof (Name), "core%d", CoresInCluster);
CpuNode = fdt_add_subnode (Fdt, ClusterNode, Name);
if (CpuNode < 0) {
DEBUG ((DEBUG_ERROR, "FDT: Error creating '%a' node\n", Name));
return EFI_INVALID_PARAMETER;
}
fdt_setprop_cell (Fdt, CpuNode, "cpu", Phandle[CoreIndex]);
// iterate to next core in cluster
if (CoresInCluster) {
do {
--CoreIndex;
} while (ClusterId != ArmCoreInfoTable[CoreIndex].ClusterId);
}
}
// iterate to next cluster
if (ClusterCount) {
do {
--ClusterIndex;
} while (ClusterInRange (ArmCoreInfoTable,
ArmCoreInfoTable[ClusterIndex].ClusterId,
ClusterIndex + 1,
ArmCoreCount - 1));
}
}
} else {
DEBUG ((DEBUG_ERROR,"FDT: Error creating 'cpu-map' node\n"));
return EFI_INVALID_PARAMETER;
}
SetSocIdStatus (Fdt);
SetXgbeStatus (Fdt);
// Update the real size of the Device Tree
fdt_pack (Fdt);
return EFI_SUCCESS;
}
int main(int argc, char *argv[])
{
void *fdt;
void *buf;
const uint32_t *intp;
const char *strp;
int err;
test_init(argc, argv);
fdt = load_blob_arg(argc, argv);
buf = xmalloc(SPACE);
err = fdt_open_into(fdt, buf, SPACE);
if (err)
FAIL("fdt_open_into(): %s", fdt_strerror(err));
fdt = buf;
intp = check_getprop_cell(fdt, 0, "prop-int", TEST_VALUE_1);
verbose_printf("Old int value was 0x%08x\n", *intp);
err = fdt_setprop_string(fdt, 0, "prop-int", NEW_STRING);
if (err)
FAIL("Failed to set \"prop-int\" to \"%s\": %s",
NEW_STRING, fdt_strerror(err));
strp = check_getprop_string(fdt, 0, "prop-int", NEW_STRING);
verbose_printf("New value is \"%s\"\n", strp);
strp = check_getprop(fdt, 0, "prop-str", strlen(TEST_STRING_1)+1,
TEST_STRING_1);
verbose_printf("Old string value was \"%s\"\n", strp);
err = fdt_setprop(fdt, 0, "prop-str", NULL, 0);
if (err)
FAIL("Failed to empty \"prop-str\": %s",
fdt_strerror(err));
check_getprop(fdt, 0, "prop-str", 0, NULL);
err = fdt_setprop_u32(fdt, 0, "prop-u32", TEST_VALUE_2);
if (err)
FAIL("Failed to set \"prop-u32\" to 0x%08x: %s",
TEST_VALUE_2, fdt_strerror(err));
check_getprop_cell(fdt, 0, "prop-u32", TEST_VALUE_2);
err = fdt_setprop_cell(fdt, 0, "prop-cell", TEST_VALUE_2);
if (err)
FAIL("Failed to set \"prop-cell\" to 0x%08x: %s",
TEST_VALUE_2, fdt_strerror(err));
check_getprop_cell(fdt, 0, "prop-cell", TEST_VALUE_2);
err = fdt_setprop_u64(fdt, 0, "prop-u64", TEST_VALUE64_1);
if (err)
FAIL("Failed to set \"prop-u64\" to 0x%016llx: %s",
TEST_VALUE64_1, fdt_strerror(err));
check_getprop_64(fdt, 0, "prop-u64", TEST_VALUE64_1);
PASS();
}
