int exynos5422_fimc_is_sensor_iclk_cfg(struct platform_device *pdev,
u32 scenario,
u32 channel)
{
int ret = 0;
pr_info("clk_cfg:(ch%d),scenario(%d)\n", channel, scenario);
switch (channel) {
case 0:
/* MIPI-CSIS0 */
fimc_is_set_parent_dt(pdev, "mout_gscl_wrap_a", "mout_mpll_ctrl");
fimc_is_set_rate_dt(pdev, "dout_gscl_wrap_a", (532 * 1000000));
fimc_is_get_rate_dt(pdev, "dout_gscl_wrap_a");
break;
case 1:
/* FL1_550_CAM */
fimc_is_set_parent_dt(pdev, "mout_aclk_fl1_550_cam", "mout_mpll_ctrl");
fimc_is_set_rate_dt(pdev, "dout_aclk_fl1_550_cam", (76 * 1000000));
fimc_is_set_parent_dt(pdev, "mout_aclk_fl1_550_cam_sw", "dout_aclk_fl1_550_cam");
fimc_is_set_parent_dt(pdev, "mout_aclk_fl1_550_cam_user", "mout_aclk_fl1_550_cam_sw");
fimc_is_set_rate_dt(pdev, "dout2_cam_blk_550", (38 * 1000000));
/* MIPI-CSIS1 */
fimc_is_set_parent_dt(pdev, "mout_gscl_wrap_b", "mout_mpll_ctrl");
fimc_is_set_rate_dt(pdev, "dout_gscl_wrap_b", (76 * 1000000));
fimc_is_get_rate_dt(pdev, "dout_gscl_wrap_b");
break;
default:
pr_err("channel is invalid(%d)\n", channel);
break;
}
return ret;
}
static int pn547_clk_initialize(struct pn547_dev *pn547_dev)
{
#if defined(CONFIG_SOC_EXYNOS5422)
pn547_dev->clk = clk_get(&pn547_dev->client->dev, "sclk_isp_sensor1");
if (IS_ERR(pn547_dev->clk)) {
pr_err("%s : clk not found\n", __func__);
return -EPERM;
}
#elif defined(CONFIG_SOC_EXYNOS5430)
if (pn547_dev->clk_use_check == CLK_USE_CAM1) {
u32 frequency;
int ret;
ret = fimc_is_set_parent_dt(pn547_dev->pdev, "mout_sclk_isp_sensor1", "oscclk");
if (ret) {
pr_err("%s, fimc_is_set_parent_dt:%d\n", __func__, ret);
return -EPERM;
}
ret = fimc_is_set_rate_dt(pn547_dev->pdev, "dout_sclk_isp_sensor1_a", 24 * 1000000);
if (ret) {
pr_err("%s, fimc_is_set_rate_dt A:%d\n", __func__, ret);
return -EPERM;
}
ret = fimc_is_set_rate_dt(pn547_dev->pdev, "dout_sclk_isp_sensor1_b", 24 * 1000000);
if (ret) {
pr_err("%s, fimc_is_set_rate_dt B:%d\n", __func__, ret);
return -EPERM;
}
frequency = fimc_is_get_rate_dt(pn547_dev->pdev, "sclk_isp_sensor1");
pr_info("%s(mclk : %d)\n", __func__, frequency);
}
#endif
return 0;
}
int exynos5430_fimc_is_sensor_mclk_on(struct platform_device *pdev,
u32 scenario,
u32 channel)
{
u32 frequency;
char mux_name[30];
char div_a_name[30];
char div_b_name[30];
char sclk_name[30];
pr_debug("%s\n", __func__);
snprintf(mux_name, sizeof(mux_name), "mout_sclk_isp_sensor%d", channel);
snprintf(div_a_name, sizeof(div_a_name), "dout_sclk_isp_sensor%d_a", channel);
snprintf(div_b_name, sizeof(div_b_name), "dout_sclk_isp_sensor%d_b", channel);
snprintf(sclk_name, sizeof(sclk_name), "sclk_isp_sensor%d", channel);
fimc_is_set_parent_dt(pdev, mux_name, "oscclk");
fimc_is_set_rate_dt(pdev, div_a_name, 24 * 1000000);
fimc_is_set_rate_dt(pdev, div_b_name, 24 * 1000000);
frequency = fimc_is_get_rate_dt(pdev, sclk_name);
pr_info("%s(%d, mclk : %d)\n", __func__, channel, frequency);
return 0;
}
int exynos5422_fimc_is_sensor_mclk_on(struct platform_device *pdev,
u32 scenario,
u32 channel)
{
u32 frequency;
char div_name[30];
char sclk_name[30];
pr_info("%s:ch(%d)\n", __func__, channel);
snprintf(div_name, sizeof(div_name), "dout_isp_sensor%d", channel);
snprintf(sclk_name, sizeof(sclk_name), "sclk_isp_sensor%d", channel);
fimc_is_set_parent_dt(pdev, "mout_isp_sensor", "fin_pll");
fimc_is_set_rate_dt(pdev, div_name, (24 * 1000000));
fimc_is_enable_dt(pdev, sclk_name);
frequency = fimc_is_get_rate_dt(pdev, div_name);
switch (channel) {
case SENSOR_CONTROL_I2C0:
fimc_is_enable_dt(pdev, "sclk_gscl_wrap_a");
fimc_is_enable_dt(pdev, "clk_camif_top_fimcl0");
fimc_is_enable_dt(pdev, "clk_camif_top_fimcl3");
fimc_is_enable_dt(pdev, "gscl_fimc_lite0");
fimc_is_enable_dt(pdev, "gscl_fimc_lite3");
fimc_is_enable_dt(pdev, "clk_gscl_wrap_a");
break;
case SENSOR_CONTROL_I2C1:
case SENSOR_CONTROL_I2C2:
fimc_is_enable_dt(pdev, "sclk_gscl_wrap_b");
fimc_is_enable_dt(pdev, "clk_camif_top_fimcl1");
fimc_is_enable_dt(pdev, "gscl_fimc_lite1");
fimc_is_enable_dt(pdev, "clk_gscl_wrap_b");
break;
default:
pr_err("channel is invalid(%d)\n", channel);
break;
}
fimc_is_enable_dt(pdev, "clk_camif_top_csis0");
fimc_is_enable_dt(pdev, "clk_xiu_si_gscl_cam");
fimc_is_enable_dt(pdev, "clk_noc_p_rstop_fimcl");
pr_info("%s(%d, mclk : %d)\n", __func__, channel, frequency);
return 0;
}
int exynos3475_fimc_is_print_clk(struct platform_device *pdev)
{
pr_debug("%s\n", __func__);
/** CMU_ISP **/
fimc_is_get_rate_dt(pdev, "mout_aclk_isp_300_user");
fimc_is_get_rate_dt(pdev, "aclk_isp_300_aclk_is");
fimc_is_get_rate_dt(pdev, "aclk_isp_300_aclk_fd");
fimc_is_get_rate_dt(pdev, "aclk_isp_300_aclk_ppmu");
fimc_is_get_rate_dt(pdev, "aclk_isp_300_aclk_isp_d");
fimc_is_get_rate_dt(pdev, "dout_pclk_isp_150");
return 0;
}
int exynos5430_fimc_is_sensor_mclk_off(struct platform_device *pdev,
u32 scenario,
u32 channel)
{
char mux_name[30];
char div_a_name[30];
char div_b_name[30];
char sclk_name[30];
pr_debug("%s\n", __func__);
snprintf(mux_name, sizeof(mux_name), "mout_sclk_isp_sensor%d", channel);
snprintf(div_a_name, sizeof(div_a_name), "dout_sclk_isp_sensor%d_a", channel);
snprintf(div_b_name, sizeof(div_b_name), "dout_sclk_isp_sensor%d_b", channel);
snprintf(sclk_name, sizeof(sclk_name), "sclk_isp_sensor%d", channel);
fimc_is_set_parent_dt(pdev, mux_name, "oscclk");
fimc_is_set_rate_dt(pdev, div_a_name, 1);
fimc_is_set_rate_dt(pdev, div_b_name, 1);
fimc_is_get_rate_dt(pdev, sclk_name);
return 0;
}
int exynos5430_fimc_is_print_clk(struct platform_device *pdev)
{
pr_debug("%s\n", __func__);
/* SCLK */
/* SCLK_SPI0 */
fimc_is_get_rate_dt(pdev, "sclk_isp_spi0_top");
fimc_is_get_rate_dt(pdev, "sclk_isp_spi0");
/* SCLK_SPI1 */
fimc_is_get_rate_dt(pdev, "sclk_isp_spi1_top");
fimc_is_get_rate_dt(pdev, "sclk_isp_spi1");
/* SCLK_UART */
fimc_is_get_rate_dt(pdev, "sclk_isp_uart_top");
fimc_is_get_rate_dt(pdev, "sclk_isp_uart");
/* CAM0 */
/* CMU_TOP */
fimc_is_get_rate_dt(pdev, "aclk_cam0_552");
fimc_is_get_rate_dt(pdev, "aclk_cam0_400");
fimc_is_get_rate_dt(pdev, "aclk_cam0_333");
/* LITE A */
fimc_is_get_rate_dt(pdev, "dout_aclk_lite_a");
fimc_is_get_rate_dt(pdev, "dout_pclk_lite_a");
/* LITE B */
fimc_is_get_rate_dt(pdev, "dout_aclk_lite_b");
fimc_is_get_rate_dt(pdev, "dout_pclk_lite_b");
/* LITE D */
fimc_is_get_rate_dt(pdev, "dout_aclk_lite_d");
fimc_is_get_rate_dt(pdev, "dout_pclk_lite_d");
/* LITE C PIXELASYNC */
fimc_is_get_rate_dt(pdev, "dout_sclk_pixelasync_lite_c_init");
fimc_is_get_rate_dt(pdev, "dout_pclk_pixelasync_lite_c");
fimc_is_get_rate_dt(pdev, "dout_sclk_pixelasync_lite_c");
/* 3AA 0 */
fimc_is_get_rate_dt(pdev, "dout_aclk_3aa0");
fimc_is_get_rate_dt(pdev, "dout_pclk_3aa0");
/* 3AA 0 */
fimc_is_get_rate_dt(pdev, "dout_aclk_3aa1");
fimc_is_get_rate_dt(pdev, "dout_pclk_3aa1");
/* CSI 0 */
fimc_is_get_rate_dt(pdev, "dout_aclk_csis0");
/* CSI 1 */
fimc_is_get_rate_dt(pdev, "dout_aclk_csis1");
/* CAM0 400 */
fimc_is_get_rate_dt(pdev, "dout_aclk_cam0_400");
fimc_is_get_rate_dt(pdev, "dout_aclk_cam0_200");
fimc_is_get_rate_dt(pdev, "dout_pclk_cam0_50");
/* CAM1 */
/* CMU_TOP */
fimc_is_get_rate_dt(pdev, "aclk_cam1_552");
fimc_is_get_rate_dt(pdev, "aclk_cam1_400");
fimc_is_get_rate_dt(pdev, "aclk_cam1_333");
/* C-A5 */
fimc_is_get_rate_dt(pdev, "dout_atclk_cam1");
fimc_is_get_rate_dt(pdev, "dout_pclk_dbg_cam1");
/* LITE A */
fimc_is_get_rate_dt(pdev, "dout_aclk_lite_c");
fimc_is_get_rate_dt(pdev, "dout_pclk_lite_c");
/* FD */
fimc_is_get_rate_dt(pdev, "dout_aclk_fd");
fimc_is_get_rate_dt(pdev, "dout_pclk_fd");
/* CSI 2 */
fimc_is_get_rate_dt(pdev, "dout_aclk_csis2_a");
/* MPWM */
fimc_is_get_rate_dt(pdev, "dout_pclk_cam1_166");
fimc_is_get_rate_dt(pdev, "dout_pclk_cam1_83");
fimc_is_get_rate_dt(pdev, "dout_sclk_isp_mpwm");
/* ISP */
/* CMU_TOP */
fimc_is_get_rate_dt(pdev, "aclk_isp_400");
fimc_is_get_rate_dt(pdev, "aclk_isp_dis_400");
/* ISP */
fimc_is_get_rate_dt(pdev, "dout_aclk_isp_c_200");
fimc_is_get_rate_dt(pdev, "dout_aclk_isp_d_200");
fimc_is_get_rate_dt(pdev, "dout_pclk_isp");
/* DIS */
fimc_is_get_rate_dt(pdev, "dout_pclk_isp_dis");
/* CMU_TOP_DUMP */
pr_info("EXYNOS5430_SRC_SEL_TOP1(0x%08X)\n", readl(EXYNOS5430_SRC_SEL_TOP1));
pr_info("EXYNOS5430_SRC_SEL_TOP2(0x%08X)\n", readl(EXYNOS5430_SRC_SEL_TOP2));
pr_info("EXYNOS5430_SRC_SEL_TOP_CAM1(0x%08X)\n", readl(EXYNOS5430_SRC_SEL_TOP_CAM1));
pr_info("EXYNOS5430_SRC_ENABLE_TOP0(0x%08X)\n", readl(EXYNOS5430_SRC_ENABLE_TOP0));
pr_info("EXYNOS5430_SRC_ENABLE_TOP1(0x%08X)\n", readl(EXYNOS5430_SRC_ENABLE_TOP1));
pr_info("EXYNOS5430_SRC_ENABLE_TOP2(0x%08X)\n", readl(EXYNOS5430_SRC_ENABLE_TOP2));
pr_info("EXYNOS5430_SRC_ENABLE_TOP3(0x%08X)\n", readl(EXYNOS5430_SRC_ENABLE_TOP3));
pr_info("EXYNOS5430_SRC_ENABLE_TOP_CAM1(0x%08X)\n", readl(EXYNOS5430_SRC_ENABLE_TOP_CAM1));
pr_info("EXYNOS5430_DIV_TOP0(0x%08X)\n", readl(EXYNOS5430_DIV_TOP0));
pr_info("EXYNOS5430_DIV_TOP_CAM10(0x%08X)\n", readl(EXYNOS5430_DIV_TOP_CAM10));
pr_info("EXYNOS5430_DIV_TOP_CAM11(0x%08X)\n", readl(EXYNOS5430_DIV_TOP_CAM11));
pr_info("EXYNOS5430_ENABLE_SCLK_TOP_CAM1(0x%08X)\n", readl(EXYNOS5430_ENABLE_SCLK_TOP_CAM1));
pr_info("EXYNOS5430_ENABLE_IP_TOP(0x%08X)\n", readl(EXYNOS5430_ENABLE_IP_TOP));
/* CMU_CAM0_DUMP */
pr_info("EXYNOS5430_SRC_SEL_CAM00(0x%08X)\n", readl(EXYNOS5430_SRC_SEL_CAM00));
pr_info("EXYNOS5430_SRC_SEL_CAM01(0x%08X)\n", readl(EXYNOS5430_SRC_SEL_CAM01));
pr_info("EXYNOS5430_SRC_SEL_CAM02(0x%08X)\n", readl(EXYNOS5430_SRC_SEL_CAM02));
pr_info("EXYNOS5430_SRC_SEL_CAM03(0x%08X)\n", readl(EXYNOS5430_SRC_SEL_CAM03));
pr_info("EXYNOS5430_SRC_SEL_CAM04(0x%08X)\n", readl(EXYNOS5430_SRC_SEL_CAM04));
pr_info("EXYNOS5430_SRC_ENABLE_CAM00(0x%08X)\n", readl(EXYNOS5430_SRC_ENABLE_CAM00));
pr_info("EXYNOS5430_SRC_ENABLE_CAM01(0x%08X)\n", readl(EXYNOS5430_SRC_ENABLE_CAM01));
pr_info("EXYNOS5430_SRC_ENABLE_CAM02(0x%08X)\n", readl(EXYNOS5430_SRC_ENABLE_CAM02));
pr_info("EXYNOS5430_SRC_ENABLE_CAM03(0x%08X)\n", readl(EXYNOS5430_SRC_ENABLE_CAM03));
pr_info("EXYNOS5430_SRC_ENABLE_CAM04(0x%08X)\n", readl(EXYNOS5430_SRC_ENABLE_CAM04));
pr_info("EXYNOS5430_SRC_STAT_CAM00(0x%08X)\n", readl(EXYNOS5430_SRC_STAT_CAM00));
pr_info("EXYNOS5430_SRC_STAT_CAM01(0x%08X)\n", readl(EXYNOS5430_SRC_STAT_CAM01));
pr_info("EXYNOS5430_SRC_STAT_CAM02(0x%08X)\n", readl(EXYNOS5430_SRC_STAT_CAM02));
pr_info("EXYNOS5430_SRC_STAT_CAM03(0x%08X)\n", readl(EXYNOS5430_SRC_STAT_CAM03));
pr_info("EXYNOS5430_SRC_STAT_CAM04(0x%08X)\n", readl(EXYNOS5430_SRC_STAT_CAM04));
pr_info("EXYNOS5430_SRC_IGNORE_CAM01(0x%08X)\n", readl(EXYNOS5430_SRC_IGNORE_CAM01));
pr_info("EXYNOS5430_DIV_CAM00(0x%08X)\n", readl(EXYNOS5430_DIV_CAM00));
pr_info("EXYNOS5430_DIV_CAM01(0x%08X)\n", readl(EXYNOS5430_DIV_CAM01));
pr_info("EXYNOS5430_DIV_CAM02(0x%08X)\n", readl(EXYNOS5430_DIV_CAM02));
pr_info("EXYNOS5430_DIV_CAM03(0x%08X)\n", readl(EXYNOS5430_DIV_CAM03));
pr_info("EXYNOS5430_DIV_STAT_CAM00(0x%08X)\n", readl(EXYNOS5430_DIV_STAT_CAM00));
pr_info("EXYNOS5430_DIV_STAT_CAM01(0x%08X)\n", readl(EXYNOS5430_DIV_STAT_CAM01));
pr_info("EXYNOS5430_DIV_STAT_CAM02(0x%08X)\n", readl(EXYNOS5430_DIV_STAT_CAM02));
pr_info("EXYNOS5430_DIV_STAT_CAM03(0x%08X)\n", readl(EXYNOS5430_DIV_STAT_CAM03));
pr_info("EXYNOS5430_ENABLE_IP_CAM00(0x%08X)\n", readl(EXYNOS5430_ENABLE_IP_CAM00));
pr_info("EXYNOS5430_ENABLE_IP_CAM01(0x%08X)\n", readl(EXYNOS5430_ENABLE_IP_CAM01));
pr_info("EXYNOS5430_ENABLE_IP_CAM02(0x%08X)\n", readl(EXYNOS5430_ENABLE_IP_CAM02));
pr_info("EXYNOS5430_ENABLE_IP_CAM03(0x%08X)\n", readl(EXYNOS5430_ENABLE_IP_CAM03));
/* CMU_CAM1_DUMP */
pr_info("EXYNOS5430_SRC_SEL_CAM10(0x%08X)\n", readl(EXYNOS5430_SRC_SEL_CAM10));
pr_info("EXYNOS5430_SRC_SEL_CAM11(0x%08X)\n", readl(EXYNOS5430_SRC_SEL_CAM11));
pr_info("EXYNOS5430_SRC_SEL_CAM12(0x%08X)\n", readl(EXYNOS5430_SRC_SEL_CAM12));
pr_info("EXYNOS5430_SRC_ENABLE_CAM10(0x%08X)\n", readl(EXYNOS5430_SRC_ENABLE_CAM10));
pr_info("EXYNOS5430_SRC_ENABLE_CAM11(0x%08X)\n", readl(EXYNOS5430_SRC_ENABLE_CAM11));
pr_info("EXYNOS5430_SRC_ENABLE_CAM12(0x%08X)\n", readl(EXYNOS5430_SRC_ENABLE_CAM12));
pr_info("EXYNOS5430_SRC_STAT_CAM10(0x%08X)\n", readl(EXYNOS5430_SRC_STAT_CAM10));
pr_info("EXYNOS5430_SRC_STAT_CAM11(0x%08X)\n", readl(EXYNOS5430_SRC_STAT_CAM11));
pr_info("EXYNOS5430_SRC_STAT_CAM12(0x%08X)\n", readl(EXYNOS5430_SRC_STAT_CAM12));
pr_info("EXYNOS5430_SRC_IGNORE_CAM11(0x%08X)\n", readl(EXYNOS5430_SRC_IGNORE_CAM11));
pr_info("EXYNOS5430_DIV_CAM10(0x%08X)\n", readl(EXYNOS5430_DIV_CAM10));
pr_info("EXYNOS5430_DIV_CAM11(0x%08X)\n", readl(EXYNOS5430_DIV_CAM11));
pr_info("EXYNOS5430_DIV_STAT_CAM10(0x%08X)\n", readl(EXYNOS5430_DIV_STAT_CAM10));
pr_info("EXYNOS5430_DIV_STAT_CAM11(0x%08X)\n", readl(EXYNOS5430_DIV_STAT_CAM11));
pr_info("EXYNOS5430_ENABLE_SCLK_CAM1(0x%08X)\n", readl(EXYNOS5430_ENABLE_SCLK_CAM1));
pr_info("EXYNOS5430_ENABLE_IP_CAM10(0x%08X)\n", readl(EXYNOS5430_ENABLE_IP_CAM10));
pr_info("EXYNOS5430_ENABLE_IP_CAM11(0x%08X)\n", readl(EXYNOS5430_ENABLE_IP_CAM11));
pr_info("EXYNOS5430_ENABLE_IP_CAM12(0x%08X)\n", readl(EXYNOS5430_ENABLE_IP_CAM12));
/* CMU_ISP_DUMP */
pr_info("EXYNOS5430_SRC_SEL_ISP(0x%08X)\n", readl(EXYNOS5430_SRC_SEL_ISP));
pr_info("EXYNOS5430_SRC_ENABLE_ISP(0x%08X)\n", readl(EXYNOS5430_SRC_ENABLE_ISP));
pr_info("EXYNOS5430_SRC_STAT_ISP(0x%08X)\n", readl(EXYNOS5430_SRC_STAT_ISP));
pr_info("EXYNOS5430_DIV_ISP(0x%08X)\n", readl(EXYNOS5430_DIV_ISP));
pr_info("EXYNOS5430_DIV_STAT_ISP(0x%08X)\n", readl(EXYNOS5430_DIV_STAT_ISP));
pr_info("EXYNOS5430_ENABLE_ACLK_ISP0(0x%08X)\n", readl(EXYNOS5430_ENABLE_ACLK_ISP0));
pr_info("EXYNOS5430_ENABLE_ACLK_ISP1(0x%08X)\n", readl(EXYNOS5430_ENABLE_ACLK_ISP1));
pr_info("EXYNOS5430_ENABLE_ACLK_ISP2(0x%08X)\n", readl(EXYNOS5430_ENABLE_ACLK_ISP2));
pr_info("EXYNOS5430_ENABLE_PCLK_ISP(0x%08X)\n", readl(EXYNOS5430_ENABLE_PCLK_ISP));
pr_info("EXYNOS5430_ENABLE_SCLK_ISP(0x%08X)\n", readl(EXYNOS5430_ENABLE_SCLK_ISP));
pr_info("EXYNOS5430_ENABLE_IP_ISP0(0x%08X)\n", readl(EXYNOS5430_ENABLE_IP_ISP0));
pr_info("EXYNOS5430_ENABLE_IP_ISP1(0x%08X)\n", readl(EXYNOS5430_ENABLE_IP_ISP1));
pr_info("EXYNOS5430_ENABLE_IP_ISP2(0x%08X)\n", readl(EXYNOS5430_ENABLE_IP_ISP2));
pr_info("EXYNOS5430_ENABLE_IP_ISP3(0x%08X)\n", readl(EXYNOS5430_ENABLE_IP_ISP3));
/* CMU_ENABLE_DUMP */
pr_info("EXYNOS5430_ENABLE_SCLK_TOP_CAM1(0x%08X)\n", readl(EXYNOS5430_ENABLE_SCLK_TOP_CAM1));
pr_info("EXYNOS5430_ENABLE_IP_TOP(0x%08X)\n", readl(EXYNOS5430_ENABLE_IP_TOP));
pr_info("EXYNOS5430_ENABLE_IP_CAM00(0x%08X)\n", readl(EXYNOS5430_ENABLE_IP_CAM00));
pr_info("EXYNOS5430_ENABLE_IP_CAM01(0x%08X)\n", readl(EXYNOS5430_ENABLE_IP_CAM01));
pr_info("EXYNOS5430_ENABLE_IP_CAM02(0x%08X)\n", readl(EXYNOS5430_ENABLE_IP_CAM02));
pr_info("EXYNOS5430_ENABLE_IP_CAM03(0x%08X)\n", readl(EXYNOS5430_ENABLE_IP_CAM03));
pr_info("EXYNOS5430_ENABLE_IP_CAM10(0x%08X)\n", readl(EXYNOS5430_ENABLE_IP_CAM10));
pr_info("EXYNOS5430_ENABLE_IP_CAM11(0x%08X)\n", readl(EXYNOS5430_ENABLE_IP_CAM11));
pr_info("EXYNOS5430_ENABLE_IP_CAM12(0x%08X)\n", readl(EXYNOS5430_ENABLE_IP_CAM12));
pr_info("EXYNOS5430_ENABLE_IP_ISP0(0x%08X)\n", readl(EXYNOS5430_ENABLE_IP_ISP0));
pr_info("EXYNOS5430_ENABLE_IP_ISP1(0x%08X)\n", readl(EXYNOS5430_ENABLE_IP_ISP1));
pr_info("EXYNOS5430_ENABLE_IP_ISP2(0x%08X)\n", readl(EXYNOS5430_ENABLE_IP_ISP2));
pr_info("EXYNOS5430_ENABLE_IP_ISP3(0x%08X)\n", readl(EXYNOS5430_ENABLE_IP_ISP3));
return 0;
}
int exynos5422_fimc_is_print_clk(struct platform_device *pdev)
{
pr_debug("%s\n", __func__);
fimc_is_get_rate_dt(pdev, "mout_aclk_550_cam_user");
fimc_is_get_rate_dt(pdev, "mout_aclk_fl1_550_cam_user");
fimc_is_get_rate_dt(pdev, "mout_aclk_432_cam_user");
fimc_is_get_rate_dt(pdev, "mout_aclk_333_432_gscl_user");
fimc_is_get_rate_dt(pdev, "mout_aclk_333_432_isp0_user");
fimc_is_get_rate_dt(pdev, "mout_aclk_333_432_isp_user");
fimc_is_get_rate_dt(pdev, "mout_aclk_400_isp_user");
fimc_is_get_rate_dt(pdev, "mout_aclk_266_isp_user");
fimc_is_get_rate_dt(pdev, "dout_mcuispdiv0");
fimc_is_get_rate_dt(pdev, "dout_mcuispdiv1");
fimc_is_get_rate_dt(pdev, "dout_ispdiv0");
fimc_is_get_rate_dt(pdev, "dout_ispdiv1");
fimc_is_get_rate_dt(pdev, "dout_ispdiv2");
fimc_is_get_rate_dt(pdev, "dout2_gscl_blk_333");
fimc_is_get_rate_dt(pdev, "dout2_cam_blk_432");
fimc_is_get_rate_dt(pdev, "dout2_cam_blk_550");
fimc_is_get_rate_dt(pdev, "dout_pwm_isp");
fimc_is_get_rate_dt(pdev, "dout_uart_isp");
fimc_is_get_rate_dt(pdev, "dout_spi0_isp_pre");
fimc_is_get_rate_dt(pdev, "dout_spi1_isp_pre");
/* CMU_TOP_DUMP */
pr_info("EXYNOS5_CLK_SRC_TOP0(0x%08X)\n", readl(EXYNOS5_CLK_SRC_TOP0));
pr_info("EXYNOS5_CLK_SRC_TOP1(0x%08X)\n", readl(EXYNOS5_CLK_SRC_TOP1));
pr_info("EXYNOS5_CLK_SRC_TOP3(0x%08X)\n", readl(EXYNOS5_CLK_SRC_TOP3));
pr_info("EXYNOS5_CLK_SRC_TOP4(0x%08X)\n", readl(EXYNOS5_CLK_SRC_TOP4));
pr_info("EXYNOS5_CLK_SRC_TOP8(0x%08X)\n", readl(EXYNOS5_CLK_SRC_TOP8));
pr_info("EXYNOS5_CLK_SRC_TOP9(0x%08X)\n", readl(EXYNOS5_CLK_SRC_TOP9));
pr_info("EXYNOS5_CLK_SRC_TOP11(0x%08X)\n", readl(EXYNOS5_CLK_SRC_TOP11));
pr_info("EXYNOS5_CLK_SRC_TOP13(0x%08X)\n", readl(EXYNOS5_CLK_SRC_TOP13));
pr_info("EXYNOS5_CLK_DIV_TOP0(0x%08X)\n", readl(EXYNOS5_CLK_DIV_TOP0));
pr_info("EXYNOS5_CLK_DIV_TOP1(0x%08X)\n", readl(EXYNOS5_CLK_DIV_TOP1));
pr_info("EXYNOS5_CLK_DIV_TOP8(0x%08X)\n", readl(EXYNOS5_CLK_DIV_TOP8));
return 0;
}
