Ejemplos de fixed_sdram en C++ (Cpp)

Ejemplo n.º 1

Archivo: mpc837xemds.c Proyecto: Digilent/u-boot-digilent

phys_size_t initdram(int board_type)
{
	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
	u32 msize = 0;

	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
		return -1;

#if defined(CONFIG_SPD_EEPROM)
	msize = spd_sdram();
#else
	msize = fixed_sdram();
#endif

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	/* Initialize DDR ECC byte */
	ddr_enable_ecc(msize * 1024 * 1024);
#endif

	/* return total bus DDR size(bytes) */
	return (msize * 1024 * 1024);
}

Ejemplo n.º 2

Archivo: km83xx.c Proyecto: AeroGirl/u-boot-kern3.2

phys_size_t initdram(int board_type)
{
	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
	u32 msize = 0;

	if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
		return -1;

	out_be32(&im->sysconf.ddrlaw[0].bar,
		CONFIG_SYS_DDR_BASE & LAWBAR_BAR);
	msize = fixed_sdram();

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	/*
	 * Initialize DDR ECC byte
	 */
	ddr_enable_ecc(msize * 1024 * 1024);
#endif

	/* return total bus SDRAM size(bytes)  -- DDR */
	return msize * 1024 * 1024;
}

Ejemplo n.º 3

Archivo: sdram.c Proyecto: Medvedroid/OT_903D-kernel-2.6.35.7

phys_size_t initdram(int board_type)
{
	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
	volatile fsl_lbus_t *lbc= &im->lbus;
	u32 msize;

	if ((__raw_readl(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32) im)
		return -1;

	/* DDR SDRAM - Main SODIMM */
	__raw_writel(CONFIG_SYS_DDR_BASE & LAWBAR_BAR, &im->sysconf.ddrlaw[0].bar);

	msize = fixed_sdram();

	/* Local Bus setup lbcr and mrtpr */
	__raw_writel(CONFIG_SYS_LBC_LBCR, &lbc->lbcr);
	__raw_writel(CONFIG_SYS_LBC_MRTPR, &lbc->mrtpr);
	sync();

	/* return total bus SDRAM size(bytes)  -- DDR */
	return (msize * 1024 * 1024);
}

Ejemplo n.º 4

Archivo: mpc837xerdb.c Proyecto: OpenNoah/u-boot

int dram_init(void)
{
	immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
	u32 msize = 0;

	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
		return -ENXIO;

#if defined(CONFIG_SPD_EEPROM)
	msize = spd_sdram();
#else
	msize = fixed_sdram();
#endif

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	/* Initialize DDR ECC byte */
	ddr_enable_ecc(msize * 1024 * 1024);
#endif
	/* return total bus DDR size(bytes) */
	gd->ram_size = msize * 1024 * 1024;

	return 0;
}

Ejemplo n.º 5

Archivo: ac14xx.c Proyecto: pallavides/AMP_Demo

phys_size_t initdram(int board_type)
{
    return fixed_sdram(NULL, sdram_init_seq, ARRAY_SIZE(sdram_init_seq));
}

Ejemplo n.º 6

Archivo: mpc8540eval.c Proyecto: Medvedroid/OT_903D-kernel-2.6.35.7

phys_size_t initdram (int board_type)
{
	long dram_size = 0;

#if !defined(CONFIG_RAM_AS_FLASH)
	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
	sys_info_t sysinfo;
	uint temp_lbcdll = 0;
#endif
#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#endif

#if defined(CONFIG_DDR_DLL)
	uint temp_ddrdll = 0;

	/* Work around to stabilize DDR DLL */
	temp_ddrdll = gur->ddrdllcr;
	gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
	asm("sync;isync;msync");
#endif

#if defined(CONFIG_SPD_EEPROM)
	dram_size = fsl_ddr_sdram();
	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
	dram_size *= 0x100000;
#else
	dram_size = fixed_sdram ();
#endif

#if defined(CONFIG_SYS_RAMBOOT)
	return dram_size;
#endif

#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */
	get_sys_info(&sysinfo);
	/* if localbus freq is less than 66MHz,we use bypass mode,otherwise use DLL */
	if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV) < 66000000) {
		lbc->lcrr = (CONFIG_SYS_LBC_LCRR & 0x0fffffff)| 0x80000000;
	} else {
		lbc->lcrr = CONFIG_SYS_LBC_LCRR & 0x7fffffff;
		udelay(200);
		temp_lbcdll = gur->lbcdllcr;
		gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
		asm("sync;isync;msync");
	}
	lbc->or2 = CONFIG_SYS_OR2_PRELIM; /* 64MB SDRAM */
	lbc->br2 = CONFIG_SYS_BR2_PRELIM;
	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
	asm("sync");
	* (ulong *)0 = 0x000000ff;
	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
	asm("sync");
	* (ulong *)0 = 0x000000ff;
	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3;
	asm("sync");
	* (ulong *)0 = 0x000000ff;
	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
	asm("sync");
	* (ulong *)0 = 0x000000ff;
	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5;
	asm("sync");
	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
	asm("sync");
	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
	asm("sync");
#endif

#if defined(CONFIG_DDR_ECC)
	{
		/* Initialize all of memory for ECC, then
		 * enable errors */
		volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);

		dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size);

		/* Enable errors for ECC */
		ddr->err_disable = 0x00000000;
		asm("sync;isync;msync");
	}
#endif

	return dram_size;
}

Ejemplo n.º 7

Archivo: mpc8540eval.c Proyecto: lalabu/u-boot-yaffs2mpc837xerdb

long int initdram (int board_type)
{
    long dram_size = 0;

#if !defined(CONFIG_RAM_AS_FLASH)
    volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
    sys_info_t sysinfo;
    uint temp_lbcdll = 0;
#endif
#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
    volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
#endif

#if defined(CONFIG_DDR_DLL)
    uint temp_ddrdll = 0;

    /* Work around to stabilize DDR DLL */
    temp_ddrdll = gur->ddrdllcr;
    gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
    asm("sync;isync;msync");
#endif

#if defined(CONFIG_SPD_EEPROM)
    dram_size = spd_sdram ();
#else
    dram_size = fixed_sdram ();
#endif

#if defined(CFG_RAMBOOT)
    return dram_size;
#endif

#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */
    get_sys_info(&sysinfo);
    /* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */
    if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) {
        lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000;
    } else {
        lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff;
        udelay(200);
        temp_lbcdll = gur->lbcdllcr;
        gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
        asm("sync;isync;msync");
    }
    lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */
    lbc->br2 = CFG_BR2_PRELIM;
    lbc->lbcr = CFG_LBC_LBCR;
    lbc->lsdmr = CFG_LBC_LSDMR_1;
    asm("sync");
    * (ulong *)0 = 0x000000ff;
    lbc->lsdmr = CFG_LBC_LSDMR_2;
    asm("sync");
    * (ulong *)0 = 0x000000ff;
    lbc->lsdmr = CFG_LBC_LSDMR_3;
    asm("sync");
    * (ulong *)0 = 0x000000ff;
    lbc->lsdmr = CFG_LBC_LSDMR_4;
    asm("sync");
    * (ulong *)0 = 0x000000ff;
    lbc->lsdmr = CFG_LBC_LSDMR_5;
    asm("sync");
    lbc->lsrt = CFG_LBC_LSRT;
    asm("sync");
    lbc->mrtpr = CFG_LBC_MRTPR;
    asm("sync");
#endif

#if defined(CONFIG_DDR_ECC)
    {
        /* Initialize all of memory for ECC, then
         * enable errors */
        uint *p = 0;
        uint i = 0;
        volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
        dma_init();
        for (*p = 0; p < (uint *)(8 * 1024); p++) {
            if (((unsigned int)p & 0x1f) == 0) {
                dcbz(p);
            }
            *p = (unsigned int)0xdeadbeef;
            if (((unsigned int)p & 0x1c) == 0x1c) {
                dcbf(p);
            }
        }

        /* 8K */
        dma_xfer((uint *)0x2000,0x2000,(uint *)0);
        /* 16K */
        dma_xfer((uint *)0x4000,0x4000,(uint *)0);
        /* 32K */
        dma_xfer((uint *)0x8000,0x8000,(uint *)0);
        /* 64K */
        dma_xfer((uint *)0x10000,0x10000,(uint *)0);
        /* 128k */
        dma_xfer((uint *)0x20000,0x20000,(uint *)0);
        /* 256k */
        dma_xfer((uint *)0x40000,0x40000,(uint *)0);
        /* 512k */
        dma_xfer((uint *)0x80000,0x80000,(uint *)0);
        /* 1M */
        dma_xfer((uint *)0x100000,0x100000,(uint *)0);
        /* 2M */
        dma_xfer((uint *)0x200000,0x200000,(uint *)0);
        /* 4M */
        dma_xfer((uint *)0x400000,0x400000,(uint *)0);

        for (i = 1; i < dram_size / 0x800000; i++) {
            dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0);
        }

        /* Enable errors for ECC */
        ddr->err_disable = 0x00000000;
        asm("sync;isync;msync");
    }
#endif

    return dram_size;
}

Ejemplo n.º 8

Archivo: aria.c Proyecto: 0xFelix/u-boot-edminiv2

phys_size_t initdram (int board_type)
{
	return fixed_sdram(NULL, NULL, 0);
}

Ejemplo n.º 9

Archivo: mpc5121ads.c Proyecto: 01hyang/u-boot

phys_size_t initdram(int board_type)
{
	u32 msize = 0;
	/*
	 * Elpida MDDRC and initialization settings are an alternative
	 * to the Default Micron ones for all but the earliest Rev 4 boards
	 */
	ddr512x_config_t elpida_mddrc_config = {
		.ddr_sys_config   = CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA,
		.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0,
		.ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA,
		.ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA,
	};

	u32 elpida_init_sequence[] = {
		CONFIG_SYS_DDRCMD_NOP,
		CONFIG_SYS_DDRCMD_NOP,
		CONFIG_SYS_DDRCMD_NOP,
		CONFIG_SYS_DDRCMD_NOP,
		CONFIG_SYS_DDRCMD_NOP,
		CONFIG_SYS_DDRCMD_NOP,
		CONFIG_SYS_DDRCMD_NOP,
		CONFIG_SYS_DDRCMD_NOP,
		CONFIG_SYS_DDRCMD_NOP,
		CONFIG_SYS_DDRCMD_NOP,
		CONFIG_SYS_DDRCMD_PCHG_ALL,
		CONFIG_SYS_DDRCMD_NOP,
		CONFIG_SYS_DDRCMD_RFSH,
		CONFIG_SYS_DDRCMD_NOP,
		CONFIG_SYS_DDRCMD_RFSH,
		CONFIG_SYS_DDRCMD_NOP,
		CONFIG_SYS_DDRCMD_EM2,
		CONFIG_SYS_DDRCMD_EM3,
		CONFIG_SYS_DDRCMD_EN_DLL,
		CONFIG_SYS_ELPIDA_RES_DLL,
		CONFIG_SYS_DDRCMD_PCHG_ALL,
		CONFIG_SYS_DDRCMD_RFSH,
		CONFIG_SYS_DDRCMD_RFSH,
		CONFIG_SYS_DDRCMD_RFSH,
		CONFIG_SYS_ELPIDA_INIT_DEV_OP,
		CONFIG_SYS_DDRCMD_NOP,
		CONFIG_SYS_DDRCMD_NOP,
		CONFIG_SYS_DDRCMD_NOP,
		CONFIG_SYS_DDRCMD_NOP,
		CONFIG_SYS_DDRCMD_NOP,
		CONFIG_SYS_DDRCMD_NOP,
		CONFIG_SYS_DDRCMD_NOP,
		CONFIG_SYS_DDRCMD_NOP,
		CONFIG_SYS_DDRCMD_NOP,
		CONFIG_SYS_DDRCMD_NOP,
		CONFIG_SYS_DDRCMD_OCD_DEFAULT,
		CONFIG_SYS_ELPIDA_OCD_EXIT,
		CONFIG_SYS_DDRCMD_NOP,
		CONFIG_SYS_DDRCMD_NOP,
		CONFIG_SYS_DDRCMD_NOP,
		CONFIG_SYS_DDRCMD_NOP,
		CONFIG_SYS_DDRCMD_NOP,
		CONFIG_SYS_DDRCMD_NOP,
		CONFIG_SYS_DDRCMD_NOP,
		CONFIG_SYS_DDRCMD_NOP,
		CONFIG_SYS_DDRCMD_NOP,
		CONFIG_SYS_DDRCMD_NOP
	};

	if (is_micron()) {
		msize = fixed_sdram(NULL, NULL, 0);
	} else {
		msize = fixed_sdram(&elpida_mddrc_config,
				elpida_init_sequence,
				sizeof(elpida_init_sequence)/sizeof(u32));
	}

	return msize;
}