Ejemplo n.º 1
0
/* store 0xa000-0xbfff */
void REGPARM2 vic_fp_blk5_store(WORD addr, BYTE value)
{
    if (CART_CFG_BLK5_WP) {
    } else if (ram5_flop) {
        cart_ram[addr & 0x1fff] = value;
    } else {
        flash040core_store(&flash_state, (addr & 0x1fff) | (cart_rom_bank << 13), value);
    }
}
Ejemplo n.º 2
0
/* store 0x9800-0x9bff */
static void vic_um_io2_store(WORD addr, BYTE value)
{
    switch (CART_CFG_IO(2)) {
    case BLK_STATE_DISABLED:
    case BLK_STATE_RAM_RO:
        break;
    case BLK_STATE_ROM:
        flash040core_store(&flash_state,
                           ((addr | 0x1800) + CART_IO_ADDR) &
                           (cart_rom_size - 1),
                           value);
        break;
    case BLK_STATE_RAM_RW:
        cart_ram[((addr | 0x1800) + CART_IO_ADDR) & (cart_ram_size - 1)] =
            value;
    }
}
Ejemplo n.º 3
0
/* store 0xa000-0xbfff */
void vic_um_blk5_store(WORD addr, BYTE value)
{
    switch (CART_CFG_BLK(4)) {
    case BLK_STATE_DISABLED:
    case BLK_STATE_RAM_RO:
        break;
    case BLK_STATE_ROM:
        flash040core_store(&flash_state,
                           ((addr & 0x1fff) + CART_BLK_ADDR(4)) &
                           (cart_rom_size - 1),
                           value);
        break;
    case BLK_STATE_RAM_RW:
        cart_ram[((addr & 0x1fff) + CART_BLK_ADDR(4)) & (cart_ram_size - 1)] =
            value;
    }
}
Ejemplo n.º 4
0
void easyflash_romh_store(WORD addr, BYTE value)
{
    flash040core_store(easyflash_state_high, (easyflash_register_00 * 0x2000) + (addr & 0x1fff), value);
}
Ejemplo n.º 5
0
static void internal_store(WORD addr, BYTE value, int blk, WORD base, int sel)
{
    BYTE mode;
    int bank;
    unsigned int faddr;

    mode = register_a & REGA_MODE_MASK;

    /* Determine which bank to access */
    switch (mode) {
        case MODE_FLASH:
        case MODE_SUPER_RAM:
            bank = register_a & REGA_BANK_MASK;
            break;
        case MODE_SUPER_ROM:
#ifdef FE3_2_SUPER_ROM_BUG
            bank = 1 | (register_a & REGA_BANK_MASK);
            break;
#endif
        case MODE_START:
            bank = 1;
            break;
        case MODE_ROM_RAM:
        case MODE_RAM1:
            if (sel) {
                bank = 2;
            } else {
                bank = 1;
            }
            break;
        case MODE_RAM2:
            bank = 1;
            break;
        default:
            bank = 0;
            break;
    }

    /* Calculate Address */
    faddr = calc_addr(addr, bank, base);

    /* Perform access */
    switch (mode) {
        case MODE_FLASH:
            flash040core_store(&flash_state, faddr, value);
            break;
        case MODE_ROM_RAM:
            if (sel) {
                cart_ram[faddr] = value;
            }
            break;
        case MODE_START:
        case MODE_RAM1:
        case MODE_RAM2:
        case MODE_SUPER_ROM:
        case MODE_SUPER_RAM:
            cart_ram[faddr] = value;
            break;
        default:
            break;
    }
}