void free(void *ptr)
{
pthread_mutex_lock(&g_mutex);
free_exec(ptr);
pthread_mutex_unlock(&g_mutex);
}
void gen_interupt()
{
if (stop == 1)
{
vi_counter = 0; // debug
dyna_stop();
}
if (savestates_job & LOADSTATE)
{
savestates_load();
savestates_job &= ~LOADSTATE;
return;
}
if (skip_jump)
{
if (q->count > Count || (Count - q->count) < 0x80000000)
next_interupt = q->count;
else
next_interupt = 0;
if (r4300emu == CORE_PURE_INTERPRETER)
{
interp_addr = skip_jump;
last_addr = interp_addr;
}
else
{
unsigned int dest = skip_jump;
skip_jump=0;
jump_to(dest);
last_addr = PC->addr;
}
skip_jump=0;
return;
}
switch(q->type)
{
case SPECIAL_INT:
if (Count > 0x10000000) return;
remove_interupt_event();
add_interupt_event_count(SPECIAL_INT, 0);
return;
break;
case VI_INT:
if(vi_counter < 60)
{
if (vi_counter == 0)
cheat_apply_cheats(ENTRY_BOOT);
vi_counter++;
}
else
{
cheat_apply_cheats(ENTRY_VI);
}
updateScreen();
#ifdef WITH_LIRC
lircCheckInput();
#endif
SDL_PumpEvents();
refresh_stat();
// if paused, poll for input events
if(rompause)
{
#ifdef WITH_OSD
osd_render(); // draw Paused message in case updateScreen didn't do it
SDL_GL_SwapBuffers();
#endif
while(rompause)
{
SDL_Delay(10);
SDL_PumpEvents();
#ifdef WITH_LIRC
lircCheckInput();
#endif //WITH_LIRC
}
}
new_vi();
if (vi_register.vi_v_sync == 0) vi_register.vi_delay = 500000;
else vi_register.vi_delay = ((vi_register.vi_v_sync + 1)*1500);
next_vi += vi_register.vi_delay;
if (vi_register.vi_status&0x40) vi_field=1-vi_field;
else vi_field=0;
remove_interupt_event();
add_interupt_event_count(VI_INT, next_vi);
MI_register.mi_intr_reg |= 0x08;
if (MI_register.mi_intr_reg & MI_register.mi_intr_mask_reg)
Cause = (Cause | 0x400) & 0xFFFFFF83;
else
return;
if ((Status & 7) != 1) return;
if (!(Status & Cause & 0xFF00)) return;
break;
case COMPARE_INT:
remove_interupt_event();
Count+=2;
add_interupt_event_count(COMPARE_INT, Compare);
Count-=2;
Cause = (Cause | 0x8000) & 0xFFFFFF83;
if ((Status & 7) != 1) return;
if (!(Status & Cause & 0xFF00)) return;
break;
case CHECK_INT:
remove_interupt_event();
break;
case SI_INT:
#ifdef WITH_LIRC
lircCheckInput();
#endif //WITH_LIRC
SDL_PumpEvents();
PIF_RAMb[0x3F] = 0x0;
remove_interupt_event();
MI_register.mi_intr_reg |= 0x02;
si_register.si_stat |= 0x1000;
if (MI_register.mi_intr_reg & MI_register.mi_intr_mask_reg)
Cause = (Cause | 0x400) & 0xFFFFFF83;
else
return;
if ((Status & 7) != 1) return;
if (!(Status & Cause & 0xFF00)) return;
break;
case PI_INT:
remove_interupt_event();
MI_register.mi_intr_reg |= 0x10;
pi_register.read_pi_status_reg &= ~3;
if (MI_register.mi_intr_reg & MI_register.mi_intr_mask_reg)
Cause = (Cause | 0x400) & 0xFFFFFF83;
else
return;
if ((Status & 7) != 1) return;
if (!(Status & Cause & 0xFF00)) return;
break;
case AI_INT:
if (ai_register.ai_status & 0x80000000) // full
{
unsigned int ai_event = get_event(AI_INT);
remove_interupt_event();
ai_register.ai_status &= ~0x80000000;
ai_register.current_delay = ai_register.next_delay;
ai_register.current_len = ai_register.next_len;
add_interupt_event_count(AI_INT, ai_event+ai_register.next_delay);
MI_register.mi_intr_reg |= 0x04;
if (MI_register.mi_intr_reg & MI_register.mi_intr_mask_reg)
Cause = (Cause | 0x400) & 0xFFFFFF83;
else
return;
if ((Status & 7) != 1) return;
if (!(Status & Cause & 0xFF00)) return;
}
else
{
remove_interupt_event();
ai_register.ai_status &= ~0x40000000;
//-------
MI_register.mi_intr_reg |= 0x04;
if (MI_register.mi_intr_reg & MI_register.mi_intr_mask_reg)
Cause = (Cause | 0x400) & 0xFFFFFF83;
else
return;
if ((Status & 7) != 1) return;
if (!(Status & Cause & 0xFF00)) return;
}
break;
case SP_INT:
remove_interupt_event();
sp_register.sp_status_reg |= 0x303;
//sp_register.signal1 = 1;
sp_register.signal2 = 1;
sp_register.broke = 1;
sp_register.halt = 1;
if (!sp_register.intr_break) return;
MI_register.mi_intr_reg |= 0x01;
if (MI_register.mi_intr_reg & MI_register.mi_intr_mask_reg)
Cause = (Cause | 0x400) & 0xFFFFFF83;
else
return;
if ((Status & 7) != 1) return;
if (!(Status & Cause & 0xFF00)) return;
break;
case DP_INT:
remove_interupt_event();
dpc_register.dpc_status &= ~2;
dpc_register.dpc_status |= 0x81;
MI_register.mi_intr_reg |= 0x20;
if (MI_register.mi_intr_reg & MI_register.mi_intr_mask_reg)
Cause = (Cause | 0x400) & 0xFFFFFF83;
else
return;
if ((Status & 7) != 1) return;
if (!(Status & Cause & 0xFF00)) return;
break;
case HW2_INT:
// Hardware Interrupt 2 -- remove interrupt event from queue
remove_interupt_event();
// setup r4300 Status flags: reset TS, and SR, set IM2
Status = (Status & ~0x00380000) | 0x1000;
Cause = (Cause | 0x1000) & 0xFFFFFF83;
/* the exception_general() call below will jump to the interrupt vector (0x80000180) and setup the
* interpreter or dynarec
*/
break;
case NMI_INT:
// Non Maskable Interrupt -- remove interrupt event from queue
remove_interupt_event();
// setup r4300 Status flags: reset TS and SR, set BEV, ERL, and SR
Status = (Status & ~0x00380000) | 0x00500004;
Cause = 0x00000000;
// simulate the soft reset code which would run from the PIF ROM
r4300_reset_soft();
// clear all interrupts, reset interrupt counters back to 0
Count = 0;
vi_counter = 0;
init_interupt();
// clear the audio status register so that subsequent write_ai() calls will work properly
ai_register.ai_status = 0;
// reset the r4300 internal state
if (r4300emu == CORE_PURE_INTERPRETER) /* pure interpreter only */
{
// set ErrorEPC with last instruction address and set next instruction address to reset vector
ErrorEPC = interp_addr;
interp_addr = 0xa4000040;
last_addr = interp_addr;
}
else /* decode-cached interpreter or dynamic recompiler */
{
int i;
// clear all the compiled instruction blocks
for (i=0; i<0x100000; i++)
{
if (blocks[i])
{
if (blocks[i]->block) { free_exec(blocks[i]->block); blocks[i]->block = NULL; }
if (blocks[i]->code) { free_exec(blocks[i]->code); blocks[i]->code = NULL; }
if (blocks[i]->jumps_table) { free(blocks[i]->jumps_table); blocks[i]->jumps_table = NULL; }
if (blocks[i]->riprel_table) { free(blocks[i]->riprel_table); blocks[i]->riprel_table = NULL; }
free(blocks[i]);
blocks[i] = NULL;
}
}
// re-initialize
init_blocks();
// jump to the start
ErrorEPC = PC->addr;
jump_to(0xa4000040);
last_addr = PC->addr;
}
// adjust ErrorEPC if we were in a delay slot, and clear the delay_slot and dyna_interp flags
if(delay_slot==1 || delay_slot==3)
{
ErrorEPC-=4;
}
delay_slot = 0;
dyna_interp = 0;
return;
default:
remove_interupt_event();
break;
}
#ifdef NEW_DYNAREC
EPC = pcaddr;
pcaddr = 0x80000180;
Status |= 2;
Cause &= 0x7FFFFFFF;
pending_exception=1;
#else
exception_general();
#endif
if(savestates_job & SAVESTATE)
{
if(savestates_job & SAVEPJ64STATE)
{
if(savestates_save_pj64() != -1)
{
savestates_job &= ~(SAVESTATE+SAVEPJ64STATE);
}
}
else
{
savestates_save();
savestates_job &= ~SAVESTATE;
}
}
}
