void dfll_enable_closed_loop(const struct dfll_config *cfg,
unsigned int dfll_id)
{
irqflags_t flags;
/* Enable the reference clock */
genclk_enable(&cfg->ref_cfg, 0);
/*
* Enable the DFLL first, but don't wait for the DFLL0RDY bit
* because if the DFLL has been disabled before, the DFLL0RDY
* bit stays cleared until it is re-enabled.
*/
flags = cpu_irq_save();
AVR32_SCIF.unlock =
( AVR32_SCIF_UNLOCK_KEY_VALUE << AVR32_SCIF_UNLOCK_KEY_OFFSET ) |
AVR32_SCIF_DFLL0CONF;
AVR32_SCIF.dfll0conf = 1U << AVR32_SCIF_DFLL0CONF_EN;
cpu_irq_restore(flags);
/*
* Then, configure the DFLL, taking care to wait for the
* DFLL0RDY bit before every step.
*/
dfll_write_reg(DFLL0STEP, cfg->step);
#if AVR32_SCIF_H_VERSION < 110
dfll_write_reg(DFLL0FMUL, cfg->mul);
#else
dfll_write_reg(DFLL0MUL, cfg->mul);
#endif
dfll_write_reg(DFLL0SSG, cfg->ssg);
dfll_write_reg(DFLL0CONF, cfg->conf | (1U << AVR32_SCIF_DFLL0CONF_EN));
}
void dfll_enable_closed_loop(const struct dfll_config *cfg, uint32_t dfll_id)
{
irqflags_t flags;
UNUSED(dfll_id);
/* Enable the reference clock */
genclk_enable(&cfg->ref_cfg, 0);
/*
* Enable the DFLL first, but don't wait for the DFLL0RDY bit
* because if the DFLL has been disabled before, the DFLL0RDY
* bit stays cleared until it is re-enabled.
*/
flags = cpu_irq_save();
SCIF->SCIF_UNLOCK = SCIF_UNLOCK_KEY(0xAAUL)
| SCIF_UNLOCK_ADDR((uint32_t)&SCIF->SCIF_DFLL0CONF - (uint32_t)SCIF);
SCIF->SCIF_DFLL0CONF = SCIF_DFLL0CONF_EN;
cpu_irq_restore(flags);
/*
* Then, configure the DFLL, taking care to wait for the
* DFLL0RDY bit before every step.
*/
dfll_write_reg(DFLL0STEP, cfg->step);
dfll_write_reg(DFLL0MUL, cfg->mul);
dfll_write_reg(DFLL0SSG, cfg->ssg);
dfll_write_reg(DFLL0CONF, cfg->conf | SCIF_DFLL0CONF_EN);
}
/**
* \brief Test Generic clock
*
* This test enables the generic clock, sets its source and
* division factor, and then check if it's set correctly.
*
* \param test Current test case.
*/
static void run_generic_clock_test(const struct test_case *test)
{
struct genclk_config gencfg;
bool status;
genclk_config_defaults(&gencfg, CONFIG_GENERIC_ID);
genclk_config_set_source(&gencfg, CONFIG_GENERIC_SRC);
genclk_config_set_divider(&gencfg, CONFIG_GENERIC_DIV);
genclk_enable(&gencfg, CONFIG_GENERIC_ID);
status = (CONFIG_GENERIC_CLOCK == get_generic_clock());
test_assert_true(test, status, "Generic clock set fail");
}
/**
* \brief Enable the GLOC module.
*
* \param dev_inst Device structure pointer.
*
*/
void gloc_enable(struct gloc_dev_inst *const dev_inst)
{
struct genclk_config gencfg;
sysclk_enable_peripheral_clock(dev_inst->hw_dev);
sleepmgr_lock_mode(SLEEPMGR_SLEEP_0);
genclk_config_defaults(&gencfg, GLOC_GCLK_NUM);
genclk_enable_source(CONFIG_GLOC_GENCLK_SRC);
genclk_config_set_source(&gencfg, CONFIG_GLOC_GENCLK_SRC);
genclk_config_set_divider(&gencfg, CONFIG_GLOC_GENCLK_DIV);
genclk_enable(&gencfg, GLOC_GCLK_NUM);
}
/**
* \brief Enable the AES.
*
* \param dev_inst Device structure pointer.
*
*/
void aes_enable(struct aes_dev_inst *const dev_inst)
{
struct genclk_config gencfg;
sysclk_enable_peripheral_clock(dev_inst->hw_dev);
sleepmgr_lock_mode(SLEEPMGR_SLEEP_0);
dev_inst->hw_dev->AESA_CTRL = AESA_CTRL_ENABLE;
genclk_config_defaults(&gencfg, AESA_GCLK_NUM);
genclk_enable_source(CONFIG_AESA_GENERIC_SRC);
genclk_config_set_source(&gencfg, CONFIG_AESA_GENERIC_SRC);
genclk_config_set_divider(&gencfg, CONFIG_AESA_GENERIC_DIV);
genclk_enable(&gencfg, AESA_GCLK_NUM);
}
///< Enable/Disable the clock to the ADC
void ads1274_ADC_switch_clock(bool on_off)
{
if (on_off == true)
{
gpio_enable_module_pin(AVR32_SCIF_GCLK_1_1_PIN, AVR32_SCIF_GCLK_1_1_FUNCTION);
gpio_configure_pin(ADC_CLKDIV,GPIO_DIR_OUTPUT | GPIO_INIT_HIGH);
//scif_gc_setup(AVR32_SCIF_GCLK_GCLK0PIN, SCIF_GCCTRL_CPUCLOCK, 1, 1);
//scif_gc_enable(AVR32_SCIF_GCLK_GCLK0PIN);
genclk_config_defaults(&gcfg, AVR32_SCIF_GCLK_GCLK1PIN);
genclk_config_set_source(&gcfg, GENCLK_SRC_PLL1);
genclk_config_set_divider(&gcfg, 2);
genclk_enable(&gcfg, AVR32_SCIF_GCLK_GCLK1PIN);
}
else
{
genclk_disable(AVR32_SCIF_GCLK_GCLK1PIN);
}
}
/**
* \brief Initialize the clock system and output the CPU clock on pin
* PCK0 (please refer to datasheet for PIN number).
*
* \return Unused (ANSI-C compatibility).
*/
int main(void)
{
struct genclk_config gcfg;
sysclk_init();
board_init();
/* Configure specific CLKOUT pin */
ioport_set_pin_mode(GCLK_PIN, GCLK_PIN_MUX);
ioport_disable_pin(GCLK_PIN);
/* Configure the output clock */
genclk_config_defaults(&gcfg, GCLK_ID);
genclk_config_set_source(&gcfg, GCLK_SOURCE);
genclk_config_set_divider(&gcfg, GCLK_DIV);
genclk_enable(&gcfg, GCLK_ID);
while (1) {
/* Do nothing */
}
}
/**
* \brief Switch between various system clock sources and prescalers at
* run time.
*
* \return Unused (ANSI-C compatibility).
*/
int main(void)
{
struct genclk_config gcfg;
sysclk_init();
board_init();
/* Setup SysTick Timer for 1 msec interrupts */
if (SysTick_Config(SystemCoreClock / 1000)) {
while (1); // Capture error
}
/* Enable PIO module related clock */
sysclk_enable_peripheral_clock(PIN_PUSHBUTTON_1_ID);
/* Configure specific CLKOUT pin */
ioport_set_pin_mode(GCLK_PIN, GCLK_PIN_MUX);
ioport_disable_pin(GCLK_PIN);
/* Configure the output clock source and frequency */
genclk_config_defaults(&gcfg, GCLK_ID);
genclk_config_set_source(&gcfg, GENCLK_PCK_SRC_PLLACK);
genclk_config_set_divider(&gcfg, GENCLK_PCK_PRES_1);
genclk_enable(&gcfg, GCLK_ID);
while (1) {
/*
* Initial state.
*/
wait_for_switches();
/*
* Divide MCK frequency by 2.
*/
sysclk_set_prescalers(SYSCLK_PRES_2);
genclk_config_set_divider(&gcfg, GENCLK_PCK_PRES_2);
genclk_enable(&gcfg, GCLK_ID);
wait_for_switches();
#ifdef BOARD_NO_32K_XTAL
/*
* Switch to the slow clock with all prescalers disabled.
*/
sysclk_set_source(SYSCLK_SRC_SLCK_RC);
sysclk_set_prescalers(SYSCLK_PRES_1);
genclk_config_set_source(&gcfg, GENCLK_PCK_SRC_SLCK_RC);
genclk_config_set_divider(&gcfg, GENCLK_PCK_PRES_1);
genclk_enable(&gcfg, GCLK_ID);
osc_disable(OSC_MAINCK_XTAL);
wait_for_switches();
#endif
/*
* Switch to internal 8 MHz RC.
*/
/* Switch to slow clock before switch main clock */
sysclk_set_source(SYSCLK_SRC_SLCK_RC);
osc_enable(OSC_MAINCK_8M_RC);
osc_wait_ready(OSC_MAINCK_8M_RC);
sysclk_set_source(SYSCLK_SRC_MAINCK_8M_RC);
genclk_config_set_source(&gcfg, GENCLK_PCK_SRC_MAINCK_8M_RC);
genclk_enable(&gcfg, GCLK_ID);
wait_for_switches();
#if BOARD_FREQ_MAINCK_XTAL
/*
* Switch to external crystal (8MHz or 12MHz, depend on the board).
*/
osc_enable(OSC_MAINCK_XTAL);
osc_wait_ready(OSC_MAINCK_XTAL);
sysclk_set_source(SYSCLK_SRC_MAINCK_XTAL);
genclk_config_set_source(&gcfg, GENCLK_PCK_SRC_MAINCK_XTAL);
genclk_enable(&gcfg, GCLK_ID);
osc_disable(OSC_MAINCK_8M_RC);
wait_for_switches();
#endif
/*
* Go back to the initial state and start over.
*/
sysclk_init();
genclk_config_set_source(&gcfg, GENCLK_PCK_SRC_PLLACK);
genclk_config_set_divider(&gcfg, GENCLK_PCK_PRES_1);
genclk_enable(&gcfg, GCLK_ID);
}
}
/**
* \brief Test audio data transfer and receive.
*
* \param test Current test case.
*/
static void run_iis_test(const struct test_case *test)
{
uint32_t i;
struct iis_config config;
struct iis_dev_inst dev_inst;
struct genclk_config gencfg;
struct pll_config pcfg;
/* Set the GCLK according to the sample rate */
genclk_config_defaults(&gencfg, IISC_GCLK_NUM);
/* CPUCLK 48M */
pll_config_init(&pcfg, PLL_SRC_OSC0, 2, 96000000 /
BOARD_OSC0_HZ);
pll_enable(&pcfg, 0);
sysclk_set_prescalers(0, 0, 0, 0, 0);
pll_wait_for_lock(0);
sysclk_set_source(SYSCLK_SRC_PLL0);
/* GCLK according fs ratio */
genclk_enable_source(GENCLK_SRC_CLK_CPU);
genclk_config_set_source(&gencfg, GENCLK_SRC_CLK_CPU);
genclk_config_set_divider(&gencfg, 4);
genclk_enable(&gencfg, IISC_GCLK_NUM);
/* Set the configuration */
iis_get_config_defaults(&config);
config.data_format = IIS_DATE_16BIT_COMPACT;
config.slot_length = IIS_SLOT_LENGTH_16BIT;
config.fs_ratio = IIS_FS_RATE_256;
config.tx_channels = IIS_CHANNEL_STEREO;
config.rx_channels = IIS_CHANNEL_STEREO;
config.tx_dma = IIS_ONE_DMA_CHANNEL_FOR_BOTH_CHANNELS;
config.rx_dma = IIS_ONE_DMA_CHANNEL_FOR_BOTH_CHANNELS;
config.loopback = true;
iis_init(&dev_inst, IISC, &config);
/* Enable the IIS module. */
iis_enable(&dev_inst);
/* Config PDCA module */
pdca_enable(PDCA);
pdca_channel_set_config(PDCA_IISC_CHANNEL0, &pdca_iisc_config_tx);
pdca_channel_set_config(PDCA_IISC_CHANNEL1, &pdca_iisc_config_rx);
pdca_channel_write_load(PDCA_IISC_CHANNEL0,
(void *)output_samples, SOUND_SAMPLES / 2);
pdca_channel_write_load(PDCA_IISC_CHANNEL1,
(void *)input_samples, SOUND_SAMPLES / 2);
pdca_channel_enable(PDCA_IISC_CHANNEL0);
pdca_channel_enable(PDCA_IISC_CHANNEL1);
/* Enable the functions */
iis_enable_transmission(&dev_inst);
iis_enable_clocks(&dev_inst);
/**
* Since the transfer and receive timing is not under control, we
* need adjust here the enable sequence and add some delay
* functions if it's needed.
*/
delay_us(20);
iis_enable_reception(&dev_inst);
while (!(pdca_get_channel_status(PDCA_IISC_CHANNEL1)
== PDCA_CH_TRANSFER_COMPLETED)) {
}
/* Disable the PDCA module. */
pdca_channel_disable(PDCA_IISC_CHANNEL0);
pdca_channel_disable(PDCA_IISC_CHANNEL1);
pdca_disable(PDCA);
/* Disable the IISC module. */
iis_disable(&dev_inst);
for (i = 0; i < SOUND_SAMPLES; i++) {
if (input_samples[i] != output_samples[i]) {
flag = false;
}
}
test_assert_true(test, flag == true, "Audio data did not match!");
}
