void __dead2 sq_system_off(void)
{
volatile uint32_t *gpio = (uint32_t *)PLAT_SQ_GPIO_BASE;
/* set PD[9] high to power off the system */
gpio[5] |= 0x2; /* set output */
gpio[1] |= 0x2; /* set high */
dmbst();
generic_delay_timer_init();
mdelay(1);
while (1) {
gpio[1] &= ~0x2; /* set low */
dmbst();
mdelay(1);
gpio[1] |= 0x2; /* set high */
dmbst();
mdelay(100);
}
wfi();
ERROR("SQ System Off: operation not handled.\n");
panic();
}
void arm_bl2u_early_platform_setup(struct meminfo *mem_layout, void *plat_info)
{
/* Initialize the console to provide early debug support */
arm_console_boot_init();
generic_delay_timer_init();
}
void bl31_platform_setup(void)
{
const char *soc_name;
uint16_t soc_id = sunxi_read_soc_id();
void *fdt;
switch (soc_id) {
case SUNXI_SOC_A64:
soc_name = "A64/H64/R18";
break;
case SUNXI_SOC_H5:
soc_name = "H5";
break;
case SUNXI_SOC_H6:
soc_name = "H6";
break;
default:
soc_name = "unknown";
break;
}
NOTICE("BL31: Detected Allwinner %s SoC (%04x)\n", soc_name, soc_id);
generic_delay_timer_init();
fdt = sunxi_find_dtb();
if (fdt) {
const char *model;
int length;
model = fdt_getprop(fdt, 0, "model", &length);
NOTICE("BL31: Found U-Boot DTB at %p, model: %s\n", fdt,
model ?: "unknown");
} else {
/*
* Perform any BL1 specific platform actions.
*/
void bl1_early_platform_setup(void)
{
const size_t bl1_size = BL1_RAM_LIMIT - BL1_RAM_BASE;
unsigned int id, uart_base;
generic_delay_timer_init();
hikey960_read_boardid(&id);
if (id == 5300)
uart_base = PL011_UART5_BASE;
else
uart_base = PL011_UART6_BASE;
/* Initialize the console to provide early debug support */
console_init(uart_base, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE);
/* Allow BL1 to see the whole Trusted RAM */
bl1_tzram_layout.total_base = BL1_RW_BASE;
bl1_tzram_layout.total_size = BL1_RW_SIZE;
/* Calculate how much RAM BL1 is using and how much remains free */
bl1_tzram_layout.free_base = BL1_RW_BASE;
bl1_tzram_layout.free_size = BL1_RW_SIZE;
reserve_mem(&bl1_tzram_layout.free_base,
&bl1_tzram_layout.free_size,
BL1_RAM_BASE,
bl1_size);
INFO("BL1: 0x%lx - 0x%lx [size = %lu]\n", BL1_RAM_BASE, BL1_RAM_LIMIT,
bl1_size);
}
/*******************************************************************************
* Perform any BL3-1 platform setup code
******************************************************************************/
void bl31_platform_setup(void)
{
generic_delay_timer_init();
plat_rockchip_soc_init();
/* Initialize the gic cpu and distributor interfaces */
plat_rockchip_gic_driver_init();
plat_rockchip_gic_init();
plat_rockchip_pmu_init();
}
void bl31_platform_setup(void)
{
generic_delay_timer_init();
/* select the CKIL source to 32K OSC */
mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1);
plat_gic_driver_init();
plat_gic_init();
imx_gpc_init();
}
void bl1_platform_setup(void)
{
int i;
generic_delay_timer_init();
pl061_gpio_init();
for (i = 0; i < GPIO_MAX; i++)
pl061_gpio_register(GPIO_BASE(i), i);
plat_io_setup();
}
void bl31_platform_setup(void)
{
platform_setup_cpu();
generic_delay_timer_init();
plat_mt_gic_driver_init();
/* Initialize the gic cpu and distributor interfaces */
plat_mt_gic_init();
/* Topologies are best known to the platform. */
mt_setup_topology();
}
void bl2_early_platform_setup(meminfo_t *mem_layout)
{
unsigned int id, uart_base;
generic_delay_timer_init();
hikey960_read_boardid(&id);
if (id == 5300)
uart_base = PL011_UART5_BASE;
else
uart_base = PL011_UART6_BASE;
/* Initialize the console to provide early debug support */
console_init(uart_base, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE);
/* Setup the BL2 memory layout */
bl2_tzram_layout = *mem_layout;
}
void bl2_platform_setup(void)
{
arm_bl2_platform_setup();
#ifdef FVP_VE_USE_SP804_TIMER
/*
* Enable the clock override for SP804 timer 0, which means that no
* clock dividers are applied and the raw (35 MHz) clock will be used
*/
mmio_write_32(V2M_SP810_BASE, FVP_SP810_CTRL_TIM0_OV);
/* Initialize delay timer driver using SP804 dual timer 0 */
sp804_timer_init(V2M_SP804_TIMER0_BASE,
SP804_TIMER_CLKMULT, SP804_TIMER_CLKDIV);
#else
generic_delay_timer_init();
#endif /* FVP_VE_USE_SP804_TIMER */
}
/*******************************************************************************
* Perform any BL3-1 platform setup code
******************************************************************************/
void bl31_platform_setup(void)
{
platform_setup_cpu();
platform_setup_sram();
generic_delay_timer_init();
/* Initialize the gic cpu and distributor interfaces */
plat_arm_gic_driver_init();
plat_arm_gic_init();
#if ENABLE_PLAT_COMPAT
/* Topologies are best known to the platform. */
mt_setup_topology();
#endif
/* Initialize spm at boot time */
spm_boot_init();
}
/*
* Perform any BL1 specific platform actions.
*/
void bl1_early_platform_setup(void)
{
unsigned int id, uart_base;
generic_delay_timer_init();
hikey960_read_boardid(&id);
if (id == 5300)
uart_base = PL011_UART5_BASE;
else
uart_base = PL011_UART6_BASE;
/* Initialize the console to provide early debug support */
console_pl011_register(uart_base, PL011_UART_CLK_IN_HZ,
PL011_BAUDRATE, &console);
/* Allow BL1 to see the whole Trusted RAM */
bl1_tzram_layout.total_base = BL1_RW_BASE;
bl1_tzram_layout.total_size = BL1_RW_SIZE;
INFO("BL1: 0x%lx - 0x%lx [size = %lu]\n", BL1_RAM_BASE, BL1_RAM_LIMIT,
BL1_RAM_LIMIT - BL1_RAM_BASE); /* bl1_size */
}
void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
meminfo_t *mem_layout = (meminfo_t *) arg1;
/* Initialize the console to provide early debug support */
rpi3_console_init();
/* Enable arch timer */
generic_delay_timer_init();
/* Setup GPIO driver */
rpi3_gpio_setup();
/* Setup the BL2 memory layout */
bl2_tzram_layout = *mem_layout;
/* Setup SDHost driver */
rpi3_sdhost_setup();
plat_rpi3_io_setup();
}
