Ejemplo n.º 1
0
static void ambench_apbread(void)
{
	u64					raw_counter = 0;
	u64					amba_counter = 0;
	unsigned long				flags;

	disable_nonboot_cpus();
	local_irq_save(flags);

	amba_clrbitsl(TIMER_CTR_REG, TIMER_CTR_EN1);
	amba_writel(TIMER1_STATUS_REG, APBREAD_RELOAD_NUM);
	amba_writel(TIMER1_RELOAD_REG, 0x0);
	amba_writel(TIMER1_MATCH1_REG, 0x0);
	amba_writel(TIMER1_MATCH2_REG, 0x0);
	amba_clrbitsl(TIMER_CTR_REG, TIMER_CTR_OF1);
	amba_clrbitsl(TIMER_CTR_REG, TIMER_CTR_CSL1);

	amba_setbitsl(TIMER_CTR_REG, TIMER_CTR_EN1);
	do {
		raw_counter++;
	} while(__raw_readl((const volatile void *)TIMER1_STATUS_REG));

	amba_clrbitsl(TIMER_CTR_REG, TIMER_CTR_EN1);
	amba_writel(TIMER1_STATUS_REG, APBREAD_RELOAD_NUM);
	amba_writel(TIMER1_RELOAD_REG, 0x0);
	amba_writel(TIMER1_MATCH1_REG, 0x0);
	amba_writel(TIMER1_MATCH2_REG, 0x0);
	amba_clrbitsl(TIMER_CTR_REG, TIMER_CTR_OF1);
	amba_clrbitsl(TIMER_CTR_REG, TIMER_CTR_CSL1);

	amba_setbitsl(TIMER_CTR_REG, TIMER_CTR_EN1);
	do {
		amba_counter++;
	} while(amba_readl(TIMER1_STATUS_REG));
	amba_clrbitsl(TIMER_CTR_REG, TIMER_CTR_EN1);

	local_irq_restore(flags);
	enable_nonboot_cpus();

#if defined(CONFIG_PLAT_AMBARELLA_SUPPORT_HAL)
	raw_counter *= get_apb_bus_freq_hz();
#else
	raw_counter *= clk_get_rate(clk_get(NULL, "gclk_apb"));
#endif
	do_div(raw_counter, APBREAD_RELOAD_NUM);
#if defined(CONFIG_PLAT_AMBARELLA_SUPPORT_HAL)
	amba_counter *= get_apb_bus_freq_hz();
#else
	amba_counter *= clk_get_rate(clk_get(NULL, "gclk_apb"));
#endif
	do_div(amba_counter, APBREAD_RELOAD_NUM);
	pr_info("CPU[0x%x] APBRead: raw speed %llu/s!\n",
		cpu_architecture(), raw_counter);
	pr_info("CPU[0x%x] APBRead: amba speed %llu/s!\n",
		cpu_architecture(), amba_counter);
}
Ejemplo n.º 2
0
static void ambench_apbread(void)
{
	u64					raw_counter = 0;
	u64					amba_counter = 0;
	unsigned long				flags;

	disable_nonboot_cpus();
	local_irq_save(flags);

	amba_clrbitsl(TIMER_CTR_REG, TIMER_CTR_EN1);
	amba_writel(TIMER1_STATUS_REG, APBREAD_RELOAD_NUM);
	amba_writel(TIMER1_RELOAD_REG, 0x0);
	amba_writel(TIMER1_MATCH1_REG, 0x0);
	amba_writel(TIMER1_MATCH2_REG, 0x0);
	amba_clrbitsl(TIMER_CTR_REG, TIMER_CTR_OF1);
	amba_clrbitsl(TIMER_CTR_REG, TIMER_CTR_CSL1);

	amba_setbitsl(TIMER_CTR_REG, TIMER_CTR_EN1);
	do {
		raw_counter++;
	} while(__raw_readl(TIMER1_STATUS_REG));

	amba_clrbitsl(TIMER_CTR_REG, TIMER_CTR_EN1);
	amba_writel(TIMER1_STATUS_REG, APBREAD_RELOAD_NUM);
	amba_writel(TIMER1_RELOAD_REG, 0x0);
	amba_writel(TIMER1_MATCH1_REG, 0x0);
	amba_writel(TIMER1_MATCH2_REG, 0x0);
	amba_clrbitsl(TIMER_CTR_REG, TIMER_CTR_OF1);
	amba_clrbitsl(TIMER_CTR_REG, TIMER_CTR_CSL1);

	amba_setbitsl(TIMER_CTR_REG, TIMER_CTR_EN1);
	do {
		amba_counter++;
	} while(amba_readl(TIMER1_STATUS_REG));
	amba_clrbitsl(TIMER_CTR_REG, TIMER_CTR_EN1);

	local_irq_restore(flags);
	enable_nonboot_cpus();

	raw_counter *= get_apb_bus_freq_hz();
	do_div(raw_counter, APBREAD_RELOAD_NUM);
	amba_counter *= get_apb_bus_freq_hz();
	do_div(amba_counter, APBREAD_RELOAD_NUM);
	pr_info("CPU[0x%x] APBRead: raw speed %llu/s!\n",
		cpu_architecture(), raw_counter);
	pr_info("CPU[0x%x] APBRead: amba speed %llu/s!\n",
		cpu_architecture(), amba_counter);
}
Ejemplo n.º 3
0
/* ==========================================================================*/
static u32 ambarella_timer_get_pll(void)
{
#if defined(CONFIG_PLAT_AMBARELLA_SUPPORT_HAL)
	return get_apb_bus_freq_hz();
#else
	return clk_get_rate(clk_get(NULL, "gclk_apb"));
#endif
}
Ejemplo n.º 4
0
/**
 * Initialize the timer to start ticking.
 */
void timer_init(void)
{
	u32 apb_freq = get_apb_bus_freq_hz();
	unsigned int cnt;

	timer1_count = 0;
	timer2_count = 0;
	timer3_count = 0;

	/* Reset all timers */
	writel(TIMER_CTR_REG, 0x0);

	/* Setup VIC */
	vic_set_type(TIMER1_INT_VEC, VIRQ_RISING_EDGE);
	vic_enable(TIMER1_INT_VEC);

	vic_set_type(TIMER2_INT_VEC, VIRQ_RISING_EDGE);
	vic_enable(TIMER2_INT_VEC);

	/* Reset timer control register */
	writel(TIMER_CTR_REG, 0x0);

	/* Setup timer 1: 100 millisecond */
	cnt = apb_freq / 10;
	writel(TIMER1_STATUS_REG, cnt);
	writel(TIMER1_RELOAD_REG, cnt);
	writel(TIMER1_MATCH1_REG, 0x0);
	writel(TIMER1_MATCH2_REG, 0x0);

	/* Setup timer 2: 1 millisecond */
	cnt = apb_freq / 1000;
	writel(TIMER2_STATUS_REG, cnt);
	writel(TIMER2_RELOAD_REG, cnt);
	writel(TIMER2_MATCH1_REG, 0x0);
	writel(TIMER2_MATCH2_REG, 0x0);

	/* Setup timer 3: only used for polling */
	writel(TIMER3_STATUS_REG, 0xffffffff);
	writel(TIMER3_RELOAD_REG, 0xffffffff);
	writel(TIMER3_MATCH1_REG, 0x0);
	writel(TIMER3_MATCH2_REG, 0x0);

	/* Start timer */
	writel(TIMER_CTR_REG, 0x5);
}
Ejemplo n.º 5
0
amb_clock_frequency_t rct_get_ssi_clock_frequency (void)
{
	return (get_apb_bus_freq_hz() / readl(CG_SSI_REG));
}
Ejemplo n.º 6
0
u32 timer_tick2ms(u32 s_tck, u32 e_tck)
{
	u32 apb_freq = get_apb_bus_freq_hz();
	return (s_tck - e_tck) / (apb_freq / 1000);
}