__u32 usb_get_ep0_csr(pusb_struct pusb)
{
__u32 ret;
ret = get_hvalue(pusb->reg_base + USB_hCSR0_OFF);
return ret;
}
void usb_ep0_flush_fifo(pusb_struct pusb)
{
__u32 reg_val;
reg_val = get_hvalue(pusb->reg_base + USB_hCSR0_OFF);
reg_val |= (0x1<<8);
put_hvalue(pusb->reg_base + USB_hCSR0_OFF, reg_val);
}
void usb_ep0_clear_naktimeout(pusb_struct pusb)
{
__u32 reg_val;
reg_val = get_hvalue(pusb->reg_base + USB_hCSR0_OFF);
reg_val &= ~(0x1<<7);
put_hvalue(pusb->reg_base + USB_hCSR0_OFF, reg_val);
}
void usb_ep0_clear_rxpktrdy(pusb_struct pusb)
{
__u32 reg_val;
reg_val = get_hvalue(pusb->reg_base + USB_hCSR0_OFF);
reg_val |= (0x1<<6);
put_hvalue(pusb->reg_base + USB_hCSR0_OFF, reg_val);
}
void usb_ep0_set_reqpkt(pusb_struct pusb)
{
__u32 reg_val;
reg_val = get_hvalue(pusb->reg_base + USB_hCSR0_OFF);
reg_val |= (0x1<<5);
put_hvalue(pusb->reg_base + USB_hCSR0_OFF, reg_val);
}
void usb_ep0_clear_setupend(pusb_struct pusb)
{
__u32 reg_val;
reg_val = get_hvalue(pusb->reg_base + USB_hCSR0_OFF);
reg_val |= (0x1<<7);
put_hvalue(pusb->reg_base + USB_hCSR0_OFF, reg_val);
}
void usb_ep0_enable_ping(pusb_struct pusb)
{
__u32 reg_val;
reg_val = get_hvalue(pusb->reg_base + USB_hCSR0_OFF);
reg_val &= ~(0x1<<8);
put_hvalue(pusb->reg_base + USB_hCSR0_OFF, reg_val);
}
void usb_ep0_clear_statuspkt(pusb_struct pusb)
{
__u32 reg_val;
reg_val = get_hvalue(pusb->reg_base + USB_hCSR0_OFF);
reg_val &= ~(0x1<<6);
put_hvalue(pusb->reg_base + USB_hCSR0_OFF, reg_val);
}
void usb_clear_eprx_interrupt_enable(pusb_struct pusb, __u32 bm)
{
__u16 reg_val;
reg_val = get_hvalue(pusb->reg_base + USB_hINTRRXE_OFF);
reg_val &= ~(bm&0xffff);
put_hvalue(pusb->reg_base + USB_hINTRRXE_OFF, reg_val);
}
void usb_set_eptx_interrupt_enable(pusb_struct pusb, __u32 bm)
{
__u16 reg_val;
reg_val = get_hvalue(pusb->reg_base + USB_hINTRTXE_OFF);
reg_val |= (bm&0xffff);
put_hvalue(pusb->reg_base + USB_hINTRTXE_OFF, reg_val);
}
__u32 usb_get_eprx_csr(pusb_struct pusb)
{
return get_hvalue(pusb->reg_base + USB_hRXCSR_OFF);
}
__u32 usb_get_eprx_maxpkt(pusb_struct pusb)
{
return get_hvalue(pusb->reg_base + USB_hRXMAXP_OFF)&0xffff;
}
uchar write_i2c(uchar addr_i2c, uchar *data, uchar nb_byte)
{
__disable_interrupt();
//Transmitted by master
set_hbit(I2CCTL,I2CCTL_I2CMTX);
//Continues clock upon completion
// clr_hbit(I2CCTL,I2CCTL_I2CCS);
//wait for I2C bus to be ready
if (!waiti2cmbb())
{
__enable_interrupt();
return FALSE;
}
/********************/
/* Send I2C address */
/********************/
//Write slave address
put_hvalue(I2CDR,(addr_i2c|I2C_WRITE_INSTR));
//Start condition
set_hbit(I2CCTL,I2CCTL_I2CMSTA);
//Look at arbitration
if((get_hvalue(I2CSR)&I2CSR_I2CMAL))
{
//Clear status
put_hvalue(I2CSR,0x0000);
__enable_interrupt();
return FALSE;
}
//wait for transfer to be completed
if (!waiti2cmcf())
{
__enable_interrupt();
return FALSE;
}
//Look at acknowledge
if((get_hvalue(I2CSR)&I2CSR_I2CRXAK))
{
//Stop condition
clr_hbit(I2CCTL,I2CCTL_I2CMSTA);
//Clear status
put_hvalue(I2CSR,0x0000);
__enable_interrupt();
return FALSE;
}
/*****************/
/* Send I2C data */
/*****************/
//Clear status
put_hvalue(I2CSR,0x0000);
while(nb_byte--)
{
//Write data
put_hvalue(I2CDR,*(data++));
//wait for transfer to be completed
if (!waiti2cmcf())
{
__enable_interrupt();
return FALSE;
}
//Look at acknowledge
if((get_hvalue(I2CSR)&I2CSR_I2CRXAK))
{
//Stop condition
clr_hbit(I2CCTL,I2CCTL_I2CMSTA);
//Clear status
put_hvalue(I2CSR,0x0000);
__enable_interrupt();
return FALSE;
}
//Clear completion bit
clr_hbit(I2CSR,I2CSR_I2CMCF);
}
/*************/
/* Stop I2C */
/*************/
//Clear status
put_hvalue(I2CSR,0x0000);
//Stop condition
clr_hbit(I2CCTL,I2CCTL_I2CMSTA);
__enable_interrupt();
return TRUE;
}
uchar read_i2c(uchar addr_i2c, uchar *data, uchar nb_byte)
{
__disable_interrupt();
//Transmitted by master
clr_hbit(I2CCTL,I2CCTL_I2CMTX);
//Continues clock upon completion
// clr_hbit(I2CCTL,I2CCTL_I2CCS);
//wait for I2C bus to be ready
if (!waiti2cmbb())
{
__enable_interrupt();
return FALSE;
}
/********************/
/* Send I2C address */
/********************/
//Write slave address
put_hvalue(I2CDR,(addr_i2c|I2C_READ_INSTR));
//Start condition
set_hbit(I2CCTL,I2CCTL_I2CMSTA);
//Look at arbitration
if((get_hvalue(I2CSR)&I2CSR_I2CMAL))
{
//Clear status
put_hvalue(I2CSR,0x0000);
__enable_interrupt();
return FALSE;
}
//wait for transfer to be completed
if (!waiti2cmcf())
{
__enable_interrupt();
return FALSE;
}
//Look at acknowledge
if((get_hvalue(I2CSR)&I2CSR_I2CRXAK))
{
//Stop condition
clr_hbit(I2CCTL,I2CCTL_I2CMSTA);
//Clear status
put_hvalue(I2CSR,0x0000);
__enable_interrupt();
return FALSE;
}
/********************/
/* Receive I2C data */
/********************/
do{
//Clear status
put_hvalue(I2CSR,0x0000);
//Check if last byte
if((nb_byte-1)==0)
break;
//wait for transfer to be completed
if (!waiti2cmcf())
{
__enable_interrupt();
return FALSE;
}
//Read data
*(data++)=get_value(I2CDR);
}while(nb_byte--);
//Send no ack
set_hbit(I2CCTL,I2CCTL_I2CTXAK);
//wait for transfer to be completed
if (!waiti2cmcf())
{
__enable_interrupt();
return FALSE;
}
//Read data
*(data++)=get_value(I2CDR);
//Clear status
put_hvalue(I2CSR,0x0000);
/*************/
/* Stop I2C */
/*************/
//Stop condition
clr_hbit(I2CCTL,I2CCTL_I2CMSTA);
clr_hbit(I2CCTL,I2CCTL_I2CTXAK);
__enable_interrupt();
return TRUE;
}
__u32 usb_get_ep0_count(pusb_struct pusb)
{
return get_hvalue(pusb->reg_base + USB_hCOUNT0_OFF)&0x7f;
}
__u32 usb_get_frame_number(pusb_struct pusb)
{
return get_hvalue(pusb->reg_base + USB_hFRAME_OFF)&0x7ff;
}
__u32 usb_get_eprx_interrupt_status(pusb_struct pusb)
{
return get_hvalue(pusb->reg_base + USB_hINTRRX_OFF)&0xffff;
}
int waiti2cmbb()
{
int nmax=1000000;
while((get_hvalue(I2CSR)&I2CSR_I2CMBB)&&(nmax>0)) nmax--;
return nmax;
}
__u32 usb_get_eprx_count(pusb_struct pusb)
{
return get_hvalue(pusb->reg_base + USB_hRXCOUNT_OFF)&0x1fff;
}
int waiti2cmcf()
{
int nmax=1000000;
while((!(get_hvalue(I2CSR)&I2CSR_I2CMCF))&&(nmax>0)) nmax--;
return nmax;
}
