Ejemplos de get_module_clk_id en C++ (Cpp)

Ejemplo n.º 1

int nvhost_module_init(struct nvhost_module *mod, const char *name,
		nvhost_modulef func, struct nvhost_module *parent,
		struct device *dev)
{
	int i = 0;

	mod->name = name;

	while (i < NVHOST_MODULE_MAX_CLOCKS) {
		long rate;
		mod->clk[i] = clk_get(dev, get_module_clk_id(name, i));
		if (IS_ERR_OR_NULL(mod->clk[i]))
			break;
		rate = clk_round_rate(mod->clk[i], UINT_MAX);
		if (rate < 0) {
			pr_err("%s: can't get maximum rate for %s\n",
				__func__, name);
			break;
		}
		clk_set_rate(mod->clk[i], rate);
		i++;
	}

	mod->num_clks = i;
	mod->func = func;
	mod->parent = parent;
	mod->powered = false;
	mutex_init(&mod->lock);
	init_waitqueue_head(&mod->idle);
	INIT_DELAYED_WORK(&mod->powerdown, powerdown_handler);

	return 0;
}

Ejemplo n.º 2

int nvhost_module_init(struct nvhost_module *mod, const char *name,
		nvhost_modulef func, struct nvhost_module *parent,
		struct device *dev)
{
	int i = 0;
	mod->name = name;

	while (i < NVHOST_MODULE_MAX_CLOCKS) {
		long rate;
		mod->clk[i] = clk_get(dev, get_module_clk_id(name, i));
		if (IS_ERR_OR_NULL(mod->clk[i]))
			break;
		rate = clk_round_rate(mod->clk[i], UINT_MAX);
		if (rate < 0) {
			pr_err("%s: can't get maximum rate for %s\n",
				__func__, name);
			break;
		}
		if (rate != clk_get_rate(mod->clk[i])) {
			clk_set_rate(mod->clk[i], rate);
		}
		i++;
	}

	mod->num_clks = i;
	mod->func = func;
	mod->parent = parent;
	mod->powered = false;
	mod->powergate_id = get_module_powergate_id(name);
	mod->force_suspend = false;

#if CONFIG_DISABLE_3D_POWERGATING
	/*
	 * It is possible for the 3d block to generate an invalid memory
	 * request during the power up sequence in some cases.  Workaround
	 * is to disable 3d block power gating.
	 */
	if (mod->powergate_id == TEGRA_POWERGATE_3D) {
		tegra_powergate_sequence_power_up(mod->powergate_id,
			mod->clk[0]);
		clk_disable(mod->clk[0]);
		mod->powergate_id = -1;
	}
#endif

#ifdef DISABLE_MPE_POWERGATING
	/*
	 * Disable power gating for MPE as it seems to cause issues with
	 * camera record stress tests when run in loop.
	 */
	if (mod->powergate_id == TEGRA_POWERGATE_MPE) {
		tegra_powergate_sequence_power_up(mod->powergate_id,
			mod->clk[0]);
		clk_disable(mod->clk[0]);
		mod->powergate_id = -1;
	}
#endif

	mutex_init(&mod->lock);
	init_waitqueue_head(&mod->idle);
	INIT_DELAYED_WORK(&mod->powerdown, powerdown_handler);

	return 0;
}