void
print_nodeinfo(node_t *tnode)
{
U32 pci_id, secbus;
int i;
for(i=0; i < tnode->node_count; i++) {
pci_id = tnode->permnodes[i]->pci_id;
/* Read the Mmode Status */
printf("Type: %s, ", bname[tnode->permnodes[i]->node_type & 0x0F]);
printf("Pci : %08X, ", pci_id);
printf("Cmd : %08X, ", pciconf_readw(pci_id, PCI_CONF_COMM));
printf("Sts : %08X\n\r", pciconf_readw(pci_id, PCI_CONF_STAT));
if ( (tnode->permnodes[i]->node_type == NODE_NIC) ||
(tnode->permnodes[i]->node_type == NODE_RAC)) {
secbus = pciconf_readb(pci_id, PCI_BCONF_SECBUS);
/* Read Galileo Status */
pci_id = get_pci_id ( secbus, GAL120_ID, 0);
if ( pci_id ) {
printf(" Galileo, Pci : %08X, ", pci_id);
printf("Cmd : %08X, ", pciconf_readw(pci_id, PCI_CONF_COMM));
printf("Sts : %08X\n\r", pciconf_readw(pci_id, PCI_CONF_STAT));
}
/* Read Q-Logic Status */
pci_id = get_pci_id ( secbus, ISP_ID, 0);
if ( pci_id ) {
printf(" Q-logic, Pci : %08X, ", pci_id);
printf("Cmd : %08X, ", pciconf_readw(pci_id, PCI_CONF_COMM));
printf("Sts : %08X\n\r", pciconf_readw(pci_id, PCI_CONF_STAT));
}
}
}
}
void
create_pci_nodes(int bridge)
{
unsigned long pci_id = 0;
int index, instance;
node_t *node, *tnode;
/* Probe the Bus on Bridge 'bridge' for NICs */
index = 0;
instance = 0;
node = get_node(treenode, bridge);
pci_id = get_pci_id(node->bus_num, BRIDGE_21154_ID, instance);
while(pci_id ) {
if ( index >= MAXNODES ) {
printf("Too Many Devices\n\r");
return;
}
tnode = get_nodemem();
tnode->node_type = NODE_NIC;
tnode->pci_id = pci_id;
tnode->leaf = 1;
tnode->node_count = 0;
tnode->bus_num = node->bus_num + index + 1;
node->node_count++;
node->nic_count++;
node->orgnodes[index] = tnode;
index++;
instance++;
pci_id = get_pci_id(node->bus_num, BRIDGE_21154_ID, instance);
}
/* Probe the Bus on Bridge 'bridge' for SSDs */
instance = 0;
pci_id = get_pci_id(node->bus_num, GAL120_ID, instance);
while(pci_id ) {
if ( index >= MAXNODES ) {
printf("Too Many Devices\n\r");
return;
}
tnode = get_nodemem();
tnode->node_type = NODE_SSD;
tnode->pci_id = pci_id;
tnode->leaf = 1;
tnode->node_count = 0;
node->node_count++;
node->ssd_count++;
node->orgnodes[index] = tnode;
index++;
instance++;
pci_id = get_pci_id(node->bus_num, GAL120_ID, instance);
}
}
U32
IsNacE1()
{
#ifdef INCLUDE_ODYSSEY
if (get_pci_id(0, ISP2_ID, 2))
return(1);
else
return(0);
#else
return(1);
#endif
}
U32
get_isp_int(U32 instance)
{
U32 pci_id;
#ifdef CONFIG_E2
if ( IsNacE1())
pci_id = PADDR(0, (7 + instance), 0);
else
pci_id = PADDR(0, (2 + instance), 0);
#else
pci_id = get_pci_id(0, ISP_ID, instance);
#endif
if ( pci_id ) {
return((U32)pciconf_readb(pci_id, PCI_CONF_ILINE));
}
return(0);
}
U32
get_isp_base(U32 instance)
{
U32 pci_id;
#ifdef CONFIG_E2
if ( IsNacE1())
pci_id = PADDR(0, (7 + instance), 0);
else
pci_id = PADDR(0, (2 + instance), 0);
#else
pci_id = get_pci_id(0, ISP_ID, instance);
#endif
if ( pci_id ) {
return(pciconf_readl(pci_id, PCI_CONF_BASE0) & PCI_BASE_IOADDR_M);
}
return(0);
}
void IOPMaster(UNSIGNED argc, VOID *argv)
{
STATUS status;
int ch = 0;
int i;
unsigned long pci_id;
/* Access argc and argv just to avoid compilation warnings. */
status = (STATUS) argc + (STATUS) argv;
printf("\n\r");
printf("Executing the System Code....\n\r");
/* Initilaize the Hardware */
#ifdef INCLUDE_ODYSSEY
#if 0
if ((status = Init_Hardware()) != NU_SUCCESS)
printf("Error in init %d\r\n", status);
gt_init();
gt_initdma(0);
gt_initdma(1);
board_type = memmaps.aBoardType[getSlotNumber()];
init_buf(get_slotno());
#else
init_galileo();
/* enable the Switches */
*((U8 *)(0xBC0F8000)) = 0;
a_id = b_id = c_id = d_id = e_id = f_id = h_id = 0;
/* Init the E bridge */
printf("Initializing the Bridge E....");
pci_id = get_pci_id(0, BRIDGE_21154_ID, 0);
if ( pci_id ) {
bridge_init(pci_id, PCI_G_NUM, PCI_E_NUM, PCI_E_SUB, 0xFFFFFFFF, 0);
printf("OK\n\r");
e_id = pci_id;
} else {
printf("Fail\n\r");
goto done;
}
/* Init the F bridge */
printf("Initializing the Bridge F....");
pci_id = get_pci_id(0, BRIDGE_21154_ID, 1);
if ( pci_id ) {
bridge_init(pci_id, PCI_G_NUM, PCI_F_NUM, PCI_F_SUB, 0xFFFFFFFF, 0);
printf("OK\n\r");
f_id = pci_id;
} else {
printf("Fail\n\r");
goto done;
}
/* Init the H bridge */
printf("Initializing the Bridge H....");
pci_id = get_pci_id(PCI_F_NUM, BRIDGE_21154_ID, 0);
if ( pci_id ) {
bridge_init(pci_id, PCI_F_NUM, PCI_H_NUM, PCI_H_SUB, 0xFFFFFFFF, 0);
printf("OK\n\r");
h_id = pci_id;
} else {
printf("Fail\n\r");
goto done;
}
/* Init the C bridge */
printf("Initializing the Bridge C....");
pci_id = get_pci_id(PCI_F_NUM, BRIDGE_21154_ID, 1);
if ( pci_id ) {
bridge_init(pci_id, PCI_F_NUM, PCI_C_NUM, PCI_C_SUB, 0xFFFFFFFF, 0);
printf("OK\n\r");
c_id = pci_id;
} else {
printf("Fail\n\r");
goto done;
}
/* Init the D bridge */
printf("Initializing the Bridge D....");
pci_id = get_pci_id(PCI_F_NUM, BRIDGE_21154_ID, 2);
if ( pci_id ) {
bridge_init(pci_id, PCI_F_NUM, PCI_D_NUM, PCI_D_SUB, 0xFFFFFFFF, 0);
printf("OK\n\r");
d_id = pci_id;
} else {
printf("Fail\n\r");
goto done;
}
/* Init the A bridge */
printf("Initializing the Bridge A....");
pci_id = get_pci_id(PCI_H_NUM, BRIDGE_21154_ID, 0);
if ( pci_id ) {
bridge_init(pci_id, PCI_H_NUM, PCI_A_NUM, PCI_A_SUB, 0xFFFFFFFF, 0);
printf("OK\n\r");
a_id = pci_id;
} else {
printf("Fail\n\r");
goto done;
}
/* Init the B bridge */
printf("Initializing the Bridge B....");
pci_id = get_pci_id(PCI_H_NUM, BRIDGE_21154_ID, 1);
if ( pci_id ) {
bridge_init(pci_id, PCI_H_NUM, PCI_B_NUM, PCI_B_SUB, 0xFFFFFFFF, 0);
printf("OK\n\r");
b_id = pci_id;
} else {
printf("Fail\n\r");
goto done;
}
#endif
#else
init_galileo();
#endif INCLUDE_ODYSSEY
done:
/* Spawn the rest of the tasks and initialize */
Init_System(&System_Memory);
/* Lower the Priority of this task */
NU_Change_Priority( (NU_TASK *)&IOPMaster_Task, 250 );
/* Now this task will be active with lowest priority and can be used to
* any cleanup required
*/
for(;;){
NU_Sleep(500);
Cleanup_System();
/* rlw: can we implement erc91 functionality here? */
}
}
static struct icd_drm_device *probe_syspath(const struct icd_instance *instance,
struct icd_drm_device *devices,
struct udev *udev, const char *syspath,
int vendor_id_match)
{
struct udev_device *minor, *parent;
enum icd_drm_minor_type type;
const char *parent_syspath;
struct icd_drm_device *dev;
int vendor, devid;
minor = udev_device_new_from_syspath(udev, syspath);
if (!minor)
return devices;
type = get_minor_type(minor);
if (type == ICD_DRM_MINOR_INVALID) {
udev_device_unref(minor);
return devices;
}
parent = udev_device_get_parent(minor);
if (!parent) {
udev_device_unref(minor);
return devices;
}
get_pci_id(parent, &vendor, &devid);
if (vendor_id_match && vendor != vendor_id_match) {
udev_device_unref(minor);
return devices;
}
parent_syspath = udev_device_get_syspath(parent);
dev = find_dev(devices, parent_syspath);
if (dev) {
assert(dev->devid == devid);
assert(!dev->minors[type]);
if (dev->minors[type])
udev_device_unref((struct udev_device *) dev->minors[type]);
dev->minors[type] = (void *) minor;
return devices;
} else {
dev = icd_instance_alloc(instance, sizeof(*dev), sizeof(int),
VK_SYSTEM_ALLOCATION_SCOPE_COMMAND);
if (!dev)
return devices;
memset(dev, 0, sizeof(*dev));
dev->id = (const void *) parent_syspath;
dev->devid = devid;
dev->minors[type] = (void *) minor;
dev->next = devices;
return dev;
}
}
