bool has_erratum_a007798(void)
{
#ifdef CONFIG_PPC
return SVR_SOC_VER(get_svr()) == SVR_T4240 &&
IS_SVR_REV(get_svr(), 2, 0);
#endif
return false;
}
bool has_dual_phy(void)
{
u32 svr = get_svr();
u32 soc = SVR_SOC_VER(svr);
switch (soc) {
#ifdef CONFIG_PPC
case SVR_T1023:
case SVR_T1024:
case SVR_T1013:
case SVR_T1014:
return IS_SVR_REV(svr, 1, 0);
case SVR_T1040:
case SVR_T1042:
case SVR_T1020:
case SVR_T1022:
case SVR_T2080:
case SVR_T2081:
return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
case SVR_T4240:
case SVR_T4160:
case SVR_T4080:
return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
#endif
}
return false;
}
bool has_erratum_a010151(void)
{
u32 svr = get_svr();
u32 soc = SVR_SOC_VER(svr);
#ifdef CONFIG_ARM64
if (IS_SVR_DEV(svr, SVR_DEV(SVR_LS1043A)))
return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
#endif
switch (soc) {
#ifdef CONFIG_ARM64
case SVR_LS2080A:
case SVR_LS2085A:
/* fallthrough */
case SVR_LS2088A:
/* fallthrough */
case SVR_LS2081A:
case SVR_LS1046A:
case SVR_LS1012A:
return IS_SVR_REV(svr, 1, 0);
#endif
#ifdef CONFIG_ARCH_LS1021A
case SOC_VER_LS1020:
case SOC_VER_LS1021:
case SOC_VER_LS1022:
case SOC_VER_SLS1020:
return IS_SVR_REV(svr, 2, 0);
#endif
}
return false;
}
bool has_erratum_a006261(void)
{
u32 svr = get_svr();
u32 soc = SVR_SOC_VER(svr);
switch (soc) {
#ifdef CONFIG_PPC
case SVR_P1010:
return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
case SVR_P2041:
case SVR_P2040:
return IS_SVR_REV(svr, 1, 0) ||
IS_SVR_REV(svr, 1, 1) ||
IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 2, 1);
case SVR_P3041:
return IS_SVR_REV(svr, 1, 0) ||
IS_SVR_REV(svr, 1, 1) ||
IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 2, 1);
case SVR_P5010:
case SVR_P5020:
case SVR_P5021:
return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
case SVR_T4240:
return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
case SVR_P5040:
return IS_SVR_REV(svr, 1, 0) ||
IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 2, 1);
#endif
}
return false;
}
void set_liodns(void)
{
/* setup general liodn offsets */
set_liodn(liodn_tbl, liodn_tbl_sz);
/* setup SEC block liodn bases & offsets if we have one */
if (IS_E_PROCESSOR(get_svr())) {
set_liodn(sec_liodn_tbl, sec_liodn_tbl_sz);
setup_sec_liodn_base();
}
/* setup FMAN block(s) liodn bases & offsets if we have one */
#ifdef CONFIG_SYS_DPAA_FMAN
set_liodn(fman1_liodn_tbl, fman1_liodn_tbl_sz);
setup_fman_liodn_base(FSL_HW_PORTAL_FMAN1, fman1_liodn_tbl,
fman1_liodn_tbl_sz);
#if (CONFIG_SYS_NUM_FMAN == 2)
set_liodn(fman2_liodn_tbl, fman2_liodn_tbl_sz);
setup_fman_liodn_base(FSL_HW_PORTAL_FMAN2, fman2_liodn_tbl,
fman2_liodn_tbl_sz);
#endif
#endif
/* setup PME liodn base */
setup_pme_liodn_base();
}
bool has_erratum_a010151(void)
{
u32 svr = get_svr();
u32 soc = SVR_SOC_VER(svr);
switch (soc) {
#ifdef CONFIG_ARM64
case SVR_LS2080A:
case SVR_LS2085A:
case SVR_LS1046A:
case SVR_LS1012A:
return IS_SVR_REV(svr, 1, 0);
case SVR_LS1043A:
return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
#endif
#ifdef CONFIG_LS102XA
case SOC_VER_LS1020:
case SOC_VER_LS1021:
case SOC_VER_LS1022:
case SOC_VER_SLS1020:
return IS_SVR_REV(svr, 2, 0);
#endif
}
return false;
}
bool has_erratum_a004477(void)
{
u32 svr = get_svr();
u32 soc = SVR_SOC_VER(svr);
switch (soc) {
#ifdef CONFIG_PPC
case SVR_P1010:
return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
case SVR_P1022:
case SVR_9131:
case SVR_9132:
return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
case SVR_P2020:
return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0) ||
IS_SVR_REV(svr, 2, 1);
case SVR_B4860:
case SVR_B4420:
return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
case SVR_P4080:
return IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 3, 0);
#endif
}
return false;
}
u32 determine_mp_bootpg(unsigned int *pagesize)
{
u32 bootpg;
#ifdef CONFIG_SYS_FSL_ERRATUM_A004468
u32 svr = get_svr();
u32 granule_size, check;
struct law_entry e;
#endif
/* use last 4K of mapped memory */
bootpg = ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ?
CONFIG_MAX_MEM_MAPPED : gd->ram_size) +
CONFIG_SYS_SDRAM_BASE - 4096;
if (pagesize)
*pagesize = 4096;
#ifdef CONFIG_SYS_FSL_ERRATUM_A004468
/*
* Erratum A004468 has two parts. The 3-way interleaving applies to T4240,
* to be fixed in rev 2.0. The 2-way interleaving applies to many SoCs. But
* the way boot page chosen in u-boot avoids hitting this erratum. So only
* thw workaround for 3-way interleaving is needed.
*
* To make sure boot page translation works with 3-Way DDR interleaving
* enforce a check for the following constrains
* 8K granule size requires BRSIZE=8K and
* bootpg >> log2(BRSIZE) %3 == 1
* 4K and 1K granule size requires BRSIZE=4K and
* bootpg >> log2(BRSIZE) %3 == 0
*/
if (SVR_SOC_VER(svr) == SVR_T4240 && SVR_MAJ(svr) < 2) {
e = find_law(bootpg);
switch (e.trgt_id) {
case LAW_TRGT_IF_DDR_INTLV_123:
granule_size = fsl_ddr_get_intl3r() & 0x1f;
if (granule_size == FSL_DDR_3WAY_8KB_INTERLEAVING) {
if (pagesize)
*pagesize = 8192;
bootpg &= 0xffffe000; /* align to 8KB */
check = bootpg >> 13;
while ((check % 3) != 1)
check--;
bootpg = check << 13;
debug("Boot page (8K) at 0x%08x\n", bootpg);
break;
} else {
bootpg &= 0xfffff000; /* align to 4KB */
check = bootpg >> 12;
while ((check % 3) != 0)
check--;
bootpg = check << 12;
debug("Boot page (4K) at 0x%08x\n", bootpg);
}
break;
default:
break;
}
int board_early_init_f (void)
{
#ifdef CONFIG_MMC
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
setbits_be32(&gur->pmuxcr,
(MPC85xx_PMUXCR_SDHC_CD |
MPC85xx_PMUXCR_SDHC_WP));
/* The MPC8536DS board insert the SDHC_WP pin for erratum NMG_eSDHC118,
* however, this erratum only applies to MPC8536 Rev1.0.
* So set SDHC_WP to active-low when use MPC8536 Rev1.1 and greater.*/
if ((((SVR_MAJ(get_svr()) & 0x7) == 0x1) &&
(SVR_MIN(get_svr()) >= 0x1))
|| (SVR_MAJ(get_svr() & 0x7) > 0x1))
setbits_be32(&gur->gencfgr, MPC85xx_GENCFGR_SDHC_WP_INV);
#endif
return 0;
}
int probecpu (void)
{
uint svr;
uint ver;
svr = get_svr();
ver = SVR_SOC_VER(svr);
gd->cpu = identify_cpu(ver);
return 0;
}
static int fdt_cpu_setup(struct device_node *blob, void *unused)
{
struct device_node *node;
struct sys_info sysinfo;
/* delete crypto node if not on an E-processor */
if (!IS_E_PROCESSOR(get_svr()))
of_setup_crypto_node(blob);
fdt_add_enet_stashing(blob);
fsl_get_sys_info(&sysinfo);
node = of_find_node_by_type(blob, "cpu");
while (node) {
const uint32_t *reg;
of_property_write_u32(node, "timebase-frequency",
fsl_get_timebase_clock());
of_property_write_u32(node, "bus-frequency",
sysinfo.freqSystemBus);
reg = of_get_property(node, "reg", NULL);
of_property_write_u32(node, "clock-frequency",
sysinfo.freqProcessor[*reg]);
node = of_find_node_by_type(node, "cpu");
}
node = of_find_node_by_type(blob, "soc");
if (node)
of_property_write_u32(node, "bus-frequency",
sysinfo.freqSystemBus);
node = of_find_compatible_node(blob, NULL, "fsl,elbc");
if (node)
of_property_write_u32(node, "bus-frequency",
sysinfo.freqLocalBus);
node = of_find_compatible_node(blob, NULL, "ns16550");
while (node) {
of_property_write_u32(node, "clock-frequency",
sysinfo.freqSystemBus);
node = of_find_compatible_node(node, NULL, "ns16550");
}
node = of_find_compatible_node(blob, NULL, "fsl,mpic");
if (node)
of_property_write_u32(node, "clock-frequency",
sysinfo.freqSystemBus);
fdt_stdout_setup(blob);
return 0;
}
bool has_erratum_a008751(void)
{
u32 svr = get_svr();
u32 soc = SVR_SOC_VER(svr);
switch (soc) {
#ifdef CONFIG_ARM64
case SVR_LS2080A:
case SVR_LS2085A:
return IS_SVR_REV(svr, 1, 0);
#endif
}
return false;
}
static void setup_sec_liodn_base(void)
{
ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
u32 base;
if (!IS_E_PROCESSOR(get_svr()))
return;
/* QILCR[QSLOM] */
out_be32(&sec->qilcr_ms, 0x3ff<<16);
base = (liodn_bases[FSL_HW_PORTAL_SEC].id[0] << 16) |
liodn_bases[FSL_HW_PORTAL_SEC].id[1];
out_be32(&sec->qilcr_ls, base);
}
/* Set up the buffers and their descriptors, and bring up the
* interface
*/
static void startup_tsec(struct eth_device *dev)
{
int i;
struct tsec_private *priv = (struct tsec_private *)dev->priv;
tsec_t *regs = priv->regs;
/* reset the indices to zero */
rxIdx = 0;
txIdx = 0;
#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
uint svr;
#endif
/* Point to the buffer descriptors */
out_be32(®s->tbase, (unsigned int)(&rtx.txbd[txIdx]));
out_be32(®s->rbase, (unsigned int)(&rtx.rxbd[rxIdx]));
/* Initialize the Rx Buffer descriptors */
for (i = 0; i < PKTBUFSRX; i++) {
rtx.rxbd[i].status = RXBD_EMPTY;
rtx.rxbd[i].length = 0;
rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i];
}
rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP;
/* Initialize the TX Buffer Descriptors */
for (i = 0; i < TX_BUF_CNT; i++) {
rtx.txbd[i].status = 0;
rtx.txbd[i].length = 0;
rtx.txbd[i].bufPtr = 0;
}
rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP;
#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
svr = get_svr();
if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
redundant_init(dev);
#endif
/* Enable Transmit and Receive */
setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
/* Tell the DMA it is clear to go */
setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS);
out_be32(®s->tstat, TSTAT_CLEAR_THALT);
out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
}
enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
{
enum srds_prtcl prtcl;
u32 svr = get_svr();
u32 ver = SVR_SOC_VER(svr);
if (!serdes_lane_enabled(lane))
return NONE;
prtcl = serdes_cfg_tbl[cfg][lane];
/* P2040[e] does not support XAUI */
if (ver == SVR_P2040 && prtcl == XAUI_FM1)
prtcl = NONE;
return prtcl;
}
bool has_erratum_a005697(void)
{
u32 svr = get_svr();
u32 soc = SVR_SOC_VER(svr);
switch (soc) {
#ifdef CONFIG_PPC
case SVR_9131:
case SVR_9132:
return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
#endif
#ifdef ONFIG_ARM64
case SVR_LS1012A:
return IS_SVR_REV(svr, 1, 0);
#endif
}
return false;
}
void set_liodns(void)
{
/* setup general liodn offsets */
set_liodn(liodn_tbl, liodn_tbl_sz);
#ifdef CONFIG_SYS_SRIO
/* setup SRIO port liodns */
set_srio_liodn(srio_liodn_tbl, srio_liodn_tbl_sz);
#endif
/* setup SEC block liodn bases & offsets if we have one */
if (IS_E_PROCESSOR(get_svr())) {
set_liodn(sec_liodn_tbl, sec_liodn_tbl_sz);
setup_sec_liodn_base();
}
/* setup FMAN block(s) liodn bases & offsets if we have one */
#ifdef CONFIG_SYS_DPAA_FMAN
set_liodn(fman1_liodn_tbl, fman1_liodn_tbl_sz);
setup_fman_liodn_base(FSL_HW_PORTAL_FMAN1, fman1_liodn_tbl,
fman1_liodn_tbl_sz);
#if (CONFIG_SYS_NUM_FMAN == 2)
set_liodn(fman2_liodn_tbl, fman2_liodn_tbl_sz);
setup_fman_liodn_base(FSL_HW_PORTAL_FMAN2, fman2_liodn_tbl,
fman2_liodn_tbl_sz);
#endif
#endif
/* setup PME liodn base */
setup_pme_liodn_base();
#ifdef CONFIG_SYS_FSL_RAID_ENGINE
/* raid engine ccr addr code for liodn */
set_liodn(raide_liodn_tbl, raide_liodn_tbl_sz);
setup_raide_liodn_base();
#endif
#ifdef CONFIG_SYS_DPAA_RMAN
/* setup RMan liodn offsets */
set_rman_liodn(rman_liodn_tbl, rman_liodn_tbl_sz);
/* setup RMan liodn base */
setup_rman_liodn_base(rman_liodn_tbl, rman_liodn_tbl_sz);
#endif
}
int fsl_cpu_numcores(void)
{
void __iomem *pic = (void __iomem *)MPC8xxx_PIC_ADDR;
struct cpu_type *cpu;
uint svr;
uint ver;
int tmp;
svr = get_svr();
ver = SVR_SOC_VER(svr);
cpu = identify_cpu(ver);
/* better to query feature reporting register than just assume 1 */
if (cpu == &cpu_type_unknown) {
tmp = in_be32(pic + MPC85xx_PIC_FRR_OFFSET);
tmp = (tmp & MPC8xxx_PICFRR_NCPU_MASK) >>
MPC8xxx_PICFRR_NCPU_SHIFT;
tmp += 1;
} else {
int checkboard (void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
/* PCI slot in USER bits CSR[6:7] by convention. */
uint pci_slot = get_pci_slot ();
uint cpu_board_rev = get_cpu_board_revision ();
uint svr;
printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
get_board_version (), pci_slot);
printf ("CPU Board Revision %d.%d (0x%04x)\n",
MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
/*
* Initialize local bus.
*/
local_bus_init ();
svr = get_svr();
/*
* Fix CPU2 errata: A core hang possible while executing a
* msync instruction and a snoopable transaction from an I/O
* master tagged to make quick forward progress is present.
* Fixed in Silicon Rev.2.1
*/
if (!(SVR_MAJ(svr) >= 2 && SVR_MIN(svr) >= 1))
ecm->eebpcr |= (1 << 16);
/*
* Hack TSEC 3 and 4 IO voltages.
*/
gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */
ecm->eedr = 0xffffffff; /* clear ecm errors */
ecm->eeer = 0xffffffff; /* enable ecm errors */
return 0;
}
int is_serdes_prtcl_valid(u32 prtcl)
{
int i;
u32 svr = get_svr();
u32 ver = SVR_SOC_VER(svr);
if (prtcl > ARRAY_SIZE(serdes_cfg_tbl))
return 0;
/* P2040[e] does not support XAUI */
if (ver == SVR_P2040 && prtcl == XAUI_FM1)
return 0;
for (i = 0; i < SRDS_MAX_LANES; i++) {
if (serdes_cfg_tbl[prtcl][i] != NONE)
return 1;
}
return 0;
}
static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
__maybe_unused u32 svr = get_svr();
#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
if (IS_SVR_REV(svr, 1, 0)) {
switch (SVR_SOC_VER(svr)) {
case SVR_P1013:
case SVR_P1013_E:
case SVR_P1022:
case SVR_P1022_E:
puts("Work-around for Erratum SATA A001 enabled\n");
}
}
#endif
#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8)
puts("Work-around for Erratum SERDES8 enabled\n");
#endif
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
puts("Work-around for Erratum CPU22 enabled\n");
#endif
return 0;
}
int checkcpu (void)
{
sys_info_t sysinfo;
uint pvr, svr;
uint fam;
uint ver;
uint major, minor;
struct cpu_type *cpu;
char buf1[32], buf2[32];
#if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#endif /* CONFIG_FSL_CORENET */
#ifdef CONFIG_DDR_CLK_FREQ
u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
#else
#ifdef CONFIG_FSL_CORENET
u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
>> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
#else
u32 ddr_ratio = 0;
#endif /* CONFIG_FSL_CORENET */
#endif /* CONFIG_DDR_CLK_FREQ */
int i;
svr = get_svr();
major = SVR_MAJ(svr);
#ifdef CONFIG_MPC8536
major &= 0x7; /* the msb of this nibble is a mfg code */
#endif
minor = SVR_MIN(svr);
if (cpu_numcores() > 1) {
#ifndef CONFIG_MP
puts("Unicore software on multiprocessor system!!\n"
"To enable mutlticore build define CONFIG_MP\n");
#endif
volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
printf("CPU%d: ", pic->whoami);
} else {
puts("CPU: ");
}
cpu = gd->cpu;
puts(cpu->name);
if (IS_E_PROCESSOR(svr))
puts("E");
printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
pvr = get_pvr();
fam = PVR_FAM(pvr);
ver = PVR_VER(pvr);
major = PVR_MAJ(pvr);
minor = PVR_MIN(pvr);
printf("Core: ");
if (PVR_FAM(PVR_85xx)) {
switch(PVR_MEM(pvr)) {
case 0x1:
case 0x2:
puts("E500");
break;
case 0x3:
puts("E500MC");
break;
case 0x4:
puts("E5500");
break;
default:
puts("Unknown");
break;
}
} else {
puts("Unknown");
}
printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
get_sys_info(&sysinfo);
puts("Clock Configuration:");
for (i = 0; i < cpu_numcores(); i++) {
if (!(i & 3))
printf ("\n ");
printf("CPU%d:%-4s MHz, ",
i,strmhz(buf1, sysinfo.freqProcessor[i]));
}
printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
#ifdef CONFIG_FSL_CORENET
if (ddr_sync == 1) {
printf(" DDR:%-4s MHz (%s MT/s data rate) "
"(Synchronous), ",
strmhz(buf1, sysinfo.freqDDRBus/2),
strmhz(buf2, sysinfo.freqDDRBus));
} else {
printf(" DDR:%-4s MHz (%s MT/s data rate) "
"(Asynchronous), ",
strmhz(buf1, sysinfo.freqDDRBus/2),
strmhz(buf2, sysinfo.freqDDRBus));
}
#else
switch (ddr_ratio) {
case 0x0:
printf(" DDR:%-4s MHz (%s MT/s data rate), ",
strmhz(buf1, sysinfo.freqDDRBus/2),
strmhz(buf2, sysinfo.freqDDRBus));
break;
case 0x7:
printf(" DDR:%-4s MHz (%s MT/s data rate) "
"(Synchronous), ",
strmhz(buf1, sysinfo.freqDDRBus/2),
strmhz(buf2, sysinfo.freqDDRBus));
break;
default:
printf(" DDR:%-4s MHz (%s MT/s data rate) "
"(Asynchronous), ",
strmhz(buf1, sysinfo.freqDDRBus/2),
strmhz(buf2, sysinfo.freqDDRBus));
break;
}
#endif
#if defined(CONFIG_FSL_LBC)
if (sysinfo.freqLocalBus > LCRR_CLKDIV) {
printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
} else {
printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
sysinfo.freqLocalBus);
}
#endif
#ifdef CONFIG_CPM2
printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
#endif
#ifdef CONFIG_QE
printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE));
#endif
#ifdef CONFIG_SYS_DPAA_FMAN
for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
printf(" FMAN%d: %s MHz\n", i + 1,
strmhz(buf1, sysinfo.freqFMan[i]));
}
#endif
#ifdef CONFIG_SYS_DPAA_PME
printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME));
#endif
puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
return 0;
}
static phys_size_t sdram_setup(int casl)
{
int i;
volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
#ifdef CONFIG_TQM8548
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE)
volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
#endif
#else /* !CONFIG_TQM8548 */
unsigned long cfg_ddr_timing1;
unsigned long cfg_ddr_mode;
#endif /* CONFIG_TQM8548 */
/*
* Disable memory controller.
*/
ddr->cs0_config = 0;
ddr->sdram_cfg = 0;
#ifdef CONFIG_TQM8548
/* Timing and refresh settings for DDR2-533 and below */
ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24;
ddr->cs0_config = ddr_cs_conf[0].reg;
ddr->timing_cfg_3 = 0x00020000;
/* TIMING CFG 1, 533MHz
* PRETOACT: 4 Clocks
* ACTTOPRE: 12 Clocks
* ACTTORW: 4 Clocks
* CASLAT: 4 Clocks
* REFREC: EXT_REFREC:REFREC 53 Clocks
* WRREC: 4 Clocks
* ACTTOACT: 3 Clocks
* WRTORD: 2 Clocks
*/
ddr->timing_cfg_1 = 0x4C47D432;
/* TIMING CFG 2, 533MHz
* ADD_LAT: 3 Clocks
* CPO: READLAT + 1
* WR_LAT: 3 Clocks
* RD_TO_PRE: 2 Clocks
* WR_DATA_DELAY: 1/2 Clock
* CKE_PLS: 3 Clock
* FOUR_ACT: 14 Clocks
*/
ddr->timing_cfg_2 = 0x331848CE;
/* DDR SDRAM Mode, 533MHz
* MRS: Extended Mode Register
* OUT: Outputs enabled
* RDQS: no
* DQS: enabled
* OCD: default state
* RTT: 75 Ohms
* Posted CAS: 3 Clocks
* ODS: reduced strength
* DLL: enabled
* MR: Mode Register
* PD: fast exit
* WR: 4 Clocks
* DLL: no DLL reset
* TM: normal
* CAS latency: 4 Clocks
* BT: sequential
* Burst length: 4
*/
ddr->sdram_mode = 0x439E0642;
/* DDR SDRAM Interval, 533MHz
* REFINT: 1040 Clocks
* BSTOPRE: 256
*/
ddr->sdram_interval = (1040 << 16) | 0x100;
/*
* Workaround for erratum DDR19 according to MPC8548 Device Errata
* document, Rev. 1: DDR IO receiver must be set to an acceptable
* bias point by modifying a hidden register.
*/
if (SVR_REV (get_svr ()) < 0x21)
gur->ddrioovcr = 0x90000000; /* enable, VSEL 1.8V */
/* DDR SDRAM CFG 2
* FRC_SR: normal mode
* SR_IE: no self-refresh interrupt
* DLL_RST_DIS: don't care, leave at reset value
* DQS_CFG: differential DQS signals
* ODT_CFG: assert ODT to internal IOs only during reads to DRAM
* LVWx_CFG: don't care, leave at reset value
* NUM_PR: 1 refresh will be issued at a time
* DM_CFG: don't care, leave at reset value
* D_INIT: no data initialization
*/
ddr->sdram_cfg_2 = 0x04401000;
/* DDR SDRAM MODE 2
* MRS: Extended Mode Register 2
*/
ddr->sdram_mode_2 = 0x8000C000;
/* DDR SDRAM CLK CNTL
* CLK_ADJUST: 1/2 Clock 0x02000000
* CLK_ADJUST: 5/8 Clock 0x02800000
*/
ddr->sdram_clk_cntl = 0x02800000;
/* wait for clock stabilization */
asm ("sync;isync;msync");
udelay (1000);
#if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE)
/*
* Workaround for erratum DDR20 according to MPC8548 Device Errata
* document, Rev. 1: "CKE signal may not function correctly after
* assertion of HRESET"
*/
/* 1. Configure DDR register as is done in normal DDR configuration.
* Do not set DDR_SDRAM_CFG[MEM_EN].
*
* 2. Set reserved bit EEBACR[3] at offset 0x1000
*/
ecm->eebacr |= 0x10000000;
/*
* 3. Before DDR_SDRAM_CFG[MEM_EN] is set, write DDR_SDRAM_CFG_2[D_INIT]
*
* DDR_SDRAM_CFG_2:
* FRC_SR: normal mode
* SR_IE: no self-refresh interrupt
* DLL_RST_DIS: don't care, leave at reset value
* DQS_CFG: differential DQS signals
* ODT_CFG: assert ODT to internal IOs only during reads to DRAM
* LVWx_CFG: don't care, leave at reset value
* NUM_PR: 1 refresh will be issued at a time
* DM_CFG: don't care, leave at reset value
* D_INIT: enable data initialization
*/
ddr->sdram_cfg_2 |= 0x00000010;
/*
* 4. Before DDR_SDRAM_CFG[MEM_EN] set, write D3[21] to disable data
* training
*/
ddr->debug[2] |= 0x00000400;
/*
* 5. Wait 200 micro-seconds
*/
udelay (200);
/*
* 6. Set DDR_SDRAM_CFG[MEM_EN]
*
* BTW, initialize DDR_SDRAM_CFG:
* MEM_EN: enabled
* SREN: don't care, leave at reset value
* ECC_EN: no error report
* RD_EN: no registered DIMMs
* SDRAM_TYPE: DDR2
* DYN_PWR: no power management
* 32_BE: don't care, leave at reset value
* 8_BE: 4 beat burst
* NCAP: don't care, leave at reset value
* 2T_EN: 1T Timing
* BA_INTLV_CTL: no interleaving
* x32_EN: x16 organization
* PCHB8: MA[10] for auto-precharge
* HSE: half strength for single and 2-layer stacks
* (full strength for 3- and 4-layer stacks not
* yet considered)
* MEM_HALT: no halt
* BI: automatic initialization
*/
ddr->sdram_cfg = 0x83000008;
/*
* 7. Poll DDR_SDRAM_CFG_2[D_INIT] until it is cleared by hardware
*/
asm ("sync;isync;msync");
while (ddr->sdram_cfg_2 & 0x00000010)
asm ("eieio");
/*
* 8. Clear D3[21] to re-enable data training
*/
ddr->debug[2] &= ~0x00000400;
/*
* 9. Set D2(21) to force data training to run
*/
ddr->debug[1] |= 0x00000400;
/*
* 10. Poll on D2[21] until it is cleared by hardware
*/
asm ("sync;isync;msync");
while (ddr->debug[1] & 0x00000400)
asm ("eieio");
/*
* 11. Clear reserved bit EEBACR[3] at offset 0x1000
*/
ecm->eebacr &= ~0x10000000;
#else /* !(CONFIG_TQM8548_AG || CONFIG_TQM8548_BE) */
/* DDR SDRAM CLK CNTL
* MEM_EN: enabled
* SREN: don't care, leave at reset value
* ECC_EN: no error report
* RD_EN: no register DIMMs
* SDRAM_TYPE: DDR2
* DYN_PWR: no power management
* 32_BE: don't care, leave at reset value
* 8_BE: 4 beat burst
* NCAP: don't care, leave at reset value
* 2T_EN: 1T Timing
* BA_INTLV_CTL: no interleaving
* x32_EN: x16 organization
* PCHB8: MA[10] for auto-precharge
* HSE: half strength for single and 2-layer stacks
* (full strength for 3- and 4-layer stacks no yet considered)
* MEM_HALT: no halt
* BI: automatic initialization
*/
ddr->sdram_cfg = 0x83000008;
#endif /* CONFIG_TQM8548_AG || CONFIG_TQM8548_BE */
asm ("sync; isync; msync");
udelay (1000);
#else /* !CONFIG_TQM8548 */
switch (casl) {
case 20:
cfg_ddr_timing1 = 0x47405331 | (3 << 16);
cfg_ddr_mode = 0x40020002 | (2 << 4);
break;
case 25:
cfg_ddr_timing1 = 0x47405331 | (4 << 16);
cfg_ddr_mode = 0x40020002 | (6 << 4);
break;
case 30:
default:
cfg_ddr_timing1 = 0x47405331 | (5 << 16);
cfg_ddr_mode = 0x40020002 | (3 << 4);
break;
}
ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24;
ddr->cs0_config = ddr_cs_conf[0].reg;
ddr->timing_cfg_1 = cfg_ddr_timing1;
ddr->timing_cfg_2 = 0x00000800; /* P9-45,may need tuning */
ddr->sdram_mode = cfg_ddr_mode;
ddr->sdram_interval = 0x05160100; /* autocharge,no open page */
ddr->err_disable = 0x0000000D;
asm ("sync; isync; msync");
udelay (1000);
ddr->sdram_cfg = 0xc2000000; /* unbuffered,no DYN_PWR */
asm ("sync; isync; msync");
udelay (1000);
#endif /* CONFIG_TQM8548 */
for (i = 0; i < N_DDR_CS_CONF; i++) {
ddr->cs0_config = ddr_cs_conf[i].reg;
if (get_ram_size (0, ddr_cs_conf[i].size) ==
ddr_cs_conf[i].size) {
/*
* size detected -> set Chip Select Bounds Register
*/
ddr->cs0_bnds = (ddr_cs_conf[i].size - 1) >> 24;
break;
}
}
int
checkcpu(void)
{
sys_info_t sysinfo;
uint pvr, svr;
uint ver;
uint major, minor;
uint lcrr; /* local bus clock ratio register */
uint clkdiv; /* clock divider portion of lcrr */
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile ccsr_gur_t *gur = &immap->im_gur;
puts("Freescale PowerPC\n");
pvr = get_pvr();
ver = PVR_VER(pvr);
major = PVR_MAJ(pvr);
minor = PVR_MIN(pvr);
puts("CPU:\n");
puts(" Core: ");
switch (ver) {
case PVR_VER(PVR_86xx):
{
uint msscr0 = mfspr(MSSCR0);
printf("E600 Core %d", (msscr0 & 0x20) ? 1 : 0 );
if (gur->pordevsr & MPC86xx_PORDEVSR_CORE1TE)
puts("\n Core1Translation Enabled");
debug(" (MSSCR0=%x, PORDEVSR=%x)", msscr0, gur->pordevsr);
}
break;
default:
puts("Unknown");
break;
}
printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
svr = get_svr();
ver = SVR_SOC_VER(svr);
major = SVR_MAJ(svr);
minor = SVR_MIN(svr);
puts(" System: ");
switch (ver) {
case SVR_8641:
if (SVR_SUBVER(svr) == 1) {
puts("8641D");
} else {
puts("8641");
}
break;
case SVR_8610:
puts("8610");
break;
default:
puts("Unknown");
break;
}
printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
get_sys_info(&sysinfo);
puts(" Clocks: ");
printf("CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000);
printf("MPX:%4lu MHz, ", sysinfo.freqSystemBus / 1000000);
printf("DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000);
#if defined(CONFIG_SYS_LBC_LCRR)
lcrr = CONFIG_SYS_LBC_LCRR;
#else
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile ccsr_lbc_t *lbc = &immap->im_lbc;
lcrr = lbc->lcrr;
}
#endif
clkdiv = lcrr & 0x0f;
if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
printf("LBC:%4lu MHz\n",
sysinfo.freqSystemBus / 1000000 / clkdiv);
} else {
printf(" LBC: unknown (lcrr: 0x%08x)\n", lcrr);
}
puts(" L2: ");
if (get_l2cr() & 0x80000000)
puts("Enabled\n");
else
puts("Disabled\n");
return 0;
}
int checkcpu (void)
{
sys_info_t sysinfo;
uint lcrr; /* local bus clock ratio register */
uint clkdiv; /* clock divider portion of lcrr */
uint pvr, svr;
uint fam;
uint ver;
uint major, minor;
struct cpu_type *cpu;
#ifdef CONFIG_DDR_CLK_FREQ
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
#else
u32 ddr_ratio = 0;
#endif
svr = get_svr();
ver = SVR_SOC_VER(svr);
major = SVR_MAJ(svr);
#ifdef CONFIG_MPC8536
major &= 0x7; /* the msb of this nibble is a mfg code */
#endif
minor = SVR_MIN(svr);
puts("CPU: ");
cpu = identify_cpu(ver);
if (cpu) {
puts(cpu->name);
if (IS_E_PROCESSOR(svr))
puts("E");
} else {
puts("Unknown");
}
printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
pvr = get_pvr();
fam = PVR_FAM(pvr);
ver = PVR_VER(pvr);
major = PVR_MAJ(pvr);
minor = PVR_MIN(pvr);
printf("Core: ");
switch (fam) {
case PVR_FAM(PVR_85xx):
puts("E500");
break;
default:
puts("Unknown");
break;
}
printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
get_sys_info(&sysinfo);
puts("Clock Configuration:\n");
printf(" CPU:%4lu MHz, ", DIV_ROUND_UP(sysinfo.freqProcessor,1000000));
printf("CCB:%4lu MHz,\n", DIV_ROUND_UP(sysinfo.freqSystemBus,1000000));
switch (ddr_ratio) {
case 0x0:
printf(" DDR:%4lu MHz (%lu MT/s data rate), ",
DIV_ROUND_UP(sysinfo.freqDDRBus,2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000));
break;
case 0x7:
printf(" DDR:%4lu MHz (%lu MT/s data rate) (Synchronous), ",
DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus, 1000000));
break;
default:
printf(" DDR:%4lu MHz (%lu MT/s data rate) (Asynchronous), ",
DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000));
break;
}
#if defined(CFG_LBC_LCRR)
lcrr = CFG_LBC_LCRR;
#else
{
volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
lcrr = lbc->lcrr;
}
#endif
clkdiv = lcrr & 0x0f;
if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
#if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544) || \
defined(CONFIG_MPC8572) || defined(CONFIG_MPC8536)
/*
* Yes, the entire PQ38 family use the same
* bit-representation for twice the clock divider values.
*/
clkdiv *= 2;
#endif
printf("LBC:%4lu MHz\n",
DIV_ROUND_UP(sysinfo.freqSystemBus, 1000000) / clkdiv);
} else {
printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr);
}
#ifdef CONFIG_CPM2
printf("CPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
#endif
puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
return 0;
}
static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
extern int enable_cpu_a011_workaround;
#endif
__maybe_unused u32 svr = get_svr();
#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
if (IS_SVR_REV(svr, 1, 0)) {
switch (SVR_SOC_VER(svr)) {
case SVR_P1013:
case SVR_P1022:
puts("Work-around for Erratum SATA A001 enabled\n");
}
}
#endif
#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8)
puts("Work-around for Erratum SERDES8 enabled\n");
#endif
#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9)
puts("Work-around for Erratum SERDES9 enabled\n");
#endif
#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES_A005)
puts("Work-around for Erratum SERDES-A005 enabled\n");
#endif
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
if (SVR_MAJ(svr) < 3)
puts("Work-around for Erratum CPU22 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
/*
* NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
* also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
* The SVR has been checked by cpu_init_r().
*/
if (enable_cpu_a011_workaround)
puts("Work-around for Erratum CPU-A011 enabled\n");
#endif
#if defined(CONFIG_SYS_FSL_ERRATUM_CPU_A003999)
puts("Work-around for Erratum CPU-A003999 enabled\n");
#endif
#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_A003474)
puts("Work-around for Erratum DDR-A003474 enabled\n");
#endif
#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
puts("Work-around for DDR MSYNC_IN Erratum enabled\n");
#endif
#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC111)
puts("Work-around for Erratum ESDHC111 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A004468
puts("Work-around for Erratum A004468 enabled\n");
#endif
#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC135)
puts("Work-around for Erratum ESDHC135 enabled\n");
#endif
#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC13)
if (SVR_MAJ(svr) < 3)
puts("Work-around for Erratum ESDHC13 enabled\n");
#endif
#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC_A001)
puts("Work-around for Erratum ESDHC-A001 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
puts("Work-around for Erratum CPC-A002 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
puts("Work-around for Erratum CPC-A003 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_ELBC_A001
puts("Work-around for Erratum ELBC-A001 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
puts("Work-around for Erratum DDR-A003 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115
puts("Work-around for Erratum DDR115 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
puts("Work-around for Erratum DDR111 enabled\n");
puts("Work-around for Erratum DDR134 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769
puts("Work-around for Erratum IFC-A002769 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
puts("Work-around for Erratum P1010-A003549 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
puts("Work-around for Erratum IFC A-003399 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
puts("Work-around for Erratum NMG DDR120 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
puts("Work-around for Erratum NMG_LBC103 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
puts("Work-around for Erratum NMG ETSEC129 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A004508
puts("Work-around for Erratum A004508 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A004510
puts("Work-around for Erratum A004510 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
puts("Work-around for Erratum SRIO-A004034 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A_004934
puts("Work-around for Erratum A004934 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A005871
if (IS_SVR_REV(svr, 1, 0))
puts("Work-around for Erratum A005871 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A006475
if (SVR_MAJ(get_svr()) == 1)
puts("Work-around for Erratum A006475 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A006384
if (SVR_MAJ(get_svr()) == 1)
puts("Work-around for Erratum A006384 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A004849
/* This work-around is implemented in PBI, so just check for it */
check_erratum_a4849(svr);
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A004580
/* This work-around is implemented in PBI, so just check for it */
check_erratum_a4580(svr);
#endif
#ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
puts("Work-around for Erratum PCIe-A003 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_USB14
puts("Work-around for Erratum USB14 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A007186
if (has_erratum_a007186())
puts("Work-around for Erratum A007186 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A006593
puts("Work-around for Erratum A006593 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A006379
if (has_erratum_a006379())
puts("Work-around for Erratum A006379 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
if (IS_SVR_REV(svr, 1, 0))
puts("Work-around for Erratum A003571 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A005812
puts("Work-around for Erratum A-005812 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A005125
puts("Work-around for Erratum A005125 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A007075
if (has_erratum_a007075())
puts("Work-around for Erratum A007075 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A007798
if (has_erratum_a007798())
puts("Work-around for Erratum A007798 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A004477
if (has_erratum_a004477())
puts("Work-around for Erratum A004477 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447
if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) ||
(SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV))
puts("Work-around for Erratum I2C-A004447 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
if (has_erratum_a006261())
puts("Work-around for Erratum A006261 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
check_erratum_a007212();
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A005434
puts("Work-around for Erratum A-005434 enabled\n");
#endif
#if defined(CONFIG_SYS_FSL_ERRATUM_A008044) && \
defined(CONFIG_A008044_WORKAROUND)
if (IS_SVR_REV(svr, 1, 0))
puts("Work-around for Erratum A-008044 enabled\n");
#endif
#if defined(CONFIG_SYS_FSL_B4860QDS_XFI_ERR) && defined(CONFIG_B4860QDS)
puts("Work-around for Erratum XFI on B4860QDS enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A009663
puts("Work-around for Erratum A009663 enabled\n");
#endif
return 0;
}
int
checkcpu(void)
{
sys_info_t sysinfo;
uint pvr, svr;
uint ver;
uint major, minor;
uint lcrr; /* local bus clock ratio register */
uint clkdiv; /* clock divider portion of lcrr */
puts("Freescale PowerPC\n");
pvr = get_pvr();
ver = PVR_VER(pvr);
major = PVR_MAJ(pvr);
minor = PVR_MIN(pvr);
puts("CPU:\n");
puts(" Core: ");
switch (ver) {
case PVR_VER(PVR_86xx):
puts("E600");
break;
default:
puts("Unknown");
break;
}
printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
svr = get_svr();
ver = SVR_VER(svr);
major = SVR_MAJ(svr);
minor = SVR_MIN(svr);
puts(" System: ");
switch (ver) {
case SVR_8641:
if (SVR_SUBVER(svr) == 1) {
puts("8641D");
} else {
puts("8641");
}
break;
default:
puts("Unknown");
break;
}
printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
get_sys_info(&sysinfo);
puts(" Clocks: ");
printf("CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000);
printf("MPX:%4lu MHz, ", sysinfo.freqSystemBus / 1000000);
printf("DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000);
#if defined(CFG_LBC_LCRR)
lcrr = CFG_LBC_LCRR;
#else
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile ccsr_lbc_t *lbc = &immap->im_lbc;
lcrr = lbc->lcrr;
}
#endif
clkdiv = lcrr & 0x0f;
if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
printf("LBC:%4lu MHz\n",
sysinfo.freqSystemBus / 1000000 / clkdiv);
} else {
printf(" LBC: unknown (lcrr: 0x%08x)\n", lcrr);
}
puts(" L2: ");
if (get_l2cr() & 0x80000000)
puts("Enabled\n");
else
puts("Disabled\n");
return 0;
}
void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
unsigned int ctrl_num, int step)
{
unsigned int i;
struct ccsr_ddr __iomem *ddr =
(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
#if defined(CONFIG_SYS_FSL_ERRATUM_NMG_DDR120) && defined(CONFIG_MPC85xx)
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
uint svr;
#endif
if (ctrl_num) {
printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
return;
}
#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
/*
* Set the DDR IO receiver to an acceptable bias point.
* Fixed in Rev 2.1.
*/
svr = get_svr();
if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) {
if ((regs->ddr_sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) ==
SDRAM_CFG_SDRAM_TYPE_DDR2)
out_be32(&gur->ddrioovcr, 0x90000000);
else
out_be32(&gur->ddrioovcr, 0xA8000000);
}
#endif
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
if (i == 0) {
out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
out_be32(&ddr->cs0_config, regs->cs[i].config);
} else if (i == 1) {
out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
out_be32(&ddr->cs1_config, regs->cs[i].config);
} else if (i == 2) {
out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
out_be32(&ddr->cs2_config, regs->cs[i].config);
} else if (i == 3) {
out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
out_be32(&ddr->cs3_config, regs->cs[i].config);
}
}
out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
out_be32(&ddr->init_addr, regs->ddr_init_addr);
out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
/*
* 200 painful micro-seconds must elapse between
* the DDR clock setup and the DDR config enable.
*/
udelay(200);
asm volatile("sync;isync");
out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
/* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
while (in_be32(&ddr->sdram_cfg_2) & 0x10) {
udelay(10000); /* throttle polling rate */
}
}
/*
* Initialize Local Bus
*/
void local_bus_init (void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint lbc_mhz = get_lbc_clock () / 1000000;
#ifdef CONFIG_MPC8548
uint svr = get_svr ();
uint lcrr;
/*
* MPC revision < 2.0
* According to MPC8548E_Device_Errata Rev. L, Erratum LBIU1:
* Modify engineering use only register at address 0xE_0F20.
* "1. Read register at offset 0xE_0F20
* 2. And value with 0x0000_FFFF
* 3. OR result with 0x0000_0004
* 4. Write result back to offset 0xE_0F20."
*
* According to MPC8548E_Device_Errata Rev. L, Erratum LBIU2:
* Modify engineering use only register at address 0xE_0F20.
* "1. Read register at offset 0xE_0F20
* 2. And value with 0xFFFF_FFDF
* 3. Write result back to offset 0xE_0F20."
*
* Since it is the same register, we do the modification in one step.
*/
if (SVR_MAJ (svr) < 2) {
uint dummy = gur->lbiuiplldcr1;
dummy &= 0x0000FFDF;
dummy |= 0x00000004;
gur->lbiuiplldcr1 = dummy;
}
lcrr = CONFIG_SYS_LBC_LCRR;
/*
* Local Bus Clock > 83.3 MHz. According to timing
* specifications set LCRR[EADC] to 2 delay cycles.
*/
if (lbc_mhz > 83) {
lcrr &= ~LCRR_EADC;
lcrr |= LCRR_EADC_2;
}
/*
* According to MPC8548ERMAD Rev. 1.3, 13.3.1.16, 13-30
* disable PLL bypass for Local Bus Clock > 83 MHz.
*/
if (lbc_mhz >= 66)
lcrr &= (~LCRR_DBYP); /* DLL Enabled */
else
lcrr |= LCRR_DBYP; /* DLL Bypass */
lbc->lcrr = lcrr;
asm ("sync;isync;msync");
/*
* According to MPC8548ERMAD Rev.1.3 read back LCRR
* and terminate with isync
*/
lcrr = lbc->lcrr;
asm ("isync;");
/* let DLL stabilize */
udelay (500);
#else /* !CONFIG_MPC8548 */
/*
* Errata LBC11.
* Fix Local Bus clock glitch when DLL is enabled.
*
* If localbus freq is < 66MHz, DLL bypass mode must be used.
* If localbus freq is > 133MHz, DLL can be safely enabled.
* Between 66 and 133, the DLL is enabled with an override workaround.
*/
if (lbc_mhz < 66) {
lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */
lbc->ltedr = LTEDR_BMD | LTEDR_PARD | LTEDR_WPD | LTEDR_WARA |
LTEDR_RAWA | LTEDR_CSD; /* Disable all error checking */
} else if (lbc_mhz >= 133) {
lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */
} else {
/*
* On REV1 boards, need to change CLKDIV before enable DLL.
* Default CLKDIV is 8, change it to 4 temporarily.
*/
uint pvr = get_pvr ();
uint temp_lbcdll = 0;
if (pvr == PVR_85xx_REV1) {
/* FIXME: Justify the high bit here. */
lbc->lcrr = 0x10000004;
}
lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */
udelay (200);
/*
* Sample LBC DLL ctrl reg, upshift it to set the
* override bits.
*/
temp_lbcdll = gur->lbcdllcr;
gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
asm ("sync;isync;msync");
}
#endif /* !CONFIG_MPC8548 */
#ifdef CONFIG_CAN_DRIVER
/*
* According to timing specifications EAD must be
* set if Local Bus Clock is > 83 MHz.
*/
if (lbc_mhz > 83)
set_lbc_or(2, CONFIG_SYS_OR2_CAN | OR_UPM_EAD);
else
set_lbc_or(2, CONFIG_SYS_OR2_CAN);
set_lbc_br(2, CONFIG_SYS_BR2_CAN);
/* LGPL4 is UPWAIT */
out_be32(&lbc->mcmr, MxMR_DSx_3_CYCL | MxMR_GPL_x4DIS | MxMR_WLFx_3X);
/* Initialize UPMC for CAN: single read */
upmc_write (0x00, 0xFFFFED00);
upmc_write (0x01, 0xCCFFCC00);
upmc_write (0x02, 0x00FFCF00);
upmc_write (0x03, 0x00FFCF00);
upmc_write (0x04, 0x00FFDC00);
upmc_write (0x05, 0x00FFCF00);
upmc_write (0x06, 0x00FFED00);
upmc_write (0x07, 0x3FFFCC07);
/* Initialize UPMC for CAN: single write */
upmc_write (0x18, 0xFFFFED00);
upmc_write (0x19, 0xCCFFEC00);
upmc_write (0x1A, 0x00FFED80);
upmc_write (0x1B, 0x00FFED80);
upmc_write (0x1C, 0x00FFFC00);
upmc_write (0x1D, 0x0FFFEC00);
upmc_write (0x1E, 0x0FFFEF00);
upmc_write (0x1F, 0x3FFFEC05);
#endif /* CONFIG_CAN_DRIVER */
}
int
checkcpu(void)
{
sys_info_t sysinfo;
uint pvr, svr;
uint major, minor;
char buf1[32], buf2[32];
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile ccsr_gur_t *gur = &immap->im_gur;
struct cpu_type *cpu;
uint msscr0 = mfspr(MSSCR0);
svr = get_svr();
major = SVR_MAJ(svr);
minor = SVR_MIN(svr);
if (cpu_numcores() > 1) {
#ifndef CONFIG_MP
puts("Unicore software on multiprocessor system!!\n"
"To enable mutlticore build define CONFIG_MP\n");
#endif
}
puts("CPU: ");
cpu = gd->arch.cpu;
puts(cpu->name);
printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
puts("Core: ");
pvr = get_pvr();
major = PVR_E600_MAJ(pvr);
minor = PVR_E600_MIN(pvr);
printf("e600 Core %d", (msscr0 & 0x20) ? 1 : 0);
if (gur->pordevsr & MPC86xx_PORDEVSR_CORE1TE)
puts("\n Core1Translation Enabled");
debug(" (MSSCR0=%x, PORDEVSR=%x)", msscr0, gur->pordevsr);
printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
get_sys_info(&sysinfo);
puts("Clock Configuration:\n");
printf(" CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freqProcessor));
printf("MPX:%-4s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
printf(" DDR:%-4s MHz (%s MT/s data rate), ",
strmhz(buf1, sysinfo.freqSystemBus / 2),
strmhz(buf2, sysinfo.freqSystemBus));
if (sysinfo.freqLocalBus > LCRR_CLKDIV) {
printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
} else {
printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
sysinfo.freqLocalBus);
}
puts("L1: D-cache 32 KB enabled\n");
puts(" I-cache 32 KB enabled\n");
puts("L2: ");
if (get_l2cr() & 0x80000000) {
#if defined(CONFIG_MPC8610)
puts("256");
#elif defined(CONFIG_MPC8641)
puts("512");
#endif
puts(" KB enabled\n");
} else {
puts("Disabled\n");
}
return 0;
}
